0017-Implement-instruction-patterns-for-ZBA-extension.patch 6.3 KB

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  1. From 3b7112d4b773768af0da81e7c9575fc9a0d90062 Mon Sep 17 00:00:00 2001
  2. From: "yilun.xie" <yilun.xie@starfivetech.com>
  3. Date: Thu, 18 Nov 2021 14:42:41 +0800
  4. Subject: [PATCH 17/26] Implement instruction patterns for ZBA extension
  5. ---
  6. gcc/config/riscv/riscv.md | 12 +++++--
  7. gcc/testsuite/gcc.target/riscv/zba-adduw.c | 12 +++++++
  8. .../gcc.target/riscv/zba-shNadd-01.c | 19 ++++++++++++
  9. .../gcc.target/riscv/zba-shNadd-02.c | 19 ++++++++++++
  10. .../gcc.target/riscv/zba-shNadd-03.c | 31 +++++++++++++++++++
  11. gcc/testsuite/gcc.target/riscv/zba-slliuw.c | 11 +++++++
  12. gcc/testsuite/gcc.target/riscv/zba-zextw.c | 10 ++++++
  13. 7 files changed, 111 insertions(+), 3 deletions(-)
  14. create mode 100644 gcc/testsuite/gcc.target/riscv/zba-adduw.c
  15. create mode 100644 gcc/testsuite/gcc.target/riscv/zba-shNadd-01.c
  16. create mode 100644 gcc/testsuite/gcc.target/riscv/zba-shNadd-02.c
  17. create mode 100644 gcc/testsuite/gcc.target/riscv/zba-shNadd-03.c
  18. create mode 100644 gcc/testsuite/gcc.target/riscv/zba-slliuw.c
  19. create mode 100644 gcc/testsuite/gcc.target/riscv/zba-zextw.c
  20. diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
  21. index 26003ac5df7..34702af3aff 100644
  22. --- a/gcc/config/riscv/riscv.md
  23. +++ b/gcc/config/riscv/riscv.md
  24. @@ -1057,11 +1057,16 @@
  25. ;; Extension insns.
  26. -(define_insn_and_split "zero_extendsidi2"
  27. +(define_expand "zero_extendsidi2"
  28. + [(set (match_operand:DI 0 "register_operand")
  29. + (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand")))]
  30. + "TARGET_64BIT")
  31. +
  32. +(define_insn_and_split "*zero_extendsidi2_internal"
  33. [(set (match_operand:DI 0 "register_operand" "=r,r")
  34. (zero_extend:DI
  35. (match_operand:SI 1 "nonimmediate_operand" " r,m")))]
  36. - "TARGET_64BIT"
  37. + "TARGET_64BIT && !(TARGET_ZBA || TARGET_ZBB)"
  38. "@
  39. #
  40. lwu\t%0,%1"
  41. @@ -1833,7 +1838,7 @@
  42. (match_operand:QI 2 "immediate_operand" "I"))
  43. (match_operand 3 "immediate_operand" "")))
  44. (clobber (match_scratch:DI 4 "=&r"))]
  45. - "TARGET_64BIT
  46. + "TARGET_64BIT && !TARGET_ZBA
  47. && ((INTVAL (operands[3]) >> INTVAL (operands[2])) == 0xffffffff)"
  48. "#"
  49. "&& reload_completed"
  50. @@ -2642,6 +2647,7 @@
  51. "<load>\t%3, %1\;<load>\t%0, %2\;xor\t%0, %3, %0\;li\t%3, 0"
  52. [(set_attr "length" "12")])
  53. +(include "bitmanip.md")
  54. (include "sync.md")
  55. (include "peephole.md")
  56. (include "pic.md")
  57. diff --git a/gcc/testsuite/gcc.target/riscv/zba-adduw.c b/gcc/testsuite/gcc.target/riscv/zba-adduw.c
  58. new file mode 100644
  59. index 00000000000..480d62c884d
  60. --- /dev/null
  61. +++ b/gcc/testsuite/gcc.target/riscv/zba-adduw.c
  62. @@ -0,0 +1,12 @@
  63. +/* { dg-do compile } */
  64. +/* { dg-options "-march=rv64gc_zba_zbs -mabi=lp64 -O2" } */
  65. +
  66. +int foo(int n, unsigned char *arr, unsigned y){
  67. + int s = 0;
  68. + unsigned x = 0;
  69. + for (;x<n;x++)
  70. + s += arr[x+y];
  71. + return s;
  72. +}
  73. +
  74. +/* { dg-final { scan-assembler "add.uw" } } */
  75. \ No newline at end of file
  76. diff --git a/gcc/testsuite/gcc.target/riscv/zba-shNadd-01.c b/gcc/testsuite/gcc.target/riscv/zba-shNadd-01.c
  77. new file mode 100644
  78. index 00000000000..9893fb6c451
  79. --- /dev/null
  80. +++ b/gcc/testsuite/gcc.target/riscv/zba-shNadd-01.c
  81. @@ -0,0 +1,19 @@
  82. +/* { dg-do compile } */
  83. +/* { dg-options "-march=rv64gc_zba -mabi=lp64 -O2" } */
  84. +
  85. +long test_1(long a, long b)
  86. +{
  87. + return a + (b << 1);
  88. +}
  89. +long test_2(long a, long b)
  90. +{
  91. + return a + (b << 2);
  92. +}
  93. +long test_3(long a, long b)
  94. +{
  95. + return a + (b << 3);
  96. +}
  97. +
  98. +/* { dg-final { scan-assembler-times "sh1add" 1 } } */
  99. +/* { dg-final { scan-assembler-times "sh2add" 1 } } */
  100. +/* { dg-final { scan-assembler-times "sh3add" 1 } } */
  101. \ No newline at end of file
  102. diff --git a/gcc/testsuite/gcc.target/riscv/zba-shNadd-02.c b/gcc/testsuite/gcc.target/riscv/zba-shNadd-02.c
  103. new file mode 100644
  104. index 00000000000..f025849dc27
  105. --- /dev/null
  106. +++ b/gcc/testsuite/gcc.target/riscv/zba-shNadd-02.c
  107. @@ -0,0 +1,19 @@
  108. +/* { dg-do compile } */
  109. +/* { dg-options "-march=rv32gc_zba -mabi=ilp32 -O2" } */
  110. +
  111. +long test_1(long a, long b)
  112. +{
  113. + return a + (b << 1);
  114. +}
  115. +long test_2(long a, long b)
  116. +{
  117. + return a + (b << 2);
  118. +}
  119. +long test_3(long a, long b)
  120. +{
  121. + return a + (b << 3);
  122. +}
  123. +
  124. +/* { dg-final { scan-assembler-times "sh1add" 1 } } */
  125. +/* { dg-final { scan-assembler-times "sh2add" 1 } } */
  126. +/* { dg-final { scan-assembler-times "sh3add" 1 } } */
  127. \ No newline at end of file
  128. diff --git a/gcc/testsuite/gcc.target/riscv/zba-shNadd-03.c b/gcc/testsuite/gcc.target/riscv/zba-shNadd-03.c
  129. new file mode 100644
  130. index 00000000000..ef75e7fc486
  131. --- /dev/null
  132. +++ b/gcc/testsuite/gcc.target/riscv/zba-shNadd-03.c
  133. @@ -0,0 +1,31 @@
  134. +/* { dg-do compile } */
  135. +/* { dg-options "-march=rv64gc_zba -mabi=lp64 -O2" } */
  136. +
  137. +/* RV64 only. */
  138. +int foos(short *x, int n){
  139. + return x[n];
  140. +}
  141. +int fooi(int *x, int n){
  142. + return x[n];
  143. +}
  144. +int fooll(long long *x, int n){
  145. + return x[n];
  146. +}
  147. +
  148. +/* RV64 only. */
  149. +int ufoos(short *x, unsigned int n){
  150. + return x[n];
  151. +}
  152. +int ufooi(int *x, unsigned int n){
  153. + return x[n];
  154. +}
  155. +int ufooll(long long *x, unsigned int n){
  156. + return x[n];
  157. +}
  158. +
  159. +/* { dg-final { scan-assembler-times "sh1add\t" 1 } } */
  160. +/* { dg-final { scan-assembler-times "sh2add\t" 1 } } */
  161. +/* { dg-final { scan-assembler-times "sh3add\t" 1 } } */
  162. +/* { dg-final { scan-assembler-times "sh3add.uw" 1 } } */
  163. +/* { dg-final { scan-assembler-times "sh3add.uw" 1 } } */
  164. +/* { dg-final { scan-assembler-times "sh3add.uw" 1 } } */
  165. \ No newline at end of file
  166. diff --git a/gcc/testsuite/gcc.target/riscv/zba-slliuw.c b/gcc/testsuite/gcc.target/riscv/zba-slliuw.c
  167. new file mode 100644
  168. index 00000000000..55ebc1c81ce
  169. --- /dev/null
  170. +++ b/gcc/testsuite/gcc.target/riscv/zba-slliuw.c
  171. @@ -0,0 +1,11 @@
  172. +/* { dg-do compile } */
  173. +/* { dg-options "-march=rv64gc_zba -mabi=lp64 -O2" } */
  174. +
  175. +long
  176. +foo (long i)
  177. +{
  178. + return (long)(unsigned int)i << 10;
  179. +}
  180. +/* XXX: This pattern need combine improvement or intermediate instruction
  181. + * from zbs. */
  182. +/* { dg-final { scan-assembler-not "slli.uw" } } */
  183. \ No newline at end of file
  184. diff --git a/gcc/testsuite/gcc.target/riscv/zba-zextw.c b/gcc/testsuite/gcc.target/riscv/zba-zextw.c
  185. new file mode 100644
  186. index 00000000000..e8cccd0e374
  187. --- /dev/null
  188. +++ b/gcc/testsuite/gcc.target/riscv/zba-zextw.c
  189. @@ -0,0 +1,10 @@
  190. +/* { dg-do compile } */
  191. +/* { dg-options "-march=rv64gc_zba_zbs -mabi=lp64 -O2" } */
  192. +
  193. +long
  194. +foo (long i)
  195. +{
  196. + return (long)(unsigned int)i;
  197. +}
  198. +/* XXX: This pattern require combine improvement. */
  199. +/* { dg-final { scan-assembler-not "slli.uw" } } */
  200. \ No newline at end of file
  201. --
  202. 2.33.1