From 3b7112d4b773768af0da81e7c9575fc9a0d90062 Mon Sep 17 00:00:00 2001 From: "yilun.xie" Date: Thu, 18 Nov 2021 14:42:41 +0800 Subject: [PATCH 17/26] Implement instruction patterns for ZBA extension --- gcc/config/riscv/riscv.md | 12 +++++-- gcc/testsuite/gcc.target/riscv/zba-adduw.c | 12 +++++++ .../gcc.target/riscv/zba-shNadd-01.c | 19 ++++++++++++ .../gcc.target/riscv/zba-shNadd-02.c | 19 ++++++++++++ .../gcc.target/riscv/zba-shNadd-03.c | 31 +++++++++++++++++++ gcc/testsuite/gcc.target/riscv/zba-slliuw.c | 11 +++++++ gcc/testsuite/gcc.target/riscv/zba-zextw.c | 10 ++++++ 7 files changed, 111 insertions(+), 3 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/zba-adduw.c create mode 100644 gcc/testsuite/gcc.target/riscv/zba-shNadd-01.c create mode 100644 gcc/testsuite/gcc.target/riscv/zba-shNadd-02.c create mode 100644 gcc/testsuite/gcc.target/riscv/zba-shNadd-03.c create mode 100644 gcc/testsuite/gcc.target/riscv/zba-slliuw.c create mode 100644 gcc/testsuite/gcc.target/riscv/zba-zextw.c diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index 26003ac5df7..34702af3aff 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -1057,11 +1057,16 @@ ;; Extension insns. -(define_insn_and_split "zero_extendsidi2" +(define_expand "zero_extendsidi2" + [(set (match_operand:DI 0 "register_operand") + (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand")))] + "TARGET_64BIT") + +(define_insn_and_split "*zero_extendsidi2_internal" [(set (match_operand:DI 0 "register_operand" "=r,r") (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" " r,m")))] - "TARGET_64BIT" + "TARGET_64BIT && !(TARGET_ZBA || TARGET_ZBB)" "@ # lwu\t%0,%1" @@ -1833,7 +1838,7 @@ (match_operand:QI 2 "immediate_operand" "I")) (match_operand 3 "immediate_operand" ""))) (clobber (match_scratch:DI 4 "=&r"))] - "TARGET_64BIT + "TARGET_64BIT && !TARGET_ZBA && ((INTVAL (operands[3]) >> INTVAL (operands[2])) == 0xffffffff)" "#" "&& reload_completed" @@ -2642,6 +2647,7 @@ "\t%3, %1\;\t%0, %2\;xor\t%0, %3, %0\;li\t%3, 0" [(set_attr "length" "12")]) +(include "bitmanip.md") (include "sync.md") (include "peephole.md") (include "pic.md") diff --git a/gcc/testsuite/gcc.target/riscv/zba-adduw.c b/gcc/testsuite/gcc.target/riscv/zba-adduw.c new file mode 100644 index 00000000000..480d62c884d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/zba-adduw.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zba_zbs -mabi=lp64 -O2" } */ + +int foo(int n, unsigned char *arr, unsigned y){ + int s = 0; + unsigned x = 0; + for (;x