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- From 3b7112d4b773768af0da81e7c9575fc9a0d90062 Mon Sep 17 00:00:00 2001
- From: "yilun.xie" <yilun.xie@starfivetech.com>
- Date: Thu, 18 Nov 2021 14:42:41 +0800
- Subject: [PATCH 17/26] Implement instruction patterns for ZBA extension
- ---
- gcc/config/riscv/riscv.md | 12 +++++--
- gcc/testsuite/gcc.target/riscv/zba-adduw.c | 12 +++++++
- .../gcc.target/riscv/zba-shNadd-01.c | 19 ++++++++++++
- .../gcc.target/riscv/zba-shNadd-02.c | 19 ++++++++++++
- .../gcc.target/riscv/zba-shNadd-03.c | 31 +++++++++++++++++++
- gcc/testsuite/gcc.target/riscv/zba-slliuw.c | 11 +++++++
- gcc/testsuite/gcc.target/riscv/zba-zextw.c | 10 ++++++
- 7 files changed, 111 insertions(+), 3 deletions(-)
- create mode 100644 gcc/testsuite/gcc.target/riscv/zba-adduw.c
- create mode 100644 gcc/testsuite/gcc.target/riscv/zba-shNadd-01.c
- create mode 100644 gcc/testsuite/gcc.target/riscv/zba-shNadd-02.c
- create mode 100644 gcc/testsuite/gcc.target/riscv/zba-shNadd-03.c
- create mode 100644 gcc/testsuite/gcc.target/riscv/zba-slliuw.c
- create mode 100644 gcc/testsuite/gcc.target/riscv/zba-zextw.c
- diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
- index 26003ac5df7..34702af3aff 100644
- --- a/gcc/config/riscv/riscv.md
- +++ b/gcc/config/riscv/riscv.md
- @@ -1057,11 +1057,16 @@
-
- ;; Extension insns.
-
- -(define_insn_and_split "zero_extendsidi2"
- +(define_expand "zero_extendsidi2"
- + [(set (match_operand:DI 0 "register_operand")
- + (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand")))]
- + "TARGET_64BIT")
- +
- +(define_insn_and_split "*zero_extendsidi2_internal"
- [(set (match_operand:DI 0 "register_operand" "=r,r")
- (zero_extend:DI
- (match_operand:SI 1 "nonimmediate_operand" " r,m")))]
- - "TARGET_64BIT"
- + "TARGET_64BIT && !(TARGET_ZBA || TARGET_ZBB)"
- "@
- #
- lwu\t%0,%1"
- @@ -1833,7 +1838,7 @@
- (match_operand:QI 2 "immediate_operand" "I"))
- (match_operand 3 "immediate_operand" "")))
- (clobber (match_scratch:DI 4 "=&r"))]
- - "TARGET_64BIT
- + "TARGET_64BIT && !TARGET_ZBA
- && ((INTVAL (operands[3]) >> INTVAL (operands[2])) == 0xffffffff)"
- "#"
- "&& reload_completed"
- @@ -2642,6 +2647,7 @@
- "<load>\t%3, %1\;<load>\t%0, %2\;xor\t%0, %3, %0\;li\t%3, 0"
- [(set_attr "length" "12")])
-
- +(include "bitmanip.md")
- (include "sync.md")
- (include "peephole.md")
- (include "pic.md")
- diff --git a/gcc/testsuite/gcc.target/riscv/zba-adduw.c b/gcc/testsuite/gcc.target/riscv/zba-adduw.c
- new file mode 100644
- index 00000000000..480d62c884d
- --- /dev/null
- +++ b/gcc/testsuite/gcc.target/riscv/zba-adduw.c
- @@ -0,0 +1,12 @@
- +/* { dg-do compile } */
- +/* { dg-options "-march=rv64gc_zba_zbs -mabi=lp64 -O2" } */
- +
- +int foo(int n, unsigned char *arr, unsigned y){
- + int s = 0;
- + unsigned x = 0;
- + for (;x<n;x++)
- + s += arr[x+y];
- + return s;
- +}
- +
- +/* { dg-final { scan-assembler "add.uw" } } */
- \ No newline at end of file
- diff --git a/gcc/testsuite/gcc.target/riscv/zba-shNadd-01.c b/gcc/testsuite/gcc.target/riscv/zba-shNadd-01.c
- new file mode 100644
- index 00000000000..9893fb6c451
- --- /dev/null
- +++ b/gcc/testsuite/gcc.target/riscv/zba-shNadd-01.c
- @@ -0,0 +1,19 @@
- +/* { dg-do compile } */
- +/* { dg-options "-march=rv64gc_zba -mabi=lp64 -O2" } */
- +
- +long test_1(long a, long b)
- +{
- + return a + (b << 1);
- +}
- +long test_2(long a, long b)
- +{
- + return a + (b << 2);
- +}
- +long test_3(long a, long b)
- +{
- + return a + (b << 3);
- +}
- +
- +/* { dg-final { scan-assembler-times "sh1add" 1 } } */
- +/* { dg-final { scan-assembler-times "sh2add" 1 } } */
- +/* { dg-final { scan-assembler-times "sh3add" 1 } } */
- \ No newline at end of file
- diff --git a/gcc/testsuite/gcc.target/riscv/zba-shNadd-02.c b/gcc/testsuite/gcc.target/riscv/zba-shNadd-02.c
- new file mode 100644
- index 00000000000..f025849dc27
- --- /dev/null
- +++ b/gcc/testsuite/gcc.target/riscv/zba-shNadd-02.c
- @@ -0,0 +1,19 @@
- +/* { dg-do compile } */
- +/* { dg-options "-march=rv32gc_zba -mabi=ilp32 -O2" } */
- +
- +long test_1(long a, long b)
- +{
- + return a + (b << 1);
- +}
- +long test_2(long a, long b)
- +{
- + return a + (b << 2);
- +}
- +long test_3(long a, long b)
- +{
- + return a + (b << 3);
- +}
- +
- +/* { dg-final { scan-assembler-times "sh1add" 1 } } */
- +/* { dg-final { scan-assembler-times "sh2add" 1 } } */
- +/* { dg-final { scan-assembler-times "sh3add" 1 } } */
- \ No newline at end of file
- diff --git a/gcc/testsuite/gcc.target/riscv/zba-shNadd-03.c b/gcc/testsuite/gcc.target/riscv/zba-shNadd-03.c
- new file mode 100644
- index 00000000000..ef75e7fc486
- --- /dev/null
- +++ b/gcc/testsuite/gcc.target/riscv/zba-shNadd-03.c
- @@ -0,0 +1,31 @@
- +/* { dg-do compile } */
- +/* { dg-options "-march=rv64gc_zba -mabi=lp64 -O2" } */
- +
- +/* RV64 only. */
- +int foos(short *x, int n){
- + return x[n];
- +}
- +int fooi(int *x, int n){
- + return x[n];
- +}
- +int fooll(long long *x, int n){
- + return x[n];
- +}
- +
- +/* RV64 only. */
- +int ufoos(short *x, unsigned int n){
- + return x[n];
- +}
- +int ufooi(int *x, unsigned int n){
- + return x[n];
- +}
- +int ufooll(long long *x, unsigned int n){
- + return x[n];
- +}
- +
- +/* { dg-final { scan-assembler-times "sh1add\t" 1 } } */
- +/* { dg-final { scan-assembler-times "sh2add\t" 1 } } */
- +/* { dg-final { scan-assembler-times "sh3add\t" 1 } } */
- +/* { dg-final { scan-assembler-times "sh3add.uw" 1 } } */
- +/* { dg-final { scan-assembler-times "sh3add.uw" 1 } } */
- +/* { dg-final { scan-assembler-times "sh3add.uw" 1 } } */
- \ No newline at end of file
- diff --git a/gcc/testsuite/gcc.target/riscv/zba-slliuw.c b/gcc/testsuite/gcc.target/riscv/zba-slliuw.c
- new file mode 100644
- index 00000000000..55ebc1c81ce
- --- /dev/null
- +++ b/gcc/testsuite/gcc.target/riscv/zba-slliuw.c
- @@ -0,0 +1,11 @@
- +/* { dg-do compile } */
- +/* { dg-options "-march=rv64gc_zba -mabi=lp64 -O2" } */
- +
- +long
- +foo (long i)
- +{
- + return (long)(unsigned int)i << 10;
- +}
- +/* XXX: This pattern need combine improvement or intermediate instruction
- + * from zbs. */
- +/* { dg-final { scan-assembler-not "slli.uw" } } */
- \ No newline at end of file
- diff --git a/gcc/testsuite/gcc.target/riscv/zba-zextw.c b/gcc/testsuite/gcc.target/riscv/zba-zextw.c
- new file mode 100644
- index 00000000000..e8cccd0e374
- --- /dev/null
- +++ b/gcc/testsuite/gcc.target/riscv/zba-zextw.c
- @@ -0,0 +1,10 @@
- +/* { dg-do compile } */
- +/* { dg-options "-march=rv64gc_zba_zbs -mabi=lp64 -O2" } */
- +
- +long
- +foo (long i)
- +{
- + return (long)(unsigned int)i;
- +}
- +/* XXX: This pattern require combine improvement. */
- +/* { dg-final { scan-assembler-not "slli.uw" } } */
- \ No newline at end of file
- --
- 2.33.1
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