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@@ -245,6 +245,22 @@ ASM_PFX(LoadMicrocodeDefault):
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cmp esp, 0
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jz ParamError
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+ ;
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+ ; If microcode already loaded before this function, exit this function with SUCCESS.
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+ ;
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+ mov ecx, MSR_IA32_BIOS_SIGN_ID
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+ xor eax, eax ; Clear EAX
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+ xor edx, edx ; Clear EDX
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+ wrmsr ; Load 0 to MSR at 8Bh
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+
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+ mov eax, 1
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+ cpuid
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+ mov ecx, MSR_IA32_BIOS_SIGN_ID
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+ rdmsr ; Get current microcode signature
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+ xor eax, eax
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+ test edx, edx
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+ jnz Exit2
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+
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; skip loading Microcode if the MicrocodeCodeSize is zero
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; and report error if size is less than 2k
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; first check UPD header revision
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@@ -330,7 +346,7 @@ CheckMainHeader:
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cmp ebx, dword [esi + MicrocodeHdr.MicrocodeHdrProcessor]
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jne LoadMicrocodeDefault1
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test edx, dword [esi + MicrocodeHdr.MicrocodeHdrFlags ]
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- jnz LoadCheck ; Jif signature and platform ID match
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+ jnz LoadMicrocode ; Jif signature and platform ID match
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LoadMicrocodeDefault1:
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; Check if extended header exists
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@@ -363,7 +379,7 @@ CheckExtSig:
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cmp dword [edi + ExtSig.ExtSigProcessor], ebx
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jne LoadMicrocodeDefault2
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test dword [edi + ExtSig.ExtSigFlags], edx
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- jnz LoadCheck ; Jif signature and platform ID match
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+ jnz LoadMicrocode ; Jif signature and platform ID match
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LoadMicrocodeDefault2:
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; Check if any more extended signatures exist
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add edi, ExtSig.size
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@@ -435,23 +451,7 @@ LoadMicrocodeDefault4:
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; Is valid Microcode start point ?
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cmp dword [esi + MicrocodeHdr.MicrocodeHdrVersion], 0ffffffffh
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jz Done
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-
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-LoadCheck:
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- ; Get the revision of the current microcode update loaded
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- mov ecx, MSR_IA32_BIOS_SIGN_ID
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- xor eax, eax ; Clear EAX
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- xor edx, edx ; Clear EDX
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- wrmsr ; Load 0 to MSR at 8Bh
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-
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- mov eax, 1
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- cpuid
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- mov ecx, MSR_IA32_BIOS_SIGN_ID
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- rdmsr ; Get current microcode signature
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-
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- ; Verify this microcode update is not already loaded
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- cmp dword [esi + MicrocodeHdr.MicrocodeHdrRevision], edx
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- je Continue
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-
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+ jmp CheckMainHeader
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LoadMicrocode:
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; EAX contains the linear address of the start of the Update Data
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; EDX contains zero
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@@ -465,10 +465,12 @@ LoadMicrocode:
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mov eax, 1
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cpuid
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-Continue:
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- jmp NextMicrocode
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-
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Done:
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+ mov ecx, MSR_IA32_BIOS_SIGN_ID
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+ xor eax, eax ; Clear EAX
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+ xor edx, edx ; Clear EDX
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+ wrmsr ; Load 0 to MSR at 8Bh
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+
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mov eax, 1
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cpuid
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mov ecx, MSR_IA32_BIOS_SIGN_ID
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