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IntelFsp2Pkg: LoadMicrocodeDefault() causing unnecessary delay.

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4391

FSP should support the scenario that CPU microcode already loaded
before calling LoadMicrocodeDefault(), in this case it should return
directly without spending more time.
Also the LoadMicrocodeDefault() should only attempt to load one version
of the microcode for current CPU and return directly without parsing
rest of the microcode in FV.

This patch also removed unnecessary LoadCheck code after supporting
CPU microcode already loaded scenario.

Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
Reviewed-by: Ted Kuo <ted.kuo@intel.com>
Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
Chasel Chiu 1 年之前
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当前提交
7df447930c
共有 2 个文件被更改,包括 48 次插入43 次删除
  1. 24 22
      IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm
  2. 24 21
      IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm

+ 24 - 22
IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm

@@ -245,6 +245,22 @@ ASM_PFX(LoadMicrocodeDefault):
    cmp    esp, 0
    cmp    esp, 0
    jz     ParamError
    jz     ParamError
 
 
+   ;
+   ; If microcode already loaded before this function, exit this function with SUCCESS.
+   ;
+   mov   ecx, MSR_IA32_BIOS_SIGN_ID
+   xor   eax, eax               ; Clear EAX
+   xor   edx, edx               ; Clear EDX
+   wrmsr                        ; Load 0 to MSR at 8Bh
+
+   mov   eax, 1
+   cpuid
+   mov   ecx, MSR_IA32_BIOS_SIGN_ID
+   rdmsr                         ; Get current microcode signature
+   xor   eax, eax
+   test  edx, edx
+   jnz   Exit2
+
    ; skip loading Microcode if the MicrocodeCodeSize is zero
    ; skip loading Microcode if the MicrocodeCodeSize is zero
    ; and report error if size is less than 2k
    ; and report error if size is less than 2k
    ; first check UPD header revision
    ; first check UPD header revision
@@ -330,7 +346,7 @@ CheckMainHeader:
    cmp   ebx, dword [esi + MicrocodeHdr.MicrocodeHdrProcessor]
    cmp   ebx, dword [esi + MicrocodeHdr.MicrocodeHdrProcessor]
    jne   LoadMicrocodeDefault1
    jne   LoadMicrocodeDefault1
    test  edx, dword [esi + MicrocodeHdr.MicrocodeHdrFlags ]
    test  edx, dword [esi + MicrocodeHdr.MicrocodeHdrFlags ]
-   jnz   LoadCheck  ; Jif signature and platform ID match
+   jnz   LoadMicrocode  ; Jif signature and platform ID match
 
 
 LoadMicrocodeDefault1:
 LoadMicrocodeDefault1:
    ; Check if extended header exists
    ; Check if extended header exists
@@ -363,7 +379,7 @@ CheckExtSig:
    cmp   dword [edi + ExtSig.ExtSigProcessor], ebx
    cmp   dword [edi + ExtSig.ExtSigProcessor], ebx
    jne   LoadMicrocodeDefault2
    jne   LoadMicrocodeDefault2
    test  dword [edi + ExtSig.ExtSigFlags], edx
    test  dword [edi + ExtSig.ExtSigFlags], edx
-   jnz   LoadCheck      ; Jif signature and platform ID match
+   jnz   LoadMicrocode      ; Jif signature and platform ID match
 LoadMicrocodeDefault2:
 LoadMicrocodeDefault2:
    ; Check if any more extended signatures exist
    ; Check if any more extended signatures exist
    add   edi, ExtSig.size
    add   edi, ExtSig.size
@@ -435,23 +451,7 @@ LoadMicrocodeDefault4:
    ; Is valid Microcode start point ?
    ; Is valid Microcode start point ?
    cmp   dword [esi + MicrocodeHdr.MicrocodeHdrVersion], 0ffffffffh
    cmp   dword [esi + MicrocodeHdr.MicrocodeHdrVersion], 0ffffffffh
    jz    Done
    jz    Done
-
-LoadCheck:
-   ; Get the revision of the current microcode update loaded
-   mov   ecx, MSR_IA32_BIOS_SIGN_ID
-   xor   eax, eax               ; Clear EAX
-   xor   edx, edx               ; Clear EDX
-   wrmsr                        ; Load 0 to MSR at 8Bh
-
-   mov   eax, 1
-   cpuid
-   mov   ecx, MSR_IA32_BIOS_SIGN_ID
-   rdmsr                        ; Get current microcode signature
-
-   ; Verify this microcode update is not already loaded
-   cmp   dword [esi + MicrocodeHdr.MicrocodeHdrRevision], edx
-   je    Continue
-
+   jmp   CheckMainHeader
 LoadMicrocode:
 LoadMicrocode:
    ; EAX contains the linear address of the start of the Update Data
    ; EAX contains the linear address of the start of the Update Data
    ; EDX contains zero
    ; EDX contains zero
@@ -465,10 +465,12 @@ LoadMicrocode:
    mov   eax, 1
    mov   eax, 1
    cpuid
    cpuid
 
 
-Continue:
-   jmp   NextMicrocode
-
 Done:
 Done:
+   mov   ecx, MSR_IA32_BIOS_SIGN_ID
+   xor   eax, eax               ; Clear EAX
+   xor   edx, edx               ; Clear EDX
+   wrmsr                        ; Load 0 to MSR at 8Bh
+
    mov   eax, 1
    mov   eax, 1
    cpuid
    cpuid
    mov   ecx, MSR_IA32_BIOS_SIGN_ID
    mov   ecx, MSR_IA32_BIOS_SIGN_ID

+ 24 - 21
IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm

@@ -141,6 +141,22 @@ ASM_PFX(LoadMicrocodeDefault):
    jz     ParamError
    jz     ParamError
    mov    rsp, rcx
    mov    rsp, rcx
 
 
+   ;
+   ; If microcode already loaded before this function, exit this function with SUCCESS.
+   ;
+   mov   ecx, MSR_IA32_BIOS_SIGN_ID
+   xor   eax, eax               ; Clear EAX
+   xor   edx, edx               ; Clear EDX
+   wrmsr                        ; Load 0 to MSR at 8Bh
+
+   mov   eax, 1
+   cpuid
+   mov   ecx, MSR_IA32_BIOS_SIGN_ID
+   rdmsr                         ; Get current microcode signature
+   xor   rax, rax
+   test  edx, edx
+   jnz   Exit2
+
    ; skip loading Microcode if the MicrocodeCodeSize is zero
    ; skip loading Microcode if the MicrocodeCodeSize is zero
    ; and report error if size is less than 2k
    ; and report error if size is less than 2k
    ; first check UPD header revision
    ; first check UPD header revision
@@ -198,7 +214,7 @@ CheckMainHeader:
    cmp   ebx, dword [esi + MicrocodeHdr.MicrocodeHdrProcessor]
    cmp   ebx, dword [esi + MicrocodeHdr.MicrocodeHdrProcessor]
    jne   LoadMicrocodeDefault1
    jne   LoadMicrocodeDefault1
    test  edx, dword [esi + MicrocodeHdr.MicrocodeHdrFlags ]
    test  edx, dword [esi + MicrocodeHdr.MicrocodeHdrFlags ]
-   jnz   LoadCheck  ; Jif signature and platform ID match
+   jnz   LoadMicrocode  ; Jif signature and platform ID match
 
 
 LoadMicrocodeDefault1:
 LoadMicrocodeDefault1:
    ; Check if extended header exists
    ; Check if extended header exists
@@ -231,7 +247,7 @@ CheckExtSig:
    cmp   dword [edi + ExtSig.ExtSigProcessor], ebx
    cmp   dword [edi + ExtSig.ExtSigProcessor], ebx
    jne   LoadMicrocodeDefault2
    jne   LoadMicrocodeDefault2
    test  dword [edi + ExtSig.ExtSigFlags], edx
    test  dword [edi + ExtSig.ExtSigFlags], edx
-   jnz   LoadCheck      ; Jif signature and platform ID match
+   jnz   LoadMicrocode      ; Jif signature and platform ID match
 LoadMicrocodeDefault2:
 LoadMicrocodeDefault2:
    ; Check if any more extended signatures exist
    ; Check if any more extended signatures exist
    add   edi, ExtSig.size
    add   edi, ExtSig.size
@@ -276,22 +292,7 @@ LoadMicrocodeDefault4:
    ; Is valid Microcode start point ?
    ; Is valid Microcode start point ?
    cmp   dword [esi + MicrocodeHdr.MicrocodeHdrVersion], 0ffffffffh
    cmp   dword [esi + MicrocodeHdr.MicrocodeHdrVersion], 0ffffffffh
    jz    Done
    jz    Done
-
-LoadCheck:
-   ; Get the revision of the current microcode update loaded
-   mov   ecx, MSR_IA32_BIOS_SIGN_ID
-   xor   eax, eax               ; Clear EAX
-   xor   edx, edx               ; Clear EDX
-   wrmsr                        ; Load 0 to MSR at 8Bh
-
-   mov   eax, 1
-   cpuid
-   mov   ecx, MSR_IA32_BIOS_SIGN_ID
-   rdmsr                        ; Get current microcode signature
-
-   ; Verify this microcode update is not already loaded
-   cmp   dword [esi + MicrocodeHdr.MicrocodeHdrRevision], edx
-   je    Continue
+   jmp   CheckMainHeader
 
 
 LoadMicrocode:
 LoadMicrocode:
    ; EAX contains the linear address of the start of the Update Data
    ; EAX contains the linear address of the start of the Update Data
@@ -306,10 +307,12 @@ LoadMicrocode:
    mov   eax, 1
    mov   eax, 1
    cpuid
    cpuid
 
 
-Continue:
-   jmp   NextMicrocode
-
 Done:
 Done:
+   mov   ecx, MSR_IA32_BIOS_SIGN_ID
+   xor   eax, eax               ; Clear EAX
+   xor   edx, edx               ; Clear EDX
+   wrmsr                        ; Load 0 to MSR at 8Bh
+
    mov   eax, 1
    mov   eax, 1
    cpuid
    cpuid
    mov   ecx, MSR_IA32_BIOS_SIGN_ID
    mov   ecx, MSR_IA32_BIOS_SIGN_ID