FspApiEntryT.nasm 19 KB

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  1. ;; @file
  2. ; Provide FSP API entry points.
  3. ;
  4. ; Copyright (c) 2016 - 2022, Intel Corporation. All rights reserved.<BR>
  5. ; SPDX-License-Identifier: BSD-2-Clause-Patent
  6. ;;
  7. SECTION .text
  8. %include "SaveRestoreSseNasm.inc"
  9. %include "MicrocodeLoadNasm.inc"
  10. ;
  11. ; Following are fixed PCDs
  12. ;
  13. extern ASM_PFX(PcdGet32 (PcdTemporaryRamBase))
  14. extern ASM_PFX(PcdGet32 (PcdTemporaryRamSize))
  15. extern ASM_PFX(PcdGet32 (PcdFspReservedBufferSize))
  16. ;
  17. ; Following functions will be provided in PlatformSecLib
  18. ;
  19. extern ASM_PFX(AsmGetFspBaseAddress)
  20. extern ASM_PFX(AsmGetFspInfoHeaderNoStack)
  21. ;extern ASM_PFX(LoadMicrocode) ; @todo: needs a weak implementation
  22. extern ASM_PFX(SecPlatformInit) ; @todo: needs a weak implementation
  23. extern ASM_PFX(SecCarInit)
  24. ;
  25. ; Define the data length that we saved on the stack top
  26. ;
  27. DATA_LEN_OF_PER0 EQU 18h
  28. DATA_LEN_OF_MCUD EQU 18h
  29. DATA_LEN_AT_STACK_TOP EQU (DATA_LEN_OF_PER0 + DATA_LEN_OF_MCUD + 4)
  30. ;
  31. ; @todo: These structures are moved from MicrocodeLoadNasm.inc to avoid
  32. ; build error. This needs to be fixed later on.
  33. ;
  34. struc MicrocodeHdr
  35. .MicrocodeHdrVersion: resd 1
  36. .MicrocodeHdrRevision: resd 1
  37. .MicrocodeHdrDate: resd 1
  38. .MicrocodeHdrProcessor: resd 1
  39. .MicrocodeHdrChecksum: resd 1
  40. .MicrocodeHdrLoader: resd 1
  41. .MicrocodeHdrFlags: resd 1
  42. .MicrocodeHdrDataSize: resd 1
  43. .MicrocodeHdrTotalSize: resd 1
  44. .MicrocodeHdrRsvd: resd 3
  45. .size:
  46. endstruc
  47. struc ExtSigHdr
  48. .ExtSigHdrCount: resd 1
  49. .ExtSigHdrChecksum: resd 1
  50. .ExtSigHdrRsvd: resd 3
  51. .size:
  52. endstruc
  53. struc ExtSig
  54. .ExtSigProcessor: resd 1
  55. .ExtSigFlags: resd 1
  56. .ExtSigChecksum: resd 1
  57. .size:
  58. endstruc
  59. struc LoadMicrocodeParams
  60. ; FSP_UPD_HEADER {
  61. .FspUpdHeader: resd 8
  62. ; }
  63. ; FSPT_CORE_UPD {
  64. .MicrocodeCodeAddr: resd 1
  65. .MicrocodeCodeSize: resd 1
  66. .CodeRegionBase: resd 1
  67. .CodeRegionSize: resd 1
  68. ; }
  69. .size:
  70. endstruc
  71. struc LoadMicrocodeParamsFsp22
  72. ; FSP_UPD_HEADER {
  73. .FspUpdHeaderSignature: resd 2
  74. .FspUpdHeaderRevision: resb 1
  75. .FspUpdHeaderReserved: resb 23
  76. ; }
  77. ; FSPT_ARCH_UPD {
  78. .FsptArchRevision: resb 1
  79. .FsptArchReserved: resb 3
  80. .FsptArchUpd: resd 7
  81. ; }
  82. ; FSPT_CORE_UPD {
  83. .MicrocodeCodeAddr: resd 1
  84. .MicrocodeCodeSize: resd 1
  85. .CodeRegionBase: resd 1
  86. .CodeRegionSize: resd 1
  87. ; }
  88. .size:
  89. endstruc
  90. struc LoadMicrocodeParamsFsp24
  91. ; FSP_UPD_HEADER {
  92. .FspUpdHeaderSignature: resd 2
  93. .FspUpdHeaderRevision: resb 1
  94. .FspUpdHeaderReserved: resb 23
  95. ; }
  96. ; FSPT_ARCH2_UPD {
  97. .FsptArchRevision: resb 1
  98. .FsptArchReserved: resb 3
  99. .FsptArchLength: resd 1
  100. .FspDebugHandler resq 1
  101. .FsptArchUpd: resd 4
  102. ; }
  103. ; FSPT_CORE_UPD {
  104. .MicrocodeCodeAddr: resq 1
  105. .MicrocodeCodeSize: resq 1
  106. .CodeRegionBase: resq 1
  107. .CodeRegionSize: resq 1
  108. ; }
  109. .size:
  110. endstruc
  111. ;
  112. ; Define SSE macros
  113. ;
  114. ;
  115. ;args 1: ReturnAddress 2:MmxRegister
  116. ;
  117. %macro LOAD_MMX_EXT 2
  118. mov esi, %1
  119. movd %2, esi ; save ReturnAddress into MMX
  120. %endmacro
  121. ;
  122. ;args 1: RoutineLabel 2:MmxRegister
  123. ;
  124. %macro CALL_MMX_EXT 2
  125. mov esi, %%ReturnAddress
  126. movd %2, esi ; save ReturnAddress into MMX
  127. jmp %1
  128. %%ReturnAddress:
  129. %endmacro
  130. ;
  131. ;arg 1:MmxRegister
  132. ;
  133. %macro RET_ESI_EXT 1
  134. movd esi, %1 ; move ReturnAddress from MMX to ESI
  135. jmp esi
  136. %endmacro
  137. ;
  138. ;arg 1:RoutineLabel
  139. ;
  140. %macro CALL_MMX 1
  141. CALL_MMX_EXT %1, mm7
  142. %endmacro
  143. %macro RET_ESI 0
  144. RET_ESI_EXT mm7
  145. %endmacro
  146. %macro CALL_EDI 1
  147. mov edi, %%ReturnAddress
  148. jmp %1
  149. %%ReturnAddress:
  150. %endmacro
  151. %macro CALL_EBP 1
  152. mov ebp, %%ReturnAddress
  153. jmp %1
  154. %%ReturnAddress:
  155. %endmacro
  156. %macro RET_EBP 0
  157. jmp ebp ; restore EIP from EBP
  158. %endmacro
  159. ;
  160. ; Load UPD region pointer in ECX
  161. ;
  162. global ASM_PFX(LoadUpdPointerToECX)
  163. ASM_PFX(LoadUpdPointerToECX):
  164. ;
  165. ; esp + 4 is input UPD parameter
  166. ; If esp + 4 is NULL the default UPD should be used
  167. ; ecx will be the UPD region that should be used
  168. ;
  169. mov ecx, dword [esp + 4]
  170. cmp ecx, 0
  171. jnz ParamValid
  172. ;
  173. ; Fall back to default UPD region
  174. ;
  175. CALL_EDI ASM_PFX(AsmGetFspInfoHeaderNoStack)
  176. mov ecx, DWORD [eax + 01Ch] ; Read FsptImageBaseAddress
  177. add ecx, DWORD [eax + 024h] ; Get Cfg Region base address = FsptImageBaseAddress + CfgRegionOffset
  178. ParamValid:
  179. RET_EBP
  180. ;
  181. ; @todo: The strong/weak implementation does not work.
  182. ; This needs to be reviewed later.
  183. ;
  184. ;------------------------------------------------------------------------------
  185. ;
  186. ;;global ASM_PFX(SecPlatformInitDefault)
  187. ;ASM_PFX(SecPlatformInitDefault):
  188. ; ; Inputs:
  189. ; ; mm7 -> Return address
  190. ; ; Outputs:
  191. ; ; eax -> 0 - Successful, Non-zero - Failed.
  192. ; ; Register Usage:
  193. ; ; eax is cleared and ebp is used for return address.
  194. ; ; All others reserved.
  195. ;
  196. ; ; Save return address to EBP
  197. ; movd ebp, mm7
  198. ;
  199. ; xor eax, eax
  200. ;Exit1:
  201. ; jmp ebp
  202. ;------------------------------------------------------------------------------
  203. global ASM_PFX(LoadMicrocodeDefault)
  204. ASM_PFX(LoadMicrocodeDefault):
  205. ; Inputs:
  206. ; ecx -> UPD region contains LoadMicrocodeParams pointer
  207. ; Register Usage:
  208. ; All are destroyed
  209. ; Assumptions:
  210. ; No memory available, stack is hard-coded and used for return address
  211. ; Executed by SBSP and NBSP
  212. ; Beginning of microcode update region starts on paragraph boundary
  213. ;
  214. ; Save return address to EBP
  215. ;
  216. movd ebp, mm7
  217. mov esp, ecx ; ECX has been assigned to UPD region
  218. cmp esp, 0
  219. jz ParamError
  220. ;
  221. ; If microcode already loaded before this function, exit this function with SUCCESS.
  222. ;
  223. mov ecx, MSR_IA32_BIOS_SIGN_ID
  224. xor eax, eax ; Clear EAX
  225. xor edx, edx ; Clear EDX
  226. wrmsr ; Load 0 to MSR at 8Bh
  227. mov eax, 1
  228. cpuid
  229. mov ecx, MSR_IA32_BIOS_SIGN_ID
  230. rdmsr ; Get current microcode signature
  231. xor eax, eax
  232. test edx, edx
  233. jnz Exit2
  234. ; skip loading Microcode if the MicrocodeCodeSize is zero
  235. ; and report error if size is less than 2k
  236. ; first check UPD header revision
  237. cmp byte [esp + LoadMicrocodeParamsFsp22.FspUpdHeaderRevision], 2
  238. jb Fsp20UpdHeader
  239. cmp byte [esp + LoadMicrocodeParamsFsp22.FsptArchRevision], 2
  240. je Fsp24UpdHeader
  241. jmp Fsp22UpdHeader
  242. Fsp20UpdHeader:
  243. ; UPD structure is compliant with FSP spec 2.0/2.1
  244. mov eax, dword [esp + LoadMicrocodeParams.MicrocodeCodeSize]
  245. cmp eax, 0
  246. jz Exit2
  247. cmp eax, 0800h
  248. jl ParamError
  249. mov esi, dword [esp + LoadMicrocodeParams.MicrocodeCodeAddr]
  250. cmp esi, 0
  251. jnz CheckMainHeader
  252. jmp ParamError
  253. Fsp22UpdHeader:
  254. ; UPD structure is compliant with FSP spec 2.2
  255. mov eax, dword [esp + LoadMicrocodeParamsFsp22.MicrocodeCodeSize]
  256. cmp eax, 0
  257. jz Exit2
  258. cmp eax, 0800h
  259. jl ParamError
  260. mov esi, dword [esp + LoadMicrocodeParamsFsp22.MicrocodeCodeAddr]
  261. cmp esi, 0
  262. jnz CheckMainHeader
  263. jmp ParamError
  264. Fsp24UpdHeader:
  265. ; UPD structure is compliant with FSP spec 2.4
  266. mov eax, dword [esp + LoadMicrocodeParamsFsp24.MicrocodeCodeSize]
  267. cmp eax, 0
  268. jz Exit2
  269. cmp eax, 0800h
  270. jl ParamError
  271. mov esi, dword [esp + LoadMicrocodeParamsFsp24.MicrocodeCodeAddr]
  272. cmp esi, 0
  273. jnz CheckMainHeader
  274. ParamError:
  275. mov eax, 080000002h
  276. jmp Exit2
  277. CheckMainHeader:
  278. ; Get processor signature and platform ID from the installed processor
  279. ; and save into registers for later use
  280. ; ebx = processor signature
  281. ; edx = platform ID
  282. mov eax, 1
  283. cpuid
  284. mov ebx, eax
  285. mov ecx, MSR_IA32_PLATFORM_ID
  286. rdmsr
  287. mov ecx, edx
  288. shr ecx, 50-32 ; shift (50d-32d=18d=0x12) bits
  289. and ecx, 7h ; platform id at bit[52..50]
  290. mov edx, 1
  291. shl edx, cl
  292. ; Current register usage
  293. ; esp -> stack with parameters
  294. ; esi -> microcode update to check
  295. ; ebx = processor signature
  296. ; edx = platform ID
  297. ; Check for valid microcode header
  298. ; Minimal test checking for header version and loader version as 1
  299. mov eax, dword 1
  300. cmp dword [esi + MicrocodeHdr.MicrocodeHdrVersion], eax
  301. jne AdvanceFixedSize
  302. cmp dword [esi + MicrocodeHdr.MicrocodeHdrLoader], eax
  303. jne AdvanceFixedSize
  304. ; Check if signature and plaform ID match
  305. cmp ebx, dword [esi + MicrocodeHdr.MicrocodeHdrProcessor]
  306. jne LoadMicrocodeDefault1
  307. test edx, dword [esi + MicrocodeHdr.MicrocodeHdrFlags ]
  308. jnz LoadMicrocode ; Jif signature and platform ID match
  309. LoadMicrocodeDefault1:
  310. ; Check if extended header exists
  311. ; First check if MicrocodeHdrTotalSize and MicrocodeHdrDataSize are valid
  312. xor eax, eax
  313. cmp dword [esi + MicrocodeHdr.MicrocodeHdrTotalSize], eax
  314. je NextMicrocode
  315. cmp dword [esi + MicrocodeHdr.MicrocodeHdrDataSize], eax
  316. je NextMicrocode
  317. ; Then verify total size - sizeof header > data size
  318. mov ecx, dword [esi + MicrocodeHdr.MicrocodeHdrTotalSize]
  319. sub ecx, MicrocodeHdr.size
  320. cmp ecx, dword [esi + MicrocodeHdr.MicrocodeHdrDataSize]
  321. jng NextMicrocode ; Jif extended header does not exist
  322. ; Set edi -> extended header
  323. mov edi, esi
  324. add edi, MicrocodeHdr.size
  325. add edi, dword [esi + MicrocodeHdr.MicrocodeHdrDataSize]
  326. ; Get count of extended structures
  327. mov ecx, dword [edi + ExtSigHdr.ExtSigHdrCount]
  328. ; Move pointer to first signature structure
  329. add edi, ExtSigHdr.size
  330. CheckExtSig:
  331. ; Check if extended signature and platform ID match
  332. cmp dword [edi + ExtSig.ExtSigProcessor], ebx
  333. jne LoadMicrocodeDefault2
  334. test dword [edi + ExtSig.ExtSigFlags], edx
  335. jnz LoadMicrocode ; Jif signature and platform ID match
  336. LoadMicrocodeDefault2:
  337. ; Check if any more extended signatures exist
  338. add edi, ExtSig.size
  339. loop CheckExtSig
  340. NextMicrocode:
  341. ; Advance just after end of this microcode
  342. xor eax, eax
  343. cmp dword [esi + MicrocodeHdr.MicrocodeHdrTotalSize], eax
  344. je LoadMicrocodeDefault3
  345. add esi, dword [esi + MicrocodeHdr.MicrocodeHdrTotalSize]
  346. jmp CheckAddress
  347. LoadMicrocodeDefault3:
  348. add esi, dword 2048
  349. jmp CheckAddress
  350. AdvanceFixedSize:
  351. ; Advance by 4X dwords
  352. add esi, dword 1024
  353. CheckAddress:
  354. ; Check UPD header revision
  355. cmp byte [esp + LoadMicrocodeParamsFsp22.FspUpdHeaderRevision], 2
  356. jb Fsp20UpdHeader1
  357. cmp byte [esp + LoadMicrocodeParamsFsp22.FsptArchRevision], 2
  358. je Fsp24UpdHeader1;
  359. jmp Fsp22UpdHeader1
  360. Fsp20UpdHeader1:
  361. ; UPD structure is compliant with FSP spec 2.0/2.1
  362. ; Is automatic size detection ?
  363. mov eax, dword [esp + LoadMicrocodeParams.MicrocodeCodeSize]
  364. cmp eax, 0ffffffffh
  365. jz LoadMicrocodeDefault4
  366. ; Address >= microcode region address + microcode region size?
  367. add eax, dword [esp + LoadMicrocodeParams.MicrocodeCodeAddr]
  368. cmp esi, eax
  369. jae Done ;Jif address is outside of microcode region
  370. jmp CheckMainHeader
  371. Fsp22UpdHeader1:
  372. ; UPD structure is compliant with FSP spec 2.2
  373. ; Is automatic size detection ?
  374. mov eax, dword [esp + LoadMicrocodeParamsFsp22.MicrocodeCodeSize]
  375. cmp eax, 0ffffffffh
  376. jz LoadMicrocodeDefault4
  377. ; Address >= microcode region address + microcode region size?
  378. add eax, dword [esp + LoadMicrocodeParamsFsp22.MicrocodeCodeAddr]
  379. cmp esi, eax
  380. jae Done ;Jif address is outside of microcode region
  381. jmp CheckMainHeader
  382. Fsp24UpdHeader1:
  383. ; UPD structure is compliant with FSP spec 2.4
  384. ; Is automatic size detection ?
  385. mov eax, dword [esp + LoadMicrocodeParamsFsp24.MicrocodeCodeSize]
  386. cmp eax, 0ffffffffh
  387. jz LoadMicrocodeDefault4
  388. ; Address >= microcode region address + microcode region size?
  389. add eax, dword [esp + LoadMicrocodeParamsFsp24.MicrocodeCodeAddr]
  390. cmp esi, eax
  391. jae Done ;Jif address is outside of microcode region
  392. jmp CheckMainHeader
  393. LoadMicrocodeDefault4:
  394. ; Is valid Microcode start point ?
  395. cmp dword [esi + MicrocodeHdr.MicrocodeHdrVersion], 0ffffffffh
  396. jz Done
  397. jmp CheckMainHeader
  398. LoadMicrocode:
  399. ; EAX contains the linear address of the start of the Update Data
  400. ; EDX contains zero
  401. ; ECX contains 79h (IA32_BIOS_UPDT_TRIG)
  402. ; Start microcode load with wrmsr
  403. mov eax, esi
  404. add eax, MicrocodeHdr.size
  405. xor edx, edx
  406. mov ecx, MSR_IA32_BIOS_UPDT_TRIG
  407. wrmsr
  408. mov eax, 1
  409. cpuid
  410. Done:
  411. mov ecx, MSR_IA32_BIOS_SIGN_ID
  412. xor eax, eax ; Clear EAX
  413. xor edx, edx ; Clear EDX
  414. wrmsr ; Load 0 to MSR at 8Bh
  415. mov eax, 1
  416. cpuid
  417. mov ecx, MSR_IA32_BIOS_SIGN_ID
  418. rdmsr ; Get current microcode signature
  419. xor eax, eax
  420. cmp edx, 0
  421. jnz Exit2
  422. mov eax, 08000000Eh
  423. Exit2:
  424. jmp ebp
  425. ;
  426. ; EstablishStackFsp: EDI should be preserved cross this function
  427. ;
  428. global ASM_PFX(EstablishStackFsp)
  429. ASM_PFX(EstablishStackFsp):
  430. ;
  431. ; Save parameter pointer in edx
  432. ;
  433. mov edx, ecx ; ECX has been assigned to UPD region
  434. ;
  435. ; Enable FSP STACK
  436. ;
  437. mov esp, DWORD [ASM_PFX(PcdGet32 (PcdTemporaryRamBase))]
  438. add esp, DWORD [ASM_PFX(PcdGet32 (PcdTemporaryRamSize))]
  439. push DATA_LEN_OF_MCUD ; Size of the data region
  440. push 4455434Dh ; Signature of the data region 'MCUD'
  441. ; check UPD structure revision (edx + 8)
  442. cmp byte [edx + LoadMicrocodeParamsFsp22.FspUpdHeaderRevision], 2
  443. jb Fsp20UpdHeader2
  444. cmp byte [esp + LoadMicrocodeParamsFsp22.FsptArchRevision], 2
  445. je Fsp24UpdHeader2
  446. jmp Fsp22UpdHeader2
  447. Fsp20UpdHeader2:
  448. ; UPD structure is compliant with FSP spec 2.0/2.1
  449. push dword [edx + LoadMicrocodeParams.CodeRegionSize] ; Code size sizeof(FSPT_UPD_COMMON) + 12
  450. push dword [edx + LoadMicrocodeParams.CodeRegionBase] ; Code base sizeof(FSPT_UPD_COMMON) + 8
  451. push dword [edx + LoadMicrocodeParams.MicrocodeCodeSize] ; Microcode size sizeof(FSPT_UPD_COMMON) + 4
  452. push dword [edx + LoadMicrocodeParams.MicrocodeCodeAddr] ; Microcode base sizeof(FSPT_UPD_COMMON) + 0
  453. jmp ContinueAfterUpdPush
  454. Fsp22UpdHeader2:
  455. ; UPD structure is compliant with FSP spec 2.2
  456. push dword [edx + LoadMicrocodeParamsFsp22.CodeRegionSize] ; Code size sizeof(FSPT_UPD_COMMON) + 12
  457. push dword [edx + LoadMicrocodeParamsFsp22.CodeRegionBase] ; Code base sizeof(FSPT_UPD_COMMON) + 8
  458. push dword [edx + LoadMicrocodeParamsFsp22.MicrocodeCodeSize] ; Microcode size sizeof(FSPT_UPD_COMMON) + 4
  459. push dword [edx + LoadMicrocodeParamsFsp22.MicrocodeCodeAddr] ; Microcode base sizeof(FSPT_UPD_COMMON) + 0
  460. jmp ContinueAfterUpdPush
  461. Fsp24UpdHeader2:
  462. ; UPD structure is compliant with FSP spec 2.4
  463. push dword [edx + LoadMicrocodeParamsFsp24.CodeRegionSize] ; Code size sizeof(FSPT_UPD_COMMON) + 24
  464. push dword [edx + LoadMicrocodeParamsFsp24.CodeRegionBase] ; Code base sizeof(FSPT_UPD_COMMON) + 16
  465. push dword [edx + LoadMicrocodeParamsFsp24.MicrocodeCodeSize] ; Microcode size sizeof(FSPT_UPD_COMMON) + 8
  466. push dword [edx + LoadMicrocodeParamsFsp24.MicrocodeCodeAddr] ; Microcode base sizeof(FSPT_UPD_COMMON) + 0
  467. ContinueAfterUpdPush:
  468. ;
  469. ; Save API entry/exit timestamp into stack
  470. ;
  471. push DATA_LEN_OF_PER0 ; Size of the data region
  472. push 30524550h ; Signature of the data region 'PER0'
  473. rdtsc
  474. push edx
  475. push eax
  476. LOAD_EDX
  477. push edx
  478. LOAD_EAX
  479. push eax
  480. ;
  481. ; Terminator for the data on stack
  482. ;
  483. push 0
  484. ;
  485. ; Set ECX/EDX to the BootLoader temporary memory range
  486. ;
  487. mov ecx, [ASM_PFX(PcdGet32 (PcdTemporaryRamBase))]
  488. mov edx, ecx
  489. add edx, [ASM_PFX(PcdGet32 (PcdTemporaryRamSize))]
  490. sub edx, [ASM_PFX(PcdGet32 (PcdFspReservedBufferSize))]
  491. cmp ecx, edx ;If PcdFspReservedBufferSize >= PcdTemporaryRamSize, then error.
  492. jb EstablishStackFspSuccess
  493. mov eax, 80000003h ;EFI_UNSUPPORTED
  494. jmp EstablishStackFspExit
  495. EstablishStackFspSuccess:
  496. xor eax, eax
  497. EstablishStackFspExit:
  498. RET_ESI
  499. ;----------------------------------------------------------------------------
  500. ; TempRamInit API
  501. ;
  502. ; This FSP API will load the microcode update, enable code caching for the
  503. ; region specified by the boot loader and also setup a temporary stack to be
  504. ; used till main memory is initialized.
  505. ;
  506. ;----------------------------------------------------------------------------
  507. global ASM_PFX(TempRamInitApi)
  508. ASM_PFX(TempRamInitApi):
  509. ;
  510. ; Ensure SSE is enabled
  511. ;
  512. ENABLE_SSE
  513. ;
  514. ; Save EBP, EBX, ESI, EDI & ESP in XMM7 & XMM6
  515. ;
  516. SAVE_REGS
  517. ;
  518. ; Save timestamp into XMM6
  519. ;
  520. rdtsc
  521. SAVE_EAX
  522. SAVE_EDX
  523. CALL_EBP ASM_PFX(LoadUpdPointerToECX) ; ECX for UPD param
  524. SAVE_ECX ; save UPD param to slot 3 in xmm6
  525. ;
  526. ; Sec Platform Init
  527. ;
  528. CALL_MMX ASM_PFX(SecPlatformInit)
  529. cmp eax, 0
  530. jnz TempRamInitExit
  531. ; Load microcode
  532. LOAD_ESP
  533. LOAD_ECX
  534. CALL_MMX ASM_PFX(LoadMicrocodeDefault)
  535. SAVE_UCODE_STATUS ; Save microcode return status in slot 1 in xmm5.
  536. ;@note If return value eax is not 0, microcode did not load, but continue and attempt to boot.
  537. ; Call Sec CAR Init
  538. LOAD_ESP
  539. LOAD_ECX
  540. CALL_MMX ASM_PFX(SecCarInit)
  541. cmp eax, 0
  542. jnz TempRamInitExit
  543. LOAD_ESP
  544. LOAD_ECX
  545. mov edi, ecx ; Save UPD param to EDI for later code use
  546. CALL_MMX ASM_PFX(EstablishStackFsp)
  547. cmp eax, 0
  548. jnz TempRamInitExit
  549. LOAD_UCODE_STATUS ; Restore microcode status if no CAR init error from slot 1 in xmm5.
  550. TempRamInitExit:
  551. mov bl, al ; save al data in bl
  552. mov al, 07Fh ; API exit postcode 7f
  553. out 080h, al
  554. mov al, bl ; restore al data from bl
  555. ;
  556. ; Load EBP, EBX, ESI, EDI & ESP from XMM7 & XMM6
  557. ;
  558. LOAD_REGS
  559. ret
  560. ;----------------------------------------------------------------------------
  561. ; Module Entrypoint API
  562. ;----------------------------------------------------------------------------
  563. global ASM_PFX(_ModuleEntryPoint)
  564. ASM_PFX(_ModuleEntryPoint):
  565. jmp $