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KabylakeSiliconPkg: Support DefaultPolicyInit PPI.

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1870

FSP in dispatch mode will produce DefaultPolicyInit
PPI for boot loader to consume and install policy
with default settings built-in by FSP.
Boot loader then may patch policy with per-board
settings and then install PolicyReady PPI to start
silicon initialization (policy consumer code)

Since different version FSP has different version
policy structure, the policy revision check code has
been extended to support newer revision policy and
the policy structure boot loader consuming has been
aligned with the same structure inside FSP.
(FSP will maintain policy structure backward
compatibility)

Also removed microcode location searching code from
silicon scope because silicon code should not access
hard-coded flash region unconditionally.
This should be done by platform/boot loader side.

Cc: Michael A Kubacki <michael.a.kubacki@intel.com>
Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
Reviewed-by: Sai Chaganty <rangasai.v.chaganty@intel.com>
Chasel, Chiu преди 5 години
родител
ревизия
710f550b29
променени са 22 файла, в които са добавени 383 реда и са изтрити 186 реда
  1. 3 1
      Silicon/Intel/KabylakeSiliconPkg/Cpu/Include/CpuDataStruct.h
  2. 7 126
      Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/PeiCpuPolicyLib/PeiCpuPolicyLib.c
  3. 1 3
      Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/PeiCpuPolicyLib/PeiCpuPolicyLibrary.h
  4. 28 4
      Silicon/Intel/KabylakeSiliconPkg/Include/Library/SiPolicyLib.h
  5. 36 0
      Silicon/Intel/KabylakeSiliconPkg/Include/Ppi/PeiPreMemSiDefaultPolicyInit.h
  6. 36 0
      Silicon/Intel/KabylakeSiliconPkg/Include/Ppi/PeiSiDefaultPolicyInit.h
  7. 48 5
      Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiPolicyLib/PeiSiPolicyLib.c
  8. 5 3
      Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiPolicyLib/PeiSiPolicyLib.inf
  9. 46 4
      Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiPolicyLib/PeiSiPolicyLibPreMem.c
  10. 25 7
      Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPolicyInit.c
  11. 3 1
      Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPolicyInit.h
  12. 27 12
      Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPolicyInitPreMem.c
  13. 75 0
      Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPostMemSiliconPolicyInitLib.inf
  14. 8 3
      Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPreMemSiliconPolicyInitLib.inf
  15. 3 2
      Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLibFsp/PeiSiliconPolicyInitLibFsp.inf
  16. 1 0
      Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLibFsp/PeiSiliconPolicyInitLibFspAml.inf
  17. 3 3
      Silicon/Intel/KabylakeSiliconPkg/Me/Library/PeiMePolicyLib/PeiMePolicyLib.c
  18. 4 1
      Silicon/Intel/KabylakeSiliconPkg/SiPkg.dec
  19. 14 2
      Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Include/ConfigBlock/GraphicsPeiConfig.h
  20. 2 2
      Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/DxeSaPolicyLib/DxeSaPolicyLib.c
  21. 1 0
      Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/PeiSaPolicyLib/PeiSaPolicyLib.inf
  22. 7 7
      Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/PeiSaPolicyLib/SaPrintPolicy.c

+ 3 - 1
Silicon/Intel/KabylakeSiliconPkg/Cpu/Include/CpuDataStruct.h

@@ -1,7 +1,7 @@
 /** @file
   This file declares various data structures used in CPU reference code.
 
-Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>
 SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
@@ -24,6 +24,8 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
 #define CPU_CAUSE_BY_ASSOCIATION    0x0100
 #define CPU_CAUSE_UNSPECIFIED       0x8000
 
+#define MAX_MICROCODE_PATCH_SIZE    0x20000
+
 typedef UINT32 CPU_STATE_CHANGE_CAUSE;
 
 ///

+ 7 - 126
Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/PeiCpuPolicyLib/PeiCpuPolicyLib.c

@@ -1,7 +1,7 @@
 /** @file
   This file is PeiCpuPolicy library.
 
-Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>
 SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
@@ -13,128 +13,6 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
 #include <Library/ConfigBlockLib.h>
 #include <Library/PostCodeLib.h>
 
-#ifndef FSP_FLAG
-/**
-  Get the next microcode patch pointer.
-
-  @param[in, out] MicrocodeData - Input is a pointer to the last microcode patch address found,
-                                  and output points to the next patch address found.
-
-  @retval EFI_SUCCESS           - Patch found.
-  @retval EFI_NOT_FOUND         - Patch not found.
-**/
-EFI_STATUS
-EFIAPI
-RetrieveMicrocode (
-  IN OUT CPU_MICROCODE_HEADER **MicrocodeData
-  )
-{
-  UINTN                MicrocodeStart;
-  UINTN                MicrocodeEnd;
-  UINTN                TotalSize;
-
-  if ((FixedPcdGet32 (PcdFlashMicrocodeFvBase) == 0) || (FixedPcdGet32 (PcdFlashMicrocodeFvSize) == 0)) {
-    return EFI_NOT_FOUND;
-  }
-
-  ///
-  /// Microcode binary in SEC
-  ///
-  MicrocodeStart = (UINTN) FixedPcdGet32 (PcdFlashMicrocodeFvBase) +
-          ((EFI_FIRMWARE_VOLUME_HEADER *) (UINTN) FixedPcdGet32 (PcdFlashMicrocodeFvBase))->HeaderLength +
-          sizeof (EFI_FFS_FILE_HEADER);
-
-  MicrocodeEnd = (UINTN) FixedPcdGet32 (PcdFlashMicrocodeFvBase) + (UINTN) FixedPcdGet32 (PcdFlashMicrocodeFvSize);
-
-  if (*MicrocodeData == NULL) {
-    *MicrocodeData = (CPU_MICROCODE_HEADER *) (UINTN) MicrocodeStart;
-  } else {
-    if (*MicrocodeData < (CPU_MICROCODE_HEADER *) (UINTN) MicrocodeStart) {
-      DEBUG ((DEBUG_INFO, "[CpuPolicy]*MicrocodeData < MicrocodeStart \n"));
-      return EFI_NOT_FOUND;
-    }
-
-    TotalSize = (UINTN) ((*MicrocodeData)->TotalSize);
-    if (TotalSize == 0) {
-      TotalSize = 2048;
-    }
-
-    *MicrocodeData = (CPU_MICROCODE_HEADER *) ((UINTN)*MicrocodeData + TotalSize);
-    if (*MicrocodeData >= (CPU_MICROCODE_HEADER *) (UINTN) (MicrocodeEnd) || (*MicrocodeData)->TotalSize == (UINT32) -1) {
-      DEBUG ((DEBUG_INFO, "[CpuPolicy]*MicrocodeData >= MicrocodeEnd \n"));
-      return EFI_NOT_FOUND;
-    }
-  }
-  return EFI_SUCCESS;
-}
-
-/**
-  Get the microcode patch pointer.
-
-  @retval EFI_PHYSICAL_ADDRESS - Address of the microcode patch, or NULL if not found.
-**/
-EFI_PHYSICAL_ADDRESS
-PlatformCpuLocateMicrocodePatch (
-  VOID
-  )
-{
-  EFI_STATUS           Status;
-  CPU_MICROCODE_HEADER *MicrocodeData;
-  EFI_CPUID_REGISTER   Cpuid;
-  UINT32               UcodeRevision;
-  UINTN                MicrocodeBufferSize;
-  VOID                 *MicrocodeBuffer = NULL;
-
-  AsmCpuid (
-    CPUID_VERSION_INFO,
-    &Cpuid.RegEax,
-    &Cpuid.RegEbx,
-    &Cpuid.RegEcx,
-    &Cpuid.RegEdx
-    );
-
-  UcodeRevision = GetCpuUcodeRevision ();
-  MicrocodeData = NULL;
-  while (TRUE) {
-    ///
-    /// Find the next patch address
-    ///
-    Status = RetrieveMicrocode (&MicrocodeData);
-    DEBUG ((DEBUG_INFO, "MicrocodeData = %x\n", MicrocodeData));
-
-    if (Status != EFI_SUCCESS) {
-      break;
-    } else if (CheckMicrocode (Cpuid.RegEax, MicrocodeData, &UcodeRevision)) {
-      break;
-    }
-  }
-
-  if (EFI_ERROR (Status)) {
-    return (EFI_PHYSICAL_ADDRESS) (UINTN) NULL;
-  }
-
-  ///
-  /// Check that microcode patch size is <= 128K max size,
-  /// then copy the patch from FV to temp buffer for faster access.
-  ///
-  MicrocodeBufferSize = (UINTN) MicrocodeData->TotalSize;
-
-  if (MicrocodeBufferSize <= MAX_MICROCODE_PATCH_SIZE) {
-    MicrocodeBuffer = AllocatePages (EFI_SIZE_TO_PAGES (MicrocodeBufferSize));
-    if (MicrocodeBuffer != NULL) {
-      DEBUG(( DEBUG_INFO, "Copying Microcode to temp buffer.\n"));
-      CopyMem (MicrocodeBuffer, MicrocodeData, MicrocodeBufferSize);
-
-      return (EFI_PHYSICAL_ADDRESS) (UINTN) MicrocodeBuffer;
-    } else {
-      DEBUG(( DEBUG_ERROR, "Failed to allocate enough memory for Microcode Patch.\n"));
-    }
-  } else {
-    DEBUG(( DEBUG_ERROR, "Microcode patch size is greater than max allowed size of 128K.\n"));
-  }
-  return (EFI_PHYSICAL_ADDRESS) (UINTN) NULL;
-}
-#endif
 
 /**
   Load Config block default
@@ -158,9 +36,12 @@ LoadCpuConfigDefault (
   CpuConfig->AesEnable             = CPU_FEATURE_ENABLE;
   CpuConfig->EnableRsr             = CPU_FEATURE_ENABLE;
   CpuConfig->SmmbaseSwSmiNumber    = (UINTN) PcdGet8 (PcdSmmbaseSwSmi);
-#ifndef FSP_FLAG
-  CpuConfig->MicrocodePatchAddress = PlatformCpuLocateMicrocodePatch ();
-#endif
+  //
+  // This function is shared by both non-FSP and FSP scenarios and always executed unconditionally.
+  // Since FSP/silicon code should not unconditionally access any hardcoding flash regions (that region might not be accessible
+  // in unknown platforms), the microcode location searching code should be moved to outside silicon code scope.
+  //
+  CpuConfig->MicrocodePatchAddress = 0;
 }
 
 

+ 1 - 3
Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/PeiCpuPolicyLib/PeiCpuPolicyLibrary.h

@@ -1,7 +1,7 @@
 /** @file
   Header file for the PeiCpuPolicyLib library.
 
-Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>
 SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
@@ -24,6 +24,4 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
 #include <Register/Cpuid.h>
 #include <Library/PcdLib.h>
 
-#define MAX_MICROCODE_PATCH_SIZE 0x20000
-
 #endif // _PEI_CPU_POLICY_LIBRARY_H_

+ 28 - 4
Silicon/Intel/KabylakeSiliconPkg/Include/Library/SiPolicyLib.h

@@ -1,7 +1,7 @@
 /** @file
   Prototype of the SiPolicyLib library.
 
-Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>
 SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
@@ -65,8 +65,6 @@ SiCreateConfigBlocks (
 
 /**
   SiPreMemInstallPolicyPpi installs SiPreMemPolicyPpi.
-  While installed, RC assumes the Policy is ready and finalized. So please update and override
-  any setting before calling this function.
 
   @param[in] SiPreMemPolicyPpi   The pointer to Silicon PREMEM Policy PPI instance
 
@@ -80,10 +78,22 @@ SiPreMemInstallPolicyPpi (
   );
 
 /**
-  SiInstallPolicyPpi installs SiPolicyPpi.
+  SiPreMemInstallPolicyReadyPpi installs SiPreMemPolicyReadyPpi.
   While installed, RC assumes the Policy is ready and finalized. So please update and override
   any setting before calling this function.
 
+  @retval EFI_SUCCESS            The policy is installed.
+  @retval EFI_OUT_OF_RESOURCES   Insufficient resources to create buffer
+**/
+EFI_STATUS
+EFIAPI
+SiPreMemInstallPolicyReadyPpi (
+  VOID
+  );
+
+/**
+  SiInstallPolicyPpi installs SiPolicyPpi.
+
   @param[in] SiPolicyPpi         The pointer to Silicon Policy PPI instance
 
   @retval EFI_SUCCESS            The policy is installed.
@@ -95,6 +105,20 @@ SiInstallPolicyPpi (
   IN  SI_POLICY_PPI          *SiPolicyPpi
   );
 
+/**
+  SiInstallPolicyReadyPpi installs SiPolicyReadyPpi.
+  While installed, RC assumes the Policy is ready and finalized. So please update and override
+  any setting before calling this function.
+
+  @retval EFI_SUCCESS            The policy is installed.
+  @retval EFI_OUT_OF_RESOURCES   Insufficient resources to create buffer
+**/
+EFI_STATUS
+EFIAPI
+SiInstallPolicyReadyPpi (
+  VOID
+  );
+
 /**
   Print out all silicon policy information.
 

+ 36 - 0
Silicon/Intel/KabylakeSiliconPkg/Include/Ppi/PeiPreMemSiDefaultPolicyInit.h

@@ -0,0 +1,36 @@
+/** @file
+  This file defines the PPI function for installing PreMem silicon policy
+  PPI with default settings.
+
+Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI_H_
+#define _PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI_H_
+
+//
+// Forward declaration for the PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI.
+//
+typedef struct _PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI;
+
+/**
+  Initialize and install default silicon policy PPI
+**/
+typedef
+EFI_STATUS
+(EFIAPI *PEI_PREMEM_POLICY_INIT) (
+  VOID
+  );
+
+///
+/// This PPI provides function to install default silicon policy
+///
+struct _PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI {
+  PEI_PREMEM_POLICY_INIT   PeiPreMemPolicyInit;
+};
+
+extern EFI_GUID gSiPreMemDefaultPolicyInitPpiGuid;
+
+#endif // _PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI_H_

+ 36 - 0
Silicon/Intel/KabylakeSiliconPkg/Include/Ppi/PeiSiDefaultPolicyInit.h

@@ -0,0 +1,36 @@
+/** @file
+  This file defines the PPI function for installing PostMem silicon policy
+  PPI with default settings.
+
+Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _PEI_SI_DEFAULT_POLICY_INIT_PPI_H_
+#define _PEI_SI_DEFAULT_POLICY_INIT_PPI_H_
+
+//
+// Forward declaration for the PEI_SI_DEFAULT_POLICY_INIT_PPI.
+//
+typedef struct _PEI_SI_DEFAULT_POLICY_INIT_PPI PEI_SI_DEFAULT_POLICY_INIT_PPI;
+
+/**
+  Initialize and install default silicon policy PPI
+**/
+typedef
+EFI_STATUS
+(EFIAPI *PEI_POLICY_INIT) (
+  VOID
+  );
+
+///
+/// This PPI provides function to install default silicon policy
+///
+struct _PEI_SI_DEFAULT_POLICY_INIT_PPI {
+  PEI_POLICY_INIT   PeiPolicyInit;
+};
+
+extern EFI_GUID gSiDefaultPolicyInitPpiGuid;
+
+#endif // _PEI_SI_DEFAULT_POLICY_INIT_PPI_H_

+ 48 - 5
Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiPolicyLib/PeiSiPolicyLib.c

@@ -2,7 +2,7 @@
   This file is PeiSiPolicyLib library creates default settings of RC
   Policy and installs RC Policy PPI.
 
-Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>
 SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
@@ -196,8 +196,6 @@ DumpSiPolicy (
 
 /**
   SiInstallPolicyPpi installs SiPolicyPpi.
-  While installed, RC assumes the Policy is ready and finalized. So please update and override
-  any setting before calling this function.
 
   @param[in] SiPolicyPpi         The pointer to Silicon Policy PPI instance
 
@@ -226,11 +224,56 @@ SiInstallPolicyPpi (
   Status = GetConfigBlock ((VOID *) SiPolicyPpi, &gSiConfigGuid, (VOID *) &SiConfig);
   ASSERT_EFI_ERROR (Status);
 
+  //
+  // Install Silicon Policy PPI
+  //
+  Status = PeiServicesInstallPpi (SiPolicyPpiDesc);
+  ASSERT_EFI_ERROR (Status);
+  return Status;
+}
+
+/**
+  SiInstallPolicyReadyPpi installs SiPolicyReadyPpi.
+  While installed, RC assumes the Policy is ready and finalized. So please update and override
+  any setting before calling this function.
+
+  @retval EFI_SUCCESS            The policy is installed.
+  @retval EFI_OUT_OF_RESOURCES   Insufficient resources to create buffer
+**/
+EFI_STATUS
+EFIAPI
+SiInstallPolicyReadyPpi (
+  VOID
+  )
+{
+  EFI_STATUS             Status;
+  EFI_PEI_PPI_DESCRIPTOR *SiPolicyPpiDesc;
+  SI_POLICY_PPI          *SiPolicy;
+
+  SiPolicyPpiDesc = (EFI_PEI_PPI_DESCRIPTOR *) AllocateZeroPool (sizeof (EFI_PEI_PPI_DESCRIPTOR));
+  if (SiPolicyPpiDesc == NULL) {
+    ASSERT (FALSE);
+    return EFI_OUT_OF_RESOURCES;
+  }
+
+  SiPolicyPpiDesc->Flags = EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST;
+  SiPolicyPpiDesc->Guid  = &gSiPolicyReadyPpiGuid;
+  SiPolicyPpiDesc->Ppi   = NULL;
+
+  SiPolicy = NULL;
+  Status = PeiServicesLocatePpi (
+             &gSiPolicyPpiGuid,
+             0,
+             NULL,
+             (VOID **)&SiPolicy
+             );
+  ASSERT_EFI_ERROR(Status);
+
   DEBUG ((DEBUG_INFO, "Dump Silicon Policy update by Platform...\n"));
-  DumpSiPolicy (SiPolicyPpi);
+  DumpSiPolicy (SiPolicy);
 
   //
-  // Install Silicon Policy PPI
+  // Install Silicon Policy Ready PPI
   //
   Status = PeiServicesInstallPpi (SiPolicyPpiDesc);
   ASSERT_EFI_ERROR (Status);

+ 5 - 3
Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiPolicyLib/PeiSiPolicyLib.inf

@@ -1,7 +1,7 @@
 ## @file
 # Component description file for the PeiSiPolicyLib library.
 #
-# Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>
 #
 # SPDX-License-Identifier: BSD-2-Clause-Patent
 #
@@ -49,8 +49,10 @@ gSiConfigGuid        ## CONSUMES
 
 
 [Ppis]
-gSiPolicyPpiGuid       ## PRODUCES
-gSiPreMemPolicyPpiGuid ## PRODUCES
+gSiPolicyPpiGuid            ## PRODUCES
+gSiPreMemPolicyPpiGuid      ## PRODUCES
+gSiPreMemPolicyReadyPpiGuid ## PRODUCES
+gSiPolicyReadyPpiGuid       ## PRODUCES
 
 [Pcd]
 gSiPkgTokenSpaceGuid.PcdSiCsmEnable  ## CONSUMES

+ 46 - 4
Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiPolicyLib/PeiSiPolicyLibPreMem.c

@@ -2,7 +2,7 @@
   This file is PeiSiPolicyLib library creates default settings of RC
   Policy and installs RC Policy PPI.
 
-Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>
 SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
@@ -69,8 +69,6 @@ SiCreatePreMemConfigBlocks (
 
 /**
   SiPreMemInstallPolicyPpi installs SiPreMemPolicyPpi.
-  While installed, RC assumes the Policy is ready and finalized. So please update and override
-  any setting before calling this function.
 
   @param[in] SiPreMemPolicyPpi   The pointer to Silicon Policy PPI instance
 
@@ -96,6 +94,50 @@ SiPreMemInstallPolicyPpi (
   SiPolicyPreMemPpiDesc->Guid  = &gSiPreMemPolicyPpiGuid;
   SiPolicyPreMemPpiDesc->Ppi   = SiPolicyPreMemPpi;
 
+  //
+  // Install Silicon Policy PPI
+  //
+  Status = PeiServicesInstallPpi (SiPolicyPreMemPpiDesc);
+  ASSERT_EFI_ERROR (Status);
+  return Status;
+}
+
+/**
+  SiPreMemInstallPolicyReadyPpi installs SiPreMemPolicyReadyPpi.
+  While installed, RC assumes the Policy is ready and finalized. So please update and override
+  any setting before calling this function.
+
+  @retval EFI_SUCCESS            The policy is installed.
+  @retval EFI_OUT_OF_RESOURCES   Insufficient resources to create buffer
+**/
+EFI_STATUS
+EFIAPI
+SiPreMemInstallPolicyReadyPpi (
+  VOID
+  )
+{
+  EFI_STATUS             Status;
+  EFI_PEI_PPI_DESCRIPTOR *SiPolicyPreMemPpiDesc;
+  SI_PREMEM_POLICY_PPI    *SiPolicyPreMemPpi;
+
+  SiPolicyPreMemPpiDesc = (EFI_PEI_PPI_DESCRIPTOR *) AllocateZeroPool (sizeof (EFI_PEI_PPI_DESCRIPTOR));
+  if (SiPolicyPreMemPpiDesc == NULL) {
+    ASSERT (FALSE);
+    return EFI_OUT_OF_RESOURCES;
+  }
+
+  SiPolicyPreMemPpiDesc->Flags = EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST;
+  SiPolicyPreMemPpiDesc->Guid  = &gSiPreMemPolicyReadyPpiGuid;
+  SiPolicyPreMemPpiDesc->Ppi   = NULL;
+
+  Status = PeiServicesLocatePpi (
+             &gSiPreMemPolicyPpiGuid,
+             0,
+             NULL,
+             (VOID **)&SiPolicyPreMemPpi
+             );
+  ASSERT_EFI_ERROR (Status);
+
   //
   // Print whole PCH_POLICY_PPI and serial out.
   //
@@ -114,7 +156,7 @@ SiPreMemInstallPolicyPpi (
   CpuPreMemPrintPolicy (SiPolicyPreMemPpi);
 
   //
-  // Install Silicon Policy PPI
+  // Install PreMem Silicon Policy Ready PPI
   //
   Status = PeiServicesInstallPpi (SiPolicyPreMemPpiDesc);
   ASSERT_EFI_ERROR (Status);

+ 25 - 7
Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPolicyInit.c

@@ -1,7 +1,7 @@
 /** @file
   This file is SampleCode for Intel PEI Platform Policy initialization.
 
-Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>
 SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
@@ -35,19 +35,37 @@ SiliconPolicyInitPostMem (
   IN OUT VOID *Policy
   )
 {
-  EFI_STATUS                   Status;
-  SI_POLICY_PPI                *SiPolicyPpi;
+  EFI_STATUS                            Status;
+  SI_POLICY_PPI                         *SiPolicyPpi;
+  PEI_SI_DEFAULT_POLICY_INIT_PPI        *PeiSiDefaultPolicyInitPpi;
 
   DEBUG ((DEBUG_INFO, "Silicon PEI Policy Initialization Start in Post-Memory...\n"));
 
   ASSERT (Policy == NULL);
 
   //
-  // Call SiCreateConfigBlocks to initialize Silicon Policy structure
-  // and get all Intel default policy settings.
+  // Locate Policy init PPI to install default silicon policy
   //
-  Status = SiCreateConfigBlocks (&SiPolicyPpi);
+  Status = PeiServicesLocatePpi (
+             &gSiDefaultPolicyInitPpiGuid,
+             0,
+             NULL,
+             (VOID **) &PeiSiDefaultPolicyInitPpi
+             );
   ASSERT_EFI_ERROR (Status);
+  if (PeiSiDefaultPolicyInitPpi != NULL) {
+    Status = PeiSiDefaultPolicyInitPpi->PeiPolicyInit ();
+    ASSERT_EFI_ERROR (Status);
+    if (Status == EFI_SUCCESS) {
+      Status = PeiServicesLocatePpi (
+                 &gSiPolicyPpiGuid,
+                 0,
+                 NULL,
+                 (VOID **) &SiPolicyPpi
+                 );
+      ASSERT_EFI_ERROR (Status);
+    }
+  }
 
   return SiPolicyPpi;
 }
@@ -78,7 +96,7 @@ SiliconPolicyDonePostMem (
   // While installed, RC assumes the Policy is ready and finalized. So please
   // update and override any setting before calling this function.
   //
-  Status = SiInstallPolicyPpi (SiPolicyPpi);
+  Status = SiInstallPolicyReadyPpi ();
   ASSERT_EFI_ERROR (Status);
 
   DEBUG ((DEBUG_INFO, "Silicon PEI Policy Initialization Done in Post-Memory\n"));

+ 3 - 1
Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPolicyInit.h

@@ -1,7 +1,7 @@
 /** @file
   Header file for the PolicyInitPei PEIM.
 
-Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>
 SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
@@ -12,6 +12,8 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
 #include <PiPei.h>
 #include <Library/DebugLib.h>
 #include <Library/MemoryAllocationLib.h>
+#include <Ppi/PeiPreMemSiDefaultPolicyInit.h>
+#include <Ppi/PeiSiDefaultPolicyInit.h>
 
 #include "PeiSiPolicyInit.h"
 

+ 27 - 12
Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPolicyInitPreMem.c

@@ -1,7 +1,7 @@
 /** @file
   This file is SampleCode for Intel PEI Platform Policy initialization.
 
-Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>
 SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
@@ -35,20 +35,38 @@ SiliconPolicyInitPreMem (
   IN OUT VOID *Policy
   )
 {
-  EFI_STATUS                   Status;
-  SI_PREMEM_POLICY_PPI         *SiPreMemPolicyPpi;
+  EFI_STATUS                            Status;
+  SI_PREMEM_POLICY_PPI                  *SiPreMemPolicyPpi;
+  PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI *PeiPreMemSiDefaultPolicyInitPpi;
 
   DEBUG ((DEBUG_INFO, "Silicon PEI Policy Initialization Start in Pre-Memory...\n"));
 
   ASSERT (Policy == NULL);
+  SiPreMemPolicyPpi = NULL;
 
   //
-  // Call SiCreatePreMemConfigBlocks to initialize platform policy structure
-  // and get all intel default policy settings.
+  // Locate Policy init PPI to install default silicon policy
   //
-  Status = SiCreatePreMemConfigBlocks (&SiPreMemPolicyPpi);
+  Status = PeiServicesLocatePpi (
+             &gSiPreMemDefaultPolicyInitPpiGuid,
+             0,
+             NULL,
+             (VOID **) &PeiPreMemSiDefaultPolicyInitPpi
+             );
   ASSERT_EFI_ERROR (Status);
-
+  if (PeiPreMemSiDefaultPolicyInitPpi != NULL) {
+    Status = PeiPreMemSiDefaultPolicyInitPpi->PeiPreMemPolicyInit ();
+    ASSERT_EFI_ERROR (Status);
+    if (Status == EFI_SUCCESS) {
+      Status = PeiServicesLocatePpi (
+                 &gSiPreMemPolicyPpiGuid,
+                 0,
+                 NULL,
+                 (VOID **) &SiPreMemPolicyPpi
+                 );
+      ASSERT_EFI_ERROR (Status);
+    }
+  }
   return SiPreMemPolicyPpi;
 }
 
@@ -69,16 +87,13 @@ SiliconPolicyDonePreMem (
   )
 {
   EFI_STATUS                   Status;
-  SI_PREMEM_POLICY_PPI         *SiPreMemPolicyPpi;
-
-  SiPreMemPolicyPpi = Policy;
 
   //
-  // Install SiPreMemPolicyPpi.
+  // Install Policy Ready PPI
   // While installed, RC assumes the Policy is ready and finalized. So please
   // update and override any setting before calling this function.
   //
-  Status = SiPreMemInstallPolicyPpi (SiPreMemPolicyPpi);
+  Status = SiPreMemInstallPolicyReadyPpi ();
   ASSERT_EFI_ERROR (Status);
 
   DEBUG ((DEBUG_INFO, "Silicon PEI Policy Initialization Done in Pre-Memory\n"));

+ 75 - 0
Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPostMemSiliconPolicyInitLib.inf

@@ -0,0 +1,75 @@
+## @file
+# Library functions for Policy Initialization Library.
+#
+# Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+################################################################################
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+################################################################################
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = PeiPostMemSiliconPolicyInitLib
+  FILE_GUID                      = FA0795E2-BCB3-4627-9FB3-A325548658B4
+  MODULE_TYPE                    = BASE
+  VERSION_STRING                 = 1.0
+  LIBRARY_CLASS                  = SiliconPolicyInitLib
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+#  VALID_ARCHITECTURES           = IA32
+#
+
+################################################################################
+#
+# Sources Section - list of files that are required for the build to succeed.
+#
+################################################################################
+
+[Sources]
+  PeiPolicyInit.c
+  PeiPolicyInit.h
+
+################################################################################
+#
+# Package Dependency Section - list of Package files that are required for
+#                              this module.
+#
+################################################################################
+
+[Packages]
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  KabylakeSiliconPkg/SiPkg.dec
+  UefiCpuPkg/UefiCpuPkg.dec
+
+[LibraryClasses]
+  SiPolicyLib
+  DebugLib
+  PeiServicesLib
+
+[Ppis]
+  gSiDefaultPolicyInitPpiGuid  ## CONSUMES
+
+[Pcd]
+  #
+  # Below PCD may not be consumed by this library but still adding them here
+  # to make sure all of them can be built into PcdDataBase.
+  # Those PCD will be consumed by FSP in dispatch mode as DynamicEx type.
+  #
+  gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber
+  gSiPkgTokenSpaceGuid.PcdSiPciExpressBaseAddress
+  gSiPkgTokenSpaceGuid.PcdSiPciExpressRegionLength
+  gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress
+  gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize
+  gUefiCpuPkgTokenSpaceGuid.PcdCpuApLoopMode
+  gUefiCpuPkgTokenSpaceGuid.PcdCpuApTargetCstate
+
+[Depex]
+  gSiDefaultPolicyInitPpiGuid

+ 8 - 3
Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiSiliconPolicyInitLib.inf → Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPreMemSiliconPolicyInitLib.inf

@@ -1,7 +1,7 @@
 ### @file
 # Library functions for Policy Initialization Library.
 #
-# Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>
 #
 # SPDX-License-Identifier: BSD-2-Clause-Patent
 #
@@ -14,7 +14,7 @@
 ################################################################################
 [Defines]
   INF_VERSION                    = 0x00010005
-  BASE_NAME                      = PeiSiliconPolicyInitLib
+  BASE_NAME                      = PeiPreMemSiliconPolicyInitLib
   FILE_GUID                      = 80920B16-7778-4793-878E-4555F68BDC69
   MODULE_TYPE                    = BASE
   VERSION_STRING                 = 1.0
@@ -34,7 +34,6 @@
 
 [Sources]
   PeiPolicyInitPreMem.c
-  PeiPolicyInit.c
   PeiPolicyInit.h
 
 ################################################################################
@@ -53,3 +52,9 @@
   SiPolicyLib
   DebugLib
   PeiServicesLib
+
+[Ppis]
+  gSiPreMemDefaultPolicyInitPpiGuid  ## CONSUMES
+
+[Depex]
+  gSiPreMemDefaultPolicyInitPpiGuid

+ 3 - 2
Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLibFsp/PeiSiliconPolicyInitLibFsp.inf

@@ -1,7 +1,7 @@
 ### @file
 # Library functions for Fsp Policy Initialization Library.
 #
-# Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>
 #
 # SPDX-License-Identifier: BSD-2-Clause-Patent
 #
@@ -72,6 +72,7 @@
   MemoryAllocationLib
   DebugPrintErrorLevelLib
   FspWrapperApiLib
+  SiPolicyLib
 
 [Pcd]
   gSiPkgTokenSpaceGuid.PcdTsegSize                    ## CONSUMES
@@ -84,7 +85,7 @@
   gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress    ## CONSUMES
   gIntelFsp2WrapperTokenSpaceGuid.PcdFspsUpdDataAddress ## CONSUMES
   gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress    ## CONSUMES
- 
+
 [Ppis]
   gSiPolicyPpiGuid                              ## CONSUMES
   gSiPreMemPolicyPpiGuid                        ## CONSUMES

+ 1 - 0
Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLibFsp/PeiSiliconPolicyInitLibFspAml.inf

@@ -72,6 +72,7 @@
   MemoryAllocationLib
   DebugPrintErrorLevelLib
   FspWrapperApiLib
+  SiPolicyLib
 
 [Pcd]
   gSiPkgTokenSpaceGuid.PcdTsegSize                    ## CONSUMES

+ 3 - 3
Silicon/Intel/KabylakeSiliconPkg/Me/Library/PeiMePolicyLib/PeiMePolicyLib.c

@@ -1,7 +1,7 @@
 /** @file
   This file is PeiMePolicy library.
 
-Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>
 SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
@@ -97,7 +97,7 @@ PrintMePeiPreMemConfig (
   DEBUG_CODE_BEGIN ();
   DEBUG ((DEBUG_INFO, "------------------------ ME_PEI_PREMEM_CONFIG -----------------\n"));
   DEBUG ((DEBUG_INFO, " Revision                  : 0x%x\n", MePeiPreMemConfig->Header.Revision));
-  ASSERT (MePeiPreMemConfig->Header.Revision == ME_PEI_PREMEM_CONFIG_REVISION);
+  ASSERT (MePeiPreMemConfig->Header.Revision >= ME_PEI_PREMEM_CONFIG_REVISION);
 
   DEBUG ((DEBUG_INFO, " HeciTimeouts              : 0x%x\n", MePeiPreMemConfig->HeciTimeouts));
   DEBUG ((DEBUG_INFO, " DidInitStat               : 0x%x\n", MePeiPreMemConfig->DidInitStat));
@@ -129,7 +129,7 @@ PrintMePeiConfig (
   DEBUG_CODE_BEGIN ();
   DEBUG ((DEBUG_INFO, "------------------------ ME_PEI_CONFIG -----------------\n"));
   DEBUG ((DEBUG_INFO, " Revision                  : 0x%x\n", MePeiConfig->Header.Revision));
-  ASSERT (MePeiConfig->Header.Revision == ME_PEI_CONFIG_REVISION);
+  ASSERT (MePeiConfig->Header.Revision >= ME_PEI_CONFIG_REVISION);
 
   DEBUG ((DEBUG_INFO, " EndOfPostMessage          : 0x%x\n", MePeiConfig->EndOfPostMessage));
   DEBUG ((DEBUG_INFO, " Heci3Enabled              : 0x%x\n", MePeiConfig->Heci3Enabled));

+ 4 - 1
Silicon/Intel/KabylakeSiliconPkg/SiPkg.dec

@@ -348,7 +348,10 @@ gPeiTpmInitializationDonePpiGuid = {0xa030d115, 0x54dd, 0x447b, { 0x90, 0x64, 0x
 gSiPolicyPpiGuid  =  {0xaebffa01, 0x7edc, 0x49ff, {0x8d, 0x88, 0xcb, 0x84, 0x8c, 0x5e, 0x86, 0x70}}
 gSiPreMemPolicyPpiGuid = {0xc133fe57, 0x17c7, 0x4b09, {0x8b, 0x3c, 0x97, 0xc1, 0x89, 0xd0, 0xab, 0x8d}}
 gFspTempRamExitPpiGuid      = {0xbc1cfbdb, 0x7e50, 0x42be, {0xb4, 0x87, 0x22, 0xe0, 0xa9, 0x0c, 0xb0, 0x52}}
-
+gSiPolicyReadyPpiGuid       = {0xd570de8c, 0xb9c4, 0x4ffa, {0xad, 0xee, 0xa5, 0x82, 0x7c, 0xe3, 0x17, 0x79}}
+gSiPreMemPolicyReadyPpiGuid = {0x85270bef, 0x6984, 0x4375, {0xa6, 0xea, 0xb5, 0xaa, 0x90, 0x6e, 0xdd, 0x4a}}
+gSiPreMemDefaultPolicyInitPpiGuid =  {0xfec36242, 0xf8d8, 0x4b43, {0x87, 0x94, 0x4f, 0x1f, 0x9f, 0x63, 0x8d, 0xdc}}
+gSiDefaultPolicyInitPpiGuid = {0xf69abf86, 0x4048, 0x44ef, { 0xa8, 0xef, 0x6c, 0x7f, 0x20, 0x4a, 0xc8, 0xda}}
 ##
 ## SystemAgent
 ##

+ 14 - 2
Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Include/ConfigBlock/GraphicsPeiConfig.h

@@ -1,7 +1,7 @@
 /** @file
   Policy definition for Internal Graphics Config Block (PostMem)
 
-Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>
 SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
@@ -19,8 +19,20 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
 **/
 typedef struct {
   CONFIG_BLOCK_HEADER   Header;                   ///< Offset 0-27 Config Block Header
+  UINT32                RenderStandby     : 1;    ///< Offset 28:0 :<b>(Test)</b> This field is used to enable or disable RC6 (Render Standby): 0=FALSE, <b>1=TRUE</b>
+  UINT32                PmSupport         : 1;    ///< Offset 28:1 :<b>(Test)</b> IGD PM Support TRUE/FALSE: 0=FALSE, <b>1=TRUE</b>
+  UINT32                PavpEnable        : 1;    ///< Offset 28:2 :IGD PAVP TRUE/FALSE: 0=FALSE, <b>1=TRUE</b>
+  /**
+    Offset 28:3
+    CdClock Frequency select\n
+    0   = 337.5 Mhz, 1 = 450 Mhz,\n
+    2   = 540 Mhz,<b> 3 = 675 Mhz</b>,\n
+  **/
+  UINT32                CdClock            : 3;
   UINT32                PeiGraphicsPeimInit: 1;   ///< Offset 28:6 :This policy is used to enable/disable Intel Gfx PEIM.<b>0- Disable</b>, 1- Enable
-  UINT32                RsvdBits0          : 31;  ///< Offser 28:16 :Reserved for future use
+  UINT32                CdynmaxClampEnable : 1;   ///< Offset 28:7 : This policy is used to enable/disable CDynmax Clamping Feature (CCF) <b>1- Enable</b>, 0- Disable
+  UINT32                GtFreqMax          : 8;   ///< Offset 28:8 : <b>(Test)</b> Max GT frequency limited by user in multiples of 50MHz: Default value which indicates normal frequency is <b>0xFF</b>
+  UINT32                RsvdBits0          : 16;  ///< Offser 28:16 :Reserved for future use
   VOID*                 LogoPtr;                  ///< Offset 32 Address of Logo to be displayed in PEI
   UINT32                LogoSize;                 ///< Offset 36 Logo Size
   VOID*                 GraphicsConfigPtr;        ///< Offset 40 Address of the Graphics Configuration Table

+ 2 - 2
Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/DxeSaPolicyLib/DxeSaPolicyLib.c

@@ -1,7 +1,7 @@
 /** @file
   This file provide services for DXE phase policy default initialization
 
-Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>
 SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
@@ -38,7 +38,7 @@ SaPrintPolicyProtocol (
 
   DEBUG ((DEBUG_INFO, "\n------------------------ SA Policy (DXE) print BEGIN -----------------\n"));
   DEBUG ((DEBUG_INFO, "Revision : %x\n", SaPolicy->TableHeader.Header.Revision));
-  ASSERT (SaPolicy->TableHeader.Header.Revision == SA_POLICY_PROTOCOL_REVISION);
+  ASSERT (SaPolicy->TableHeader.Header.Revision >= SA_POLICY_PROTOCOL_REVISION);
   DEBUG ((DEBUG_INFO, "------------------------ SA_MISC_CONFIGURATION -----------------\n"));
   DEBUG ((DEBUG_INFO, " EnableAbove4GBMmio : %x\n", MiscDxeConfig->EnableAbove4GBMmio));
   DEBUG ((DEBUG_INFO, "\n------------------------ SA Policy (DXE) print END -----------------\n"));

+ 1 - 0
Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/PeiSaPolicyLib/PeiSaPolicyLib.inf

@@ -28,6 +28,7 @@ CpuMailboxLib
 SiConfigBlockLib
 RngLib
 SmbusLib
+PchCycleDecodingLib
 
 [Packages]
 MdePkg/MdePkg.dec

+ 7 - 7
Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/PeiSaPolicyLib/SaPrintPolicy.c

@@ -1,7 +1,7 @@
 /** @file
   This file provides service for PEI phase policy printing
 
-Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>
 SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
@@ -41,11 +41,11 @@ SaPrintPolicyPpiPreMem (
 
   DEBUG ((DEBUG_INFO, "\n------------------------ SA Policy (PEI PreMem) Print BEGIN -----------------\n"));
   DEBUG ((DEBUG_INFO, "Revision : 0x%x\n", SiPolicyPreMemPpi->TableHeader.Header.Revision));
-  ASSERT (SiPolicyPreMemPpi->TableHeader.Header.Revision == SI_PREMEM_POLICY_REVISION);
+  ASSERT (SiPolicyPreMemPpi->TableHeader.Header.Revision >= SI_PREMEM_POLICY_REVISION);
 
   DEBUG ((DEBUG_INFO, "------------------------ SA_MISC_PEI_PREMEM_CONFIG  -----------------\n"));
   DEBUG ((DEBUG_INFO, " Revision : %d\n", MiscPeiPreMemConfig->Header.Revision));
-  ASSERT (MiscPeiPreMemConfig->Header.Revision == SA_MISC_PEI_PREMEM_CONFIG_REVISION);
+  ASSERT (MiscPeiPreMemConfig->Header.Revision >= SA_MISC_PEI_PREMEM_CONFIG_REVISION);
   DEBUG ((DEBUG_INFO, " SpdAddressTable[%d] :", SA_MC_MAX_SOCKETS));
   for (Index = 0; Index < SA_MC_MAX_SOCKETS; Index++) {
     DEBUG ((DEBUG_INFO, " 0x%x", MiscPeiPreMemConfig->SpdAddressTable[Index]));
@@ -56,7 +56,7 @@ SaPrintPolicyPpiPreMem (
   DEBUG ((DEBUG_INFO, "------------------------ MEMORY_CONFIG ------------------------------\n"));
   DEBUG ((DEBUG_INFO, " Guid                : %g\n", &MemConfig->Header.GuidHob.Name));
   DEBUG ((DEBUG_INFO, " Revision            : %d\n",   MemConfig->Header.Revision));
-  ASSERT (MemConfig->Header.Revision == MEMORY_CONFIG_REVISION);
+  ASSERT (MemConfig->Header.Revision >= MEMORY_CONFIG_REVISION);
   DEBUG ((DEBUG_INFO, " Size                : 0x%x\n", MemConfig->Header.GuidHob.Header.HobLength));
   DEBUG ((DEBUG_INFO, " HobBufferSize       : 0x%x\n", MemConfig->HobBufferSize));
   DEBUG ((DEBUG_INFO, " EccSupport          : 0x%x\n", MemConfig->EccSupport));
@@ -296,17 +296,17 @@ SaPrintPolicyPpi (
 
   DEBUG ((DEBUG_INFO, "\n------------------------ SA Policy (PEI) Print BEGIN -----------------\n"));
   DEBUG ((DEBUG_INFO, "Revision : 0x%x\n", SiPolicyPpi->TableHeader.Header.Revision));
-  ASSERT (SiPolicyPpi->TableHeader.Header.Revision == SI_POLICY_REVISION);
+  ASSERT (SiPolicyPpi->TableHeader.Header.Revision >= SI_POLICY_REVISION);
   DEBUG ((DEBUG_INFO, "------------------------ GRAPHICS_PEI_CONFIG -----------------\n"));
   DEBUG ((DEBUG_INFO, " Revision : %d\n", GtConfig->Header.Revision));
-  ASSERT (GtConfig->Header.Revision == GRAPHICS_PEI_CONFIG_REVISION);
+  ASSERT (GtConfig->Header.Revision >= GRAPHICS_PEI_CONFIG_REVISION);
   DEBUG ((DEBUG_INFO, " PeiGraphicsPeimInit : 0x%x\n", GtConfig->PeiGraphicsPeimInit));
   DEBUG ((DEBUG_INFO, " LogoPtr : 0x%x\n", GtConfig->LogoPtr));
   DEBUG ((DEBUG_INFO, " LogoSize : 0x%x\n", GtConfig->LogoSize));
   DEBUG ((DEBUG_INFO, " GraphicsConfigPtr : 0x%x\n", GtConfig->GraphicsConfigPtr));
   DEBUG ((DEBUG_INFO, "------------------------ VTD_CONFIG -----------------\n"));
   DEBUG ((DEBUG_INFO, " Revision : %d\n", Vtd->Header.Revision));
-  ASSERT (Vtd->Header.Revision == VTD_CONFIG_REVISION);
+  ASSERT (Vtd->Header.Revision >= VTD_CONFIG_REVISION);
   DEBUG ((DEBUG_INFO, " VtdDisable : 0x%x\n", Vtd->VtdDisable));
   DEBUG ((DEBUG_INFO, " X2ApicOptOut : 0x%x\n", Vtd->X2ApicOptOut));
   DEBUG ((DEBUG_INFO, " VtdBaseAddress[%d] :", SA_VTD_ENGINE_NUMBER));