CpuDataStruct.h 6.2 KB

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  1. /** @file
  2. This file declares various data structures used in CPU reference code.
  3. Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>
  4. SPDX-License-Identifier: BSD-2-Clause-Patent
  5. **/
  6. #ifndef _CPU_DATA_STRUCT_H
  7. #define _CPU_DATA_STRUCT_H
  8. //
  9. // The reason for changing the state of the processor Only applies to Disabling processors.
  10. // In future, we can add add/remove support
  11. //
  12. #define CPU_CAUSE_NOT_DISABLED 0x0000
  13. #define CPU_CAUSE_INTERNAL_ERROR 0x0001
  14. #define CPU_CAUSE_THERMAL_ERROR 0x0002
  15. #define CPU_CAUSE_SELFTEST_FAILURE 0x0004
  16. #define CPU_CAUSE_PREBOOT_TIMEOUT 0x0008
  17. #define CPU_CAUSE_FAILED_TO_START 0x0010
  18. #define CPU_CAUSE_CONFIG_ERROR 0x0020
  19. #define CPU_CAUSE_USER_SELECTION 0x0080
  20. #define CPU_CAUSE_BY_ASSOCIATION 0x0100
  21. #define CPU_CAUSE_UNSPECIFIED 0x8000
  22. #define MAX_MICROCODE_PATCH_SIZE 0x20000
  23. typedef UINT32 CPU_STATE_CHANGE_CAUSE;
  24. ///
  25. /// The data structure is used retrieve data required for MP initialization during S3 resume.
  26. ///
  27. typedef struct {
  28. BOOLEAN APState; ///< Indicates whether the newstate of the AP is enabled or disabled.
  29. BOOLEAN S3BootPath; ///< TRUE: S3 Boot path. FALSE: Regular boot path.
  30. EFI_PHYSICAL_ADDRESS WakeUpBuffer; ///< Buffer location used during AP Initialization
  31. EFI_PHYSICAL_ADDRESS GdtrProfile; ///< Address of Global Descriptor Table
  32. EFI_PHYSICAL_ADDRESS IdtrProfile; ///< address of Interrupt Descriptor Table
  33. EFI_PHYSICAL_ADDRESS CpuPrivateData; ///< Address of CPU_PRIVATE_DATA structure
  34. EFI_PHYSICAL_ADDRESS StackAddress; ///< Address of APs's stacks
  35. EFI_PHYSICAL_ADDRESS SmramBase; ///< @deprecated Address of SMRAM base as seen by software executing on the processors
  36. EFI_PHYSICAL_ADDRESS SmmStartImageBase; ///< @deprecated Address of SMM Start Image Base
  37. UINT32 SmmStartImageSize; ///< @deprecated Size of SMM Start Image
  38. UINT32 NumberOfCpus; ///< Number of processors
  39. } ACPI_CPU_DATA;
  40. ///
  41. /// CPU information stored in SMRAM during DXE.
  42. ///
  43. typedef struct {
  44. //
  45. // Guid as Signature.
  46. //
  47. EFI_GUID HeaderGuid;
  48. EFI_PHYSICAL_ADDRESS AcpiCpuPointer;
  49. ACPI_CPU_DATA AcpiCpuData;
  50. //
  51. // It points the data defined below.
  52. //
  53. EFI_PHYSICAL_ADDRESS GdtrProfileOffset;
  54. EFI_PHYSICAL_ADDRESS GdtOffset;
  55. EFI_PHYSICAL_ADDRESS IdtrProfileOffset;
  56. EFI_PHYSICAL_ADDRESS IdtOffset;
  57. EFI_PHYSICAL_ADDRESS CpuPrivateDataOffset;
  58. EFI_PHYSICAL_ADDRESS S3BspMtrrTableOffset;
  59. ///
  60. /// We need put all the data buffer here as well.
  61. /// These data will be copied to original location in S3.
  62. ///
  63. //
  64. // DataBuffer size
  65. //
  66. UINT32 GdtrProfileSize;
  67. UINT32 GdtSize;
  68. UINT32 IdtrProfileSize;
  69. UINT32 IdtSize;
  70. UINT32 CpuPrivateDataSize;
  71. UINT32 S3BspMtrrTableSize;
  72. } SMRAM_CPU_DATA;
  73. ///
  74. /// Structure to hold the return value of AsmCpuid instruction
  75. ///
  76. typedef struct {
  77. UINT32 RegEax; ///< Value of EAX.
  78. UINT32 RegEbx; ///< Value of EBX.
  79. UINT32 RegEcx; ///< Value of ECX.
  80. UINT32 RegEdx; ///< Value of EDX.
  81. } EFI_CPUID_REGISTER;
  82. ///
  83. /// Structure to describe microcode header
  84. ///
  85. typedef struct {
  86. UINT32 HeaderVersion; ///< Version number of the update header.
  87. UINT32 UpdateRevision; ///< Unique version number for the update.
  88. UINT32 Date; ///< Date of the update creation.
  89. UINT32 ProcessorId; ///< Signature of the processor that requires this update.
  90. UINT32 Checksum; ///< Checksum of update data and header.
  91. UINT32 LoaderRevision; ///< Version number of the microcode loader program.
  92. UINT32 ProcessorFlags; ///< Lower 4 bits denoting platform type information.
  93. UINT32 DataSize; ///< Size of encoded data in bytes.
  94. UINT32 TotalSize; ///< Total size of microcode update in bytes.
  95. UINT8 Reserved[12]; ///< Reserved bits.
  96. } CPU_MICROCODE_HEADER;
  97. ///
  98. /// Structure to describe the extended signature table header of the microcode update
  99. ///
  100. typedef struct {
  101. UINT32 ExtendedSignatureCount; ///< Number of extended signature structures.
  102. UINT32 ExtendedTableChecksum; ///< Checksum of update extended processor signature table.
  103. UINT8 Reserved[12]; ///< Reserved bits.
  104. } CPU_MICROCODE_EXTENDED_TABLE_HEADER;
  105. ///
  106. /// Structure to describe the data of the extended table of the microcode update
  107. ///
  108. typedef struct {
  109. UINT32 ProcessorSignature; ///< Extended signature of the processor that requires this update
  110. UINT32 ProcessorFlag; ///< Lower 4 bits denoting platform type information
  111. UINT32 ProcessorChecksum; ///< checksum of each of the extended update
  112. } CPU_MICROCODE_EXTENDED_TABLE;
  113. #pragma pack(1)
  114. ///
  115. /// MSR_REGISTER definition as a Union of QWORDS, DWORDS and BYTES
  116. ///
  117. typedef union _MSR_REGISTER {
  118. UINT64 Qword; ///< MSR value in 64 bit QWORD.
  119. ///
  120. /// MSR value represented in two DWORDS
  121. ///
  122. struct {
  123. UINT32 Low; ///< Lower DWORD of the 64 bit MSR value.
  124. UINT32 High; ///< Higher DWORD of the 64 bit MSR value.
  125. } Dwords;
  126. ///
  127. /// MSR value represented in eight bytes.
  128. ///
  129. struct {
  130. UINT8 FirstByte; ///< First byte of the 64 bit MSR value.
  131. UINT8 SecondByte; ///< Second byte of the 64 bit MSR value.
  132. UINT8 ThirdByte; ///< Third byte of the 64 bit MSR value.
  133. UINT8 FouthByte; ///< Fourth byte of the 64 bit MSR value.
  134. UINT8 FifthByte; ///< Fifth byte of the 64 bit MSR value.
  135. UINT8 SixthByte; ///< Sixth byte of the 64 bit MSR value.
  136. UINT8 SeventhByte; ///< Seventh byte of the 64 bit MSR value.
  137. UINT8 EighthByte; ///< Eigth byte of the 64 bit MSR value.
  138. } Bytes;
  139. } MSR_REGISTER;
  140. ///
  141. /// Store BIST data for BSP.
  142. ///
  143. typedef struct {
  144. UINT32 ApicId; ///< APIC ID
  145. UINT32 Health; ///< BIST result
  146. } BIST_HOB_DATA;
  147. ///
  148. /// Processor trace buffer size selection.
  149. ///
  150. typedef enum {
  151. Enum4K = 0,
  152. Enum8K,
  153. Enum16K,
  154. Enum32K,
  155. Enum64K,
  156. Enum128K,
  157. Enum256K,
  158. Enum512K,
  159. Enum1M,
  160. Enum2M,
  161. Enum4M,
  162. Enum8M,
  163. Enum16M,
  164. Enum32M,
  165. Enum64M,
  166. Enum128M,
  167. EnumProcTraceMemDisable
  168. } PROC_TRACE_MEM_SIZE;
  169. #pragma pack()
  170. #endif