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+/** @file
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+
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+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
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+SPDX-License-Identifier: BSD-2-Clause-Patent
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+
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+**/
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+
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+ //
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+ // BIOS parameter BIOS_ACPI_PARAM
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+ //
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+ OperationRegion (PSYS, SystemMemory, 0x30584946, 0x400) // (FIX0 - Patched by ACPI Platform Driver during POST)
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+ Field (PSYS, ByteAcc, NoLock, Preserve) {
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+ // IOAPIC Start
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+ PLAT , 32, // Platform ID
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+ Offset (0x04), //
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+#if MAX_SOCKET > 4
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+ AP00 , 1, // PC00 IOAPIC Enable
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+ AP01 , 1, // PC01 IOAPIC Enable
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+ AP02 , 1, // PC02 IOAPIC Enable
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+ AP03 , 1, // PC03 IOAPIC Enable
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+ AP04 , 1, // PC04 IOAPIC Enable
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+ AP05 , 1, // PC05 IOAPIC Enable
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+ AP06 , 1, // PC06 IOAPIC Enable
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+ AP07 , 1, // PC07 IOAPIC Enable
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+ AP08 , 1, // PC08 IOAPIC Enable
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+ AP09 , 1, // PC09 IOAPIC Enable
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+ AP10 , 1, // PC10 IOAPIC Enable
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+ AP11 , 1, // PC11 IOAPIC Enable
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+ AP12 , 1, // PC12 IOAPIC Enable
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+ AP13 , 1, // PC13 IOAPIC Enable
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+ AP14 , 1, // PC14 IOAPIC Enable
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+ AP15 , 1, // PC15 IOAPIC Enable
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+ AP16 , 1, // PC16 IOAPIC Enable
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+ AP17 , 1, // PC17 IOAPIC Enable
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+ AP18 , 1, // PC18 IOAPIC Enable
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+ AP19 , 1, // PC19 IOAPIC Enable
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+ AP20 , 1, // PC20 IOAPIC Enable
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+ AP21 , 1, // PC21 IOAPIC Enable
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+ AP22 , 1, // PC22 IOAPIC Enable
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+ AP23 , 1, // PC23 IOAPIC Enable
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+ AP24 , 1, // PC24 IOAPIC Enable
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+ AP25 , 1, // 8S PC25 IOAPIC Enable
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+ AP26 , 1, // 8S PC26 IOAPIC Enable
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+ AP27 , 1, // 8S PC27 IOAPIC Enable
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+ AP28 , 1, // 8S PC28 IOAPIC Enable
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+ AP29 , 1, // 8S PC29 IOAPIC Enable
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+ AP30 , 1, // 8S PC30 IOAPIC Enable
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+ AP31 , 1, // 8S PC31 IOAPIC Enable
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+#else
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+ APC0 , 1, // PCH IOAPIC Enable
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+ AP00 , 1, // PC00 IOAPIC Enable
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+ AP01 , 1, // PC01 IOAPIC Enable
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+ AP02 , 1, // PC02 IOAPIC Enable
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+ AP03 , 1, // PC03 IOAPIC Enable
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+ AP04 , 1, // PC04 IOAPIC Enable
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+ AP05 , 1, // PC05 IOAPIC Enable
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+ AP06 , 1, // PC06 IOAPIC Enable
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+ AP07 , 1, // PC07 IOAPIC Enable
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+ AP08 , 1, // PC08 IOAPIC Enable
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+ AP09 , 1, // PC09 IOAPIC Enable
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+ AP10 , 1, // PC10 IOAPIC Enable
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+ AP11 , 1, // PC11 IOAPIC Enable
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+ AP12 , 1, // PC12 IOAPIC Enable
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+ AP13 , 1, // PC13 IOAPIC Enable
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+ AP14 , 1, // PC14 IOAPIC Enable
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+ AP15 , 1, // PC15 IOAPIC Enable
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+ AP16 , 1, // PC16 IOAPIC Enable
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+ AP17 , 1, // PC17 IOAPIC Enable
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+ AP18 , 1, // PC18 IOAPIC Enable
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+ AP19 , 1, // PC19 IOAPIC Enable
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+ AP20 , 1, // PC20 IOAPIC Enable
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+ AP21 , 1, // PC21 IOAPIC Enable
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+ AP22 , 1, // PC22 IOAPIC Enable
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+ AP23 , 1, // PC23 IOAPIC Enable
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+ RESA , 7, // Unused
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+#endif
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+ Offset (0x08),
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+ SKOV , 1, // Override ApicId socket field
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+ , 7, // Unused
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+ // IOAPIC End
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+
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+ // Power Managment Start
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+ Offset (0x09),
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+ , 1, //
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+ CSEN , 1, // C State Enable
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+ C3EN , 1, // OS C3 Report Enbale
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+ C6EN , 1, // C6 Enable
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+ C7EN , 1, // C7 Enable
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+ MWOS , 1, // MWAIT support Enable
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+ PSEN , 1, // P State Enable
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+ EMCA , 1, // EMCA Enable
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+ Offset (0x0A),
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+ HWAL , 2, // PSD HW_ALL Enable
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+ KPRS , 1, // KB present Flag
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+ MPRS , 1, // Mouse present Flag
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+ TSEN , 1, // T State Enable Flag
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+ FGTS , 1, // Fine grained T state Flag
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+ OSCX , 1, // OS C States
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+ RESX , 1, // Unused
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+ // Power Management End
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+
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+ // RAS Start
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+ Offset (0x0B),
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+ CPHP , 8, // Bit field for determining CPU hotplug event is happening, Update every time CPU Hotpug event is registered as valid
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+ // Bit0 CPU0 O*L Request
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+ // Bit1 CPU1 O*L Request
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+ // Bit2 CPU2 O*L Request
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+ // Bit3 CPU3 O*L Request
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+ // Bit4-7 Reserved
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+ IIOP , 8, // Bit field for determining IIO hotplug event is happening, Update every time IIO Hotpug event is registered as valid
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+ // Bit0 IIO1 O*L Request
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+ // Bit1 IIO2 O*L Request
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+ // Bit2 IIO3 O*L Request
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+ // Bit3-7 Reserved
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+ IIOH , 64, // IIO bit Mask, what IIOs are present for STA method, Update every time IIO hotplug event happens and at boot time (Patched by ACPI Platform Driver during POST)
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+ PRBM , 32, // Processor Bit mask, what sockets are present for STA method, Update every time hotplug event happen and at boot time (Patched by ACPI Platform Driver during POST)
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+ P0ID , 32, // Processor 0 APIC ID base
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+ P1ID , 32, // Processor 1 APIC ID base
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+ P2ID , 32, // Processor 2 APIC ID base
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+ P3ID , 32, // Processor 3 APIC ID base
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+ P4ID , 32, // Processor 4 APIC ID base
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+ P5ID , 32, // Processor 5 APIC ID base
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+ P6ID , 32, // Processor 6 APIC ID base
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+ P7ID , 32, // Processor 7 APIC ID base
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+ P0BM , 64, // Processor 0 Bit mask, what cores are present for STA method
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+ P1BM , 64, // Processor 1 Bit mask, what cores are present for STA method
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+ P2BM , 64, // Processor 2 Bit mask, what cores are present for STA method
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+ P3BM , 64, // Processor 3 Bit mask, what cores are present for STA method
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+ P4BM , 64, // Processor 4 Bit mask, what cores are present for STA method
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+ P5BM , 64, // Processor 5 Bit mask, what cores are present for STA method
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+ P6BM , 64, // Processor 6 Bit mask, what cores are present for STA method
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+ P7BM , 64, // Processor 7 Bit mask, what cores are present for STA method
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+ MEBM , 16, // Memory controller bit mask what memory controllers are present, for STA Method
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+ MEBC , 16, // Memory controller change event mask what memory controllers have been changed, for notify
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+ CFMM , 32, // MMCFG Base
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+ TSSZ , 32, // TSEG Size.
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+ M0BS , 64, // Memory Controller Base 0
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+ M1BS , 64, // Memory Controller Base 1
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+ M2BS , 64, // Memory Controller Base 2
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+ M3BS , 64, // Memory Controller Base 3
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+ M4BS , 64, // Memory Controller Base 4
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+ M5BS , 64, // Memory Controller Base 5
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+ M6BS , 64, // Memory Controller Base 6
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+ M7BS , 64, // Memory Controller Base 7
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+ M0RN , 64, // Memory Controller Range 0
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+ M1RN , 64, // Memory Controller Range 1
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+ M2RN , 64, // Memory Controller Range 2
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+ M3RN , 64, // Memory Controller Range 3
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+ M4RN , 64, // Memory Controller Range 4
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+ M5RN , 64, // Memory Controller Range 5
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+ M6RN , 64, // Memory Controller Range 6
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+ M7RN , 64, // Memory Controller Range 7
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+ SMI0 , 32, // Parameter0 used for faked SMI request
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+ SMI1 , 32, // Parameter1 used for faked SMI request
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+ SMI2 , 32, // Parameter2 used for faked SMI request
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+ SMI3 , 32, // Parameter3 used for faked SMI request
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+ SCI0 , 32, // Parameter0 used for faked SCI request
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+ SCI1 , 32, // Parameter1 used for faked SCI request
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+ SCI2 , 32, // Parameter2 used for faked SCI request
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+ SCI3 , 32, // Parameter3 used for faked SCI request
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+ MADD , 64, // Migration ActionRegion GAS address. (Migration support written for 8 CPU socket system. In a 4 socket system, CPU4-7 and MEM8-15 are invalid.)
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+ CUU0 , 128, // CPU0 UUID
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+ CUU1 , 128, // CPU1 UUID
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+ CUU2 , 128, // CPU2 UUID
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+ CUU3 , 128, // CPU3 UUID
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+ CUU4 , 128, // CPU4 UUID
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+ CUU5 , 128, // CPU5 UUID
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+ CUU6 , 128, // CPU6 UUID
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+ CUU7 , 128, // CPU7 UUID
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+ CPSP , 8, // CPU spare bitmap. 1 == IsSpare.
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+ ME00 , 128, // MEM0 UUID
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+ ME01 , 128, // MEM1 UUID
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+ ME10 , 128, // MEM2 UUID
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+ ME11 , 128, // MEM3 UUID
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+ ME20 , 128, // MEM4 UUID
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+ ME21 , 128, // MEM5 UUID
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+ ME30 , 128, // MEM6 UUID
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+ ME31 , 128, // MEM7 UUID
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+ ME40 , 128, // MEM8 UUID
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+ ME41 , 128, // MEM9 UUID
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+ ME50 , 128, // MEM10 UUID
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+ ME51 , 128, // MEM11 UUID
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+ ME60 , 128, // MEM12 UUID
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+ ME61 , 128, // MEM13 UUID
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+ ME70 , 128, // MEM14 UUID
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+ ME71 , 128, // MEM15 UUID
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+ MESP , 16, // Memory module spare bitmap. 1 == IsSpare.
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+ LDIR , 64, // L1 Directory Address
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+ PRID , 32, // Processor ID
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+ AHPE , 8, // ACPI PCIe hot plug enable.
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+ // RAS End
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+
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+ // VTD Start
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+ DHRD , 192, // DHRD
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+ ATSR , 192, // ATSR
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+ RHSA , 192, // RHSA
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+ // VTD End
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+
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+ // BIOS Guard Start
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+ CNBS , 8, // CPU SKU number bit shift
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+ // BIOS Guard End
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+
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+ // USB3 Start
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+ XHMD , 8, // copy of setup item PchUsb30Mode
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+ SBV1 , 8, // USB Sideband Deferring GPE Vector (HOST_ALERT#1)
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+ SBV2 , 8, // USB Sideband Deferring GPE Vector (HOST_ALERT#2)
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+ // USB3 End
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+
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+ // HWPM Start
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+ , 2, // HWPM State Enable option from setup
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+ , 1, // Aunomous C-state Enable option from setup
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+ HWPI , 1, // HWP Interrupt
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+ , 4, // Reserved bits
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+ // HWPM End
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+
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+ // PCIe Multi-Seg Start
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+ BB00 , 8, // Bus Base for PC00
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+ BB01 , 8, // Bus Base for PC01
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+ BB02 , 8, // Bus Base for PC02
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+ BB03 , 8, // Bus Base for PC03
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+ BB04 , 8, // Bus Base for PC04
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+ BB05 , 8, // Bus Base for PC05
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+ BB06 , 8, // Bus Base for PC06
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+ BB07 , 8, // Bus Base for PC07
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+ BB08 , 8, // Bus Base for PC08
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+ BB09 , 8, // Bus Base for PC09
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+ BB10 , 8, // Bus Base for PC10
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+ BB11 , 8, // Bus Base for PC11
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+ BB12 , 8, // Bus Base for PC12
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+ BB13 , 8, // Bus Base for PC13
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+ BB14 , 8, // Bus Base for PC14
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+ BB15 , 8, // Bus Base for PC15
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+ BB16 , 8, // Bus Base for PC16
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+ BB17 , 8, // Bus Base for PC17
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+ BB18 , 8, // Bus Base for PC18
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+ BB19 , 8, // Bus Base for PC19
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+ BB20 , 8, // Bus Base for PC20
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+ BB21 , 8, // Bus Base for PC21
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+ BB22 , 8, // Bus Base for PC22
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+ BB23 , 8, // Bus Base for PC23
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+ BB24 , 8, // Bus Base for PC24
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+ BB25 , 8, // Bus Base for PC25
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+ BB26 , 8, // Bus Base for PC26
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+ BB27 , 8, // Bus Base for PC27
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+ BB28 , 8, // Bus Base for PC28
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+ BB29 , 8, // Bus Base for PC29
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+ BB30 , 8, // Bus Base for PC30
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+ BB31 , 8, // Bus Base for PC31
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+ BB32 , 8, // Bus Base for PC32
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+ BB33 , 8, // Bus Base for PC33
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+ BB34 , 8, // Bus Base for PC34
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+ BB35 , 8, // Bus Base for PC35
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+ BB36 , 8, // Bus Base for PC36
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+ BB37 , 8, // Bus Base for PC37
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+ BB38 , 8, // Bus Base for PC38
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+ BB39 , 8, // Bus Base for PC39
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+ BB40 , 8, // Bus Base for PC40
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+ BB41 , 8, // Bus Base for PC41
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+ BB42 , 8, // Bus Base for PC42
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+ BB43 , 8, // Bus Base for PC43
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+ BB44 , 8, // Bus Base for PC44
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+ BB45 , 8, // Bus Base for PC45
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+ BB46 , 8, // Bus Base for PC46
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+ BB47 , 8, // Bus Base for PC47
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+ SGEN , 8, // PCIe_MultiSeg_Support enable/disable
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+ SG00 , 8, // Segment ID for Segment Group 0
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+ SG01 , 8, // Segment ID for Segment Group 1
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+ SG02 , 8, // Segment ID for Segment Group 2
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+ SG03 , 8, // Segment ID for Segment Group 3
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+ SG04 , 8, // Segment ID for Segment Group 4
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+ SG05 , 8, // Segment ID for Segment Group 5
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+ SG06 , 8, // Segment ID for Segment Group 6
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+ SG07 , 8, // Segment ID for Segment Group 7
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+ // PCIe Multi-Seg End
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+
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+ // Performance start
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+ CLOD , 8, // SncAnd2Cluster, i.e. 1=SNC enable and 2 Clusters, 0 otherwise
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+ // Performance End
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+
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+ }
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+
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+
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