GlobalNvsAreaDef.h 3.2 KB

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  1. /** @file
  2. Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
  3. SPDX-License-Identifier: BSD-2-Clause-Patent
  4. **/
  5. #ifndef _EFI_GLOBAL_NVS_AREA_H_
  6. #define _EFI_GLOBAL_NVS_AREA_H_
  7. //
  8. // Global NVS Area definition
  9. //
  10. #pragma pack (1)
  11. typedef struct {
  12. // IOAPIC Start
  13. UINT32 PlatformId;
  14. UINT32 IoApicEnable;
  15. UINT8 ApicIdOverrided :1;
  16. UINT8 RES0 :7;
  17. // IOAPIC End
  18. // Power Management Start
  19. UINT8 Rsvd_Pms_0 :1;
  20. UINT8 CStateEnable :1;
  21. UINT8 C3Enable :1;
  22. UINT8 C6Enable :1;
  23. UINT8 C7Enable :1;
  24. UINT8 MonitorMwaitEnable :1;
  25. UINT8 PStateEnable :1;
  26. UINT8 EmcaEn :1;
  27. UINT8 HWAllEnable :2;
  28. UINT8 KBPresent :1;
  29. UINT8 MousePresent :1;
  30. UINT8 TStateEnable :1;
  31. UINT8 TStateFineGrained: 1;
  32. UINT8 OSCX :1;
  33. UINT8 RESX :1;
  34. // Power Management End
  35. // RAS Start
  36. UINT8 CpuChangeMask;
  37. UINT8 IioChangeMask;
  38. UINT64 IioPresentBitMask;
  39. UINT32 SocketBitMask; //make sure this is at 4byte boundary
  40. UINT32 ProcessorApicIdBase[8];
  41. UINT64 ProcessorBitMask[8];
  42. UINT16 MemoryBoardBitMask;
  43. UINT16 MemoryBoardChgEvent;
  44. UINT32 MmCfg;
  45. UINT32 TsegSize;
  46. UINT64 MemoryBoardBase[8];
  47. UINT64 MemoryBoardRange[8];
  48. UINT32 SmiRequestParam[4];
  49. UINT32 SciRequestParam[4];
  50. UINT64 MigrationActionRegionAddress;
  51. UINT8 Cpu0Uuid[16];
  52. UINT8 Cpu1Uuid[16];
  53. UINT8 Cpu2Uuid[16];
  54. UINT8 Cpu3Uuid[16];
  55. UINT8 Cpu4Uuid[16];
  56. UINT8 Cpu5Uuid[16];
  57. UINT8 Cpu6Uuid[16];
  58. UINT8 Cpu7Uuid[16];
  59. UINT8 CpuSpareMask;
  60. UINT8 Mem0Uuid[16];
  61. UINT8 Mem1Uuid[16];
  62. UINT8 Mem2Uuid[16];
  63. UINT8 Mem3Uuid[16];
  64. UINT8 Mem4Uuid[16];
  65. UINT8 Mem5Uuid[16];
  66. UINT8 Mem6Uuid[16];
  67. UINT8 Mem7Uuid[16];
  68. UINT8 Mem8Uuid[16];
  69. UINT8 Mem9Uuid[16];
  70. UINT8 Mem10Uuid[16];
  71. UINT8 Mem11Uuid[16];
  72. UINT8 Mem12Uuid[16];
  73. UINT8 Mem13Uuid[16];
  74. UINT8 Mem14Uuid[16];
  75. UINT8 Mem15Uuid[16];
  76. UINT16 MemSpareMask;
  77. UINT64 EmcaL1DirAddr;
  78. UINT32 ProcessorId;
  79. UINT8 PcieAcpiHotPlugEnable;
  80. // RAS End
  81. // VTD Start
  82. UINT64 DrhdAddr[3];
  83. UINT64 AtsrAddr[3];
  84. UINT64 RhsaAddr[3];
  85. // VTD End
  86. // BIOS Guard Start
  87. UINT8 CpuSkuNumOfBitShift;
  88. // BIOS Guard End
  89. // USB3 Start
  90. UINT8 XhciMode;
  91. UINT8 HostAlertVector1;
  92. UINT8 HostAlertVector2;
  93. // USB3 End
  94. // HWPM Start
  95. UINT8 HWPMEnable:2; //HWPM
  96. UINT8 AutoCstate:1; //HWPM
  97. UINT8 HwpInterrupt:1; //HWP Interrupt
  98. UINT8 RES1:4; //reserved bits
  99. // HWPM End
  100. // PCIe Multi-Seg Start
  101. // for 8S support needs max 32 IIO IOxAPIC being enabled!
  102. UINT8 BusBase[48]; // MAX_SOCKET * MAX_IIO_STACK. Note: hardcode due to ASL constraint.
  103. UINT8 PCIe_MultiSeg_Support; // Enable /Disable switch
  104. // for 8S support needs matching to MAX_SOCKET!
  105. UINT8 PcieSegNum[8]; // Segment number array. Must match MAX_SOCKET. Note: hardcode due to ASL constraint.
  106. // PCIe Multi-seg end
  107. // Performance Start
  108. UINT8 SncAnd2Cluster; //1=SncEn and NumCluster=2, otherwise 0
  109. // Performance End
  110. } BIOS_ACPI_PARAM;
  111. #pragma pack ()
  112. #endif