PchRcVariable.h 10 KB

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  1. /** @file
  2. Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
  3. SPDX-License-Identifier: BSD-2-Clause-Patent
  4. **/
  5. #ifndef __PCH_RC_CONFIG_DATA_H__
  6. #define __PCH_RC_CONFIG_DATA_H__
  7. #include <PchLimits.h>
  8. #define HDAUDIO_FEATURES 3
  9. #define HDAUDIO_PP_MODULES 2
  10. /// sSATA max ports for Wellsburg
  11. #define PCH_SSATA_MAX_PORTS 6
  12. #pragma pack(1)
  13. typedef struct {
  14. UINT8 BiosGuard;
  15. UINT8 Dwr_Enable;
  16. UINT8 Dwr_Stall;
  17. UINT8 Dwr_BmcRootPort;
  18. UINT8 DwrEn_PMCGBL;
  19. UINT8 DwrEn_CPUTHRM;
  20. UINT8 DwrEn_PCHTHRM;
  21. UINT8 DwrEn_PBO;
  22. UINT8 DwrEn_MEPBO;
  23. UINT8 DwrEn_MEWDT;
  24. UINT8 DwrEn_MEGBL;
  25. UINT8 DwrEn_CTWDT;
  26. UINT8 DwrEn_PMCWDT;
  27. UINT8 DwrEn_ME_UERR;
  28. UINT8 DwrEn_SYSPWR;
  29. UINT8 DwrEn_OCWDT;
  30. UINT8 DwrEn_IEPBO;
  31. UINT8 DwrEn_IEWDT;
  32. UINT8 DwrEn_IEGBLN;
  33. UINT8 DwrEn_IE_UERRN;
  34. UINT8 DwrEn_ACRU_ERR_2H_EN;
  35. UINT8 DwrPmcEn_HOST_RESET_TIMEOUT;
  36. UINT8 DwrPmcEn_SX_ENTRY_TIMEOUT;
  37. UINT8 DwrPmcEn_HOST_RST_PROM;
  38. UINT8 DwrPmcEn_HSMB_MSG;
  39. UINT8 DwrPmcEn_IE_MTP_TIMEOUT;
  40. UINT8 DwrPmcEn_MTP_TIMEOUT;
  41. UINT8 DwrPmcEn_ESPI_ERROR_DETECT;
  42. UINT8 Dwr_MeResetPrepDone;
  43. UINT8 Dwr_IeResetPrepDone;
  44. //
  45. // PCH_DEVICE_ENABLES
  46. //
  47. UINT8 BoardCapability;
  48. UINT8 DeepSxMode;
  49. UINT8 Gp27WakeFromDeepSx;
  50. UINT8 GbeRegionInvalid;
  51. UINT8 LomLanSupported;
  52. UINT8 PchWakeOnLan;
  53. UINT8 PchSlpLanLowDc;
  54. UINT8 PchSmbus;
  55. UINT8 PchPciClockRun;
  56. UINT8 PchDisplay;
  57. UINT8 PchCrid;
  58. UINT8 PchRtcLock;
  59. UINT8 PchBiosLock;
  60. UINT8 PchAllUnLock;
  61. UINT8 PchThermalUnlock;
  62. UINT8 PchSerm;
  63. UINT8 PchGbeFlashLockDown;
  64. UINT8 PchSmmBwp;
  65. UINT8 Hpet;
  66. UINT8 PchPort80Route;
  67. UINT8 EnableClockSpreadSpec;
  68. UINT8 IchPort80Route;
  69. UINT8 PchSirqMode;
  70. //
  71. // Usb Config
  72. //
  73. UINT8 PchUsbManualMode;
  74. UINT8 PchGpioLockDown;
  75. UINT8 RouteUsb2PinsToWhichHc;
  76. UINT8 RouteUsb2Pin0;
  77. UINT8 RouteUsb2Pin1;
  78. UINT8 RouteUsb2Pin2;
  79. UINT8 RouteUsb2Pin3;
  80. UINT8 RouteUsb2Pin4;
  81. UINT8 RouteUsb2Pin5;
  82. UINT8 RouteUsb2Pin6;
  83. UINT8 RouteUsb2Pin7;
  84. UINT8 RouteUsb2Pin8;
  85. UINT8 RouteUsb2Pin9;
  86. UINT8 RouteUsb2Pin10;
  87. UINT8 RouteUsb2Pin11;
  88. UINT8 RouteUsb2Pin12;
  89. UINT8 RouteUsb2Pin13;
  90. UINT8 Usb3PinsTermination;
  91. UINT8 EnableUsb3Pin[10];
  92. UINT8 PchUsbHsPort[16];
  93. UINT8 PchUsbSsPort[10];
  94. UINT8 PchUsbPortDisable;
  95. UINT8 UsbSensorHub;
  96. UINT8 UsbSsicSupport[2];
  97. UINT8 XhciDisMSICapability;
  98. UINT8 PchUsbPerPortCtl;
  99. UINT8 PchUsb30Port[6];
  100. UINT8 UsbPrecondition;
  101. UINT8 XhciIdleL1;
  102. UINT8 Btcg;
  103. UINT8 PchUsbDegradeBar;
  104. //
  105. // XHCI OC Map
  106. //
  107. UINT8 XhciOcMapEnabled;
  108. //
  109. // xDCI Config
  110. //
  111. UINT8 PchXdciSupport;
  112. //
  113. // Sata CONFIG
  114. //
  115. UINT8 PchSata;
  116. //
  117. // Sata Interface Mode
  118. // 0 - IDE 1 - RAID 2 - AHCI
  119. //
  120. UINT8 SataInterfaceMode;
  121. UINT8 SataPort[PCH_MAX_SATA_PORTS];
  122. UINT8 SataHotPlug[PCH_MAX_SATA_PORTS];
  123. UINT8 SataMechanicalSw[PCH_MAX_SATA_PORTS];
  124. UINT8 SataSpinUp[PCH_MAX_SATA_PORTS];
  125. UINT8 SataExternal[PCH_MAX_SATA_PORTS];
  126. UINT8 SataType[PCH_MAX_SATA_PORTS];
  127. UINT8 SataRaidR0;
  128. UINT8 SataRaidR1;
  129. UINT8 SataRaidR10;
  130. UINT8 SataRaidR5;
  131. UINT8 SataRaidIrrt;
  132. UINT8 SataRaidOub;
  133. UINT8 SataHddlk;
  134. UINT8 SataLedl;
  135. UINT8 SataRaidIooe;
  136. UINT8 SataRaidSrt;
  137. UINT8 SataRaidLoadEfiDriver;
  138. UINT8 SataRaidOromDelay;
  139. UINT8 SataAlternateId;
  140. UINT8 SataSalp;
  141. UINT8 SataTestMode;
  142. UINT8 PxDevSlp[PCH_MAX_SATA_PORTS];
  143. UINT8 EnableDitoConfig[PCH_MAX_SATA_PORTS];
  144. UINT16 DitoVal[PCH_MAX_SATA_PORTS];
  145. UINT8 DmVal[PCH_MAX_SATA_PORTS];
  146. UINT8 SataTopology[PCH_MAX_SATA_PORTS];
  147. //
  148. // sSata CONFIG
  149. //
  150. UINT8 PchsSata;
  151. //
  152. // Sata Interface Mode
  153. // 0 - IDE 1 - RAID 2 - AHCI
  154. //
  155. UINT8 sSataInterfaceMode;
  156. UINT8 sSataPort[PCH_SSATA_MAX_PORTS];
  157. UINT8 sSataHotPlug[PCH_SSATA_MAX_PORTS];
  158. UINT8 sSataSpinUp[PCH_SSATA_MAX_PORTS];
  159. UINT8 sSataExternal[PCH_SSATA_MAX_PORTS];
  160. UINT8 sPxDevSlp[PCH_SSATA_MAX_PORTS];
  161. UINT8 sSataType[PCH_SSATA_MAX_PORTS];
  162. UINT8 sSataRaidR0;
  163. UINT8 sSataRaidR1;
  164. UINT8 sSataRaidR10;
  165. UINT8 sSataRaidR5;
  166. UINT8 sSataRaidIrrt;
  167. UINT8 sSataRaidOub;
  168. UINT8 sSataHddlk;
  169. UINT8 sSataLedl;
  170. UINT8 sSataRaidIooe;
  171. UINT8 sSataRaidSrt;
  172. UINT8 sSataRaidLoadEfiDriver;
  173. UINT8 sSataRaidOromDelay;
  174. UINT8 sSataAlternateId;
  175. UINT8 sSataSalp;
  176. UINT8 sSataTestMode;
  177. UINT8 sEnableDitoConfig[PCH_SSATA_MAX_PORTS];
  178. UINT8 sDmVal[PCH_SSATA_MAX_PORTS];
  179. UINT8 sDitoVal[PCH_SSATA_MAX_PORTS];
  180. UINT8 sSataTopology[PCH_SSATA_MAX_PORTS];
  181. //PCH THERMAL SENSOR
  182. UINT8 ThermalDeviceEnable;
  183. UINT8 PchCrossThrottling;
  184. UINT8 PchDmiExtSync;
  185. UINT8 PcieDmiExtSync;
  186. // AcpiDebug Setup Options
  187. UINT8 PciDelayOptimizationEcr;
  188. UINT8 PchPcieGlobalAspm;
  189. UINT8 PcieDmiStopAndScreamEnable;
  190. UINT8 DmiLinkDownHangBypass;
  191. UINT8 XTpmLen;
  192. UINT8 PcieRootPort8xhDecode;
  193. UINT8 Pcie8xhDecodePortIndex;
  194. UINT8 PcieRootPortPeerMemoryWriteEnable;
  195. UINT8 PcieComplianceTestMode;
  196. UINT8 PcieRootPortSBDE;
  197. UINT8 PcieSBDEPort;
  198. UINT8 RstPcieStorageRemap[PCH_MAX_RST_PCIE_STORAGE_CR];
  199. UINT8 RstPcieStorageRemapPort[PCH_MAX_RST_PCIE_STORAGE_CR];
  200. UINT8 PcieRootPortFunctionSwapping;
  201. UINT8 PcieRootPortEn[PCH_MAX_PCIE_ROOT_PORTS];
  202. UINT8 PcieRootPortAspm[PCH_MAX_PCIE_ROOT_PORTS];
  203. UINT8 PcieRootPortURE[PCH_MAX_PCIE_ROOT_PORTS];
  204. UINT8 PcieRootPortFEE[PCH_MAX_PCIE_ROOT_PORTS];
  205. UINT8 PcieRootPortNFE[PCH_MAX_PCIE_ROOT_PORTS];
  206. UINT8 PcieRootPortCEE[PCH_MAX_PCIE_ROOT_PORTS];
  207. UINT8 PcieRootPortMSIE[PCH_MAX_PCIE_ROOT_PORTS];
  208. UINT8 PcieRootPortMaxPayLoadSize[PCH_MAX_PCIE_ROOT_PORTS];
  209. UINT8 PcieRootPortAER[PCH_MAX_PCIE_ROOT_PORTS];
  210. UINT8 PcieTopology[PCH_MAX_PCIE_ROOT_PORTS];
  211. UINT8 PcieLaneCm[PCH_MAX_PCIE_ROOT_PORTS];
  212. UINT8 PcieLaneCp[PCH_MAX_PCIE_ROOT_PORTS];
  213. UINT8 PcieSwEqOverride;
  214. UINT8 PcieSwEqCoeffCm[PCH_PCIE_SWEQ_COEFFS_MAX];
  215. UINT8 PcieSwEqCoeffCp[PCH_PCIE_SWEQ_COEFFS_MAX];
  216. UINT8 PchPcieUX8MaxPayloadSize;
  217. UINT8 PchPcieUX16MaxPayloadSize;
  218. UINT8 PcieRootPortCompletionTimeout[PCH_MAX_PCIE_ROOT_PORTS];
  219. UINT8 PcieClockGatingDisabled;
  220. UINT8 PcieUsbGlitchWa;
  221. UINT8 PcieRootPortPIE[PCH_MAX_PCIE_ROOT_PORTS];
  222. UINT8 PcieRootPortACS[PCH_MAX_PCIE_ROOT_PORTS];
  223. UINT8 PcieRootPortEqPh3Method[PCH_MAX_PCIE_ROOT_PORTS];
  224. UINT8 PcieRootPortMaxReadRequestSize;
  225. UINT8 PcieRootPortSFE[PCH_MAX_PCIE_ROOT_PORTS];
  226. UINT8 PcieRootPortSNE[PCH_MAX_PCIE_ROOT_PORTS];
  227. UINT8 PcieRootPortSCE[PCH_MAX_PCIE_ROOT_PORTS];
  228. UINT8 PcieRootPortPMCE[PCH_MAX_PCIE_ROOT_PORTS];
  229. UINT8 PcieRootPortHPE[PCH_MAX_PCIE_ROOT_PORTS];
  230. UINT8 PcieRootPortSpeed[PCH_MAX_PCIE_ROOT_PORTS];
  231. UINT8 PcieRootPortTHS[PCH_MAX_PCIE_ROOT_PORTS];
  232. //
  233. // PCI Bridge Resources
  234. //
  235. UINT8 PcieRootPortL1SubStates[PCH_MAX_PCIE_ROOT_PORTS];
  236. UINT8 MemoryThermalManagement;
  237. UINT8 ExttsViaTsOnBoard;
  238. UINT8 ExttsViaTsOnDimm;
  239. UINT8 FixupPlatformSpecificSoftstraps;
  240. //
  241. // SMBUS Configuration
  242. //
  243. UINT8 TestSmbusSpdWriteDisable;
  244. //
  245. // HD-Audio Configuration
  246. //
  247. UINT8 PchHdAudio;
  248. UINT8 PchHdAudioDsp;
  249. UINT8 PchHdAudioPme;
  250. UINT8 PchHdAudioIoBufferOwnership;
  251. UINT8 PchHdAudioIoBufferVoltage;
  252. UINT8 PchHdAudioCodecSelect;
  253. UINT8 PchHdAudioFeature[HDAUDIO_FEATURES];
  254. UINT8 PchHdAudioPostProcessingMod[HDAUDIO_PP_MODULES];
  255. UINT8 RtoHdaVcType;
  256. //
  257. // DMI Configuration
  258. //
  259. UINT8 TestDmiAspmCtrl;
  260. //
  261. //
  262. // PCIe LTR Configuration
  263. //
  264. UINT8 PchPcieLtrEnable[PCH_MAX_PCIE_ROOT_PORTS];
  265. UINT8 PchPcieLtrConfigLock[PCH_MAX_PCIE_ROOT_PORTS];
  266. UINT8 PchPcieSnoopLatencyOverrideMode[PCH_MAX_PCIE_ROOT_PORTS];
  267. UINT8 PchPcieSnoopLatencyOverrideMultiplier[PCH_MAX_PCIE_ROOT_PORTS];
  268. UINT8 PchPcieNonSnoopLatencyOverrideMode[PCH_MAX_PCIE_ROOT_PORTS];
  269. UINT8 PchPcieNonSnoopLatencyOverrideMultiplier[PCH_MAX_PCIE_ROOT_PORTS];
  270. UINT16 PchPcieSnoopLatencyOverrideValue[PCH_MAX_PCIE_ROOT_PORTS];
  271. UINT16 PchPcieNonSnoopLatencyOverrideValue[PCH_MAX_PCIE_ROOT_PORTS];
  272. UINT8 PchPcieForceLtrOverride[PCH_MAX_PCIE_ROOT_PORTS];
  273. UINT8 PchSataLtrOverride;
  274. UINT8 PchSataLtrEnable;
  275. UINT16 PchSataSnoopLatencyOverrideValue;
  276. UINT8 PchSataSnoopLatencyOverrideMultiplier;
  277. UINT8 PchSataLtrConfigLock;
  278. UINT8 PchSSataLtrOverride;
  279. UINT16 PchSSataSnoopLatencyOverrideValue;
  280. UINT8 PchSSataSnoopLatencyOverrideMultiplier;
  281. UINT8 PchSSataLtrEnable;
  282. UINT8 PchSSataLtrConfigLock;
  283. UINT8 PchPcieUX16CompletionTimeout;
  284. UINT8 PchPcieUX8CompletionTimeout;
  285. //
  286. // Interrupt Configuration
  287. //
  288. UINT8 PchIoApic24119Entries;
  289. //
  290. // DPTF SETUP items begin
  291. //
  292. UINT8 EnableDptf;
  293. UINT8 EnablePchDevice;
  294. //
  295. // CPU
  296. //
  297. UINT8 DebugDciEnable;
  298. UINT8 DebugInterfaceEnable;
  299. //
  300. // Miscellaneous options
  301. //
  302. UINT8 OsDebugPort;
  303. UINT8 SlpLanLowDc;
  304. UINT8 PchLanK1Off;
  305. UINT8 PchWakeOnWlan;
  306. UINT8 PchWakeOnWlanDeepSx;
  307. UINT8 StateAfterG3;
  308. UINT8 PciePllSsc;
  309. UINT8 FirmwareConfiguration;
  310. UINT8 PchDciEn;
  311. UINT8 PchDciAutoDetect;
  312. // Acpi.sd
  313. UINT8 CSNotifyEC;
  314. UINT8 EcLowPowerMode;
  315. //
  316. // TraceHub Setup Options
  317. //
  318. UINT8 TraceHubEnableMode;
  319. UINT8 MemRegion0BufferSize;
  320. UINT8 MemRegion1BufferSize;
  321. //
  322. // PCH P2SB hide and lock options
  323. //
  324. UINT8 PchP2sbDevReveal;
  325. UINT8 PchP2sbUnlock;
  326. //
  327. // PCH SPI hide and lock options
  328. //
  329. UINT8 FlashLockDown;
  330. //
  331. // PCH PMC option
  332. //
  333. UINT8 PmcReadDisable;
  334. //
  335. // ADR Configuration
  336. //
  337. UINT8 PchAdrEn;
  338. UINT8 AdrTimerEn;
  339. UINT8 AdrTimerVal;
  340. UINT8 AdrMultiplierVal;
  341. UINT8 AdrGpioSel;
  342. UINT8 AdrHostPartitionReset;
  343. //
  344. // Audio DSP Configuration
  345. //
  346. UINT8 PchAudioDsp;
  347. UINT8 PchAudioDspD3PowerGating;
  348. UINT8 PchAudioDspAcpiMode;
  349. UINT8 PchAudioDspBluetooth;
  350. UINT8 PchAudioDspAcpiInterruptMode;
  351. //
  352. // Miscellaneous options
  353. //
  354. UINT8 PchEvaMrom0HookEnable;
  355. UINT8 PchEvaMrom1HookEnable;
  356. UINT8 TestMctpBroadcastCycle;
  357. UINT8 PchEvaLockDown;
  358. UINT8 PchTraceHubHide;
  359. } PCH_RC_CONFIGURATION;
  360. #pragma pack()
  361. #endif