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sd2snes
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sd2snes
/
verilog
Maximilian Rehkopf
39b07df47e
Correct LoROM SRAM mapping for smaller ROMs
il y a 11 ans
..
sd2snes
39b07df47e
Correct LoROM SRAM mapping for smaller ROMs
il y a 11 ans
sd2snes_cx4
e92ad06f38
FPGA/Cx4: slow down bus timing
il y a 11 ans
sd2snes_test
7109f9e030
FPGA: add SD clock pullup to test configuration
il y a 12 ans
sd2sneslite
968c347986
FPGA/SPI: detect end of byte via MSB toggle instead of constant compare of async input
il y a 12 ans