Maximilian Rehkopf 7109f9e030 FPGA: add SD clock pullup to test configuration 12 years ago
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ipcore_dir f5caf21fac FPGA: slightly tighten timing constraints 12 years ago
address.v dc01edfe9a FPGA: add test suite 12 years ago
clk_test.v dc01edfe9a FPGA: add test suite 12 years ago
dac.v dc01edfe9a FPGA: add test suite 12 years ago
dcm.v dc01edfe9a FPGA: add test suite 12 years ago
main.ucf 7109f9e030 FPGA: add SD clock pullup to test configuration 12 years ago
main.v dc01edfe9a FPGA: add test suite 12 years ago
mcu_cmd.v dc01edfe9a FPGA: add test suite 12 years ago
sd2snes_test.xise f5caf21fac FPGA: slightly tighten timing constraints 12 years ago
sd_dma.v dc01edfe9a FPGA: add test suite 12 years ago
spi.v dc01edfe9a FPGA: add test suite 12 years ago