Maximilian Rehkopf 9fbe61bad1 FPGA: Use internal clock instead of SNES master clock for $213F RMW timing 12 years ago
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sd2snes 9fbe61bad1 FPGA: Use internal clock instead of SNES master clock for $213F RMW timing 12 years ago
sd2snes_cx4 9fbe61bad1 FPGA: Use internal clock instead of SNES master clock for $213F RMW timing 12 years ago
sd2snes_test 7109f9e030 FPGA: add SD clock pullup to test configuration 12 years ago
sd2sneslite 968c347986 FPGA/SPI: detect end of byte via MSB toggle instead of constant compare of async input 12 years ago