Maximilian Rehkopf 6b3a7eb4ae FPGA/SRTC: buffer register/address input 12 years ago
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sd2snes 6b3a7eb4ae FPGA/SRTC: buffer register/address input 12 years ago
sd2snes_cx4 effa2a6972 FPGA/SDDMA: fix clock glitch, adjust RAM write timings 12 years ago
sd2snes_test 7109f9e030 FPGA: add SD clock pullup to test configuration 12 years ago
sd2sneslite 968c347986 FPGA/SPI: detect end of byte via MSB toggle instead of constant compare of async input 12 years ago