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@@ -33,7 +33,7 @@
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#endif
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#if !defined(CONFIG_SPL) && !defined(CONFIG_SYS_RAMBOOT) && \
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- !defined(CONFIG_SECURE_BOOT) && !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
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+ !defined(CONFIG_NXP_ESBC) && !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
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#define NOR_BOOT
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#endif
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@@ -123,7 +123,7 @@ _start_e500:
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#endif
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-#if defined(CONFIG_SECURE_BOOT) && defined(CONFIG_E500MC) && \
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+#if defined(CONFIG_NXP_ESBC) && defined(CONFIG_E500MC) && \
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!defined(CONFIG_E6500)
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/* ISBC uses L2 as stack.
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* Disable L2 cache here so that u-boot can enable it later
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@@ -467,7 +467,7 @@ nexti: mflr r1 /* R1 = our PC */
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blt 1b
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#if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB) && !defined(MINIMAL_SPL) && \
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- !defined(CONFIG_SECURE_BOOT)
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+ !defined(CONFIG_NXP_ESBC)
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/*
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* TLB entry for debuggging in AS1
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* Create temporary TLB entry in AS0 to handle debug exception
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@@ -1065,7 +1065,7 @@ create_init_ram_area:
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0xffc00000, MAS3_SX|MAS3_SW|MAS3_SR, \
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0, r6
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-#elif !defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SECURE_BOOT)
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+#elif !defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_NXP_ESBC)
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/* create a temp mapping in AS = 1 for Flash mapping
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* created by PBL for ISBC code
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*/
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@@ -1080,7 +1080,7 @@ create_init_ram_area:
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* and for targets with CONFIG_SPL like T1, T2, T4, only for
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* u-boot-spl i.e. CONFIG_SPL_BUILD
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*/
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-#elif defined(CONFIG_RAMBOOT_PBL) && defined(CONFIG_SECURE_BOOT) && \
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+#elif defined(CONFIG_RAMBOOT_PBL) && defined(CONFIG_NXP_ESBC) && \
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(!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD))
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/* create a temp mapping in AS = 1 for mapping CONFIG_SYS_MONITOR_BASE
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* to L3 Address configured by PBL for ISBC code
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