tlb.c 4.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2013 Freescale Semiconductor, Inc.
  4. */
  5. #include <common.h>
  6. #include <asm/mmu.h>
  7. struct fsl_e_tlb_entry tlb_table[] = {
  8. /* TLB 0 - for temp stack in cache */
  9. SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
  10. CONFIG_SYS_INIT_RAM_ADDR_PHYS,
  11. MAS3_SX|MAS3_SW|MAS3_SR, 0,
  12. 0, 0, BOOKE_PAGESZ_4K, 0),
  13. SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
  14. CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
  15. MAS3_SX|MAS3_SW|MAS3_SR, 0,
  16. 0, 0, BOOKE_PAGESZ_4K, 0),
  17. SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
  18. CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
  19. MAS3_SX|MAS3_SW|MAS3_SR, 0,
  20. 0, 0, BOOKE_PAGESZ_4K, 0),
  21. SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
  22. CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
  23. MAS3_SX|MAS3_SW|MAS3_SR, 0,
  24. 0, 0, BOOKE_PAGESZ_4K, 0),
  25. /* TLB 1 */
  26. /* *I*** - Covers boot page */
  27. #if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR) && \
  28. !defined(CONFIG_NXP_ESBC)
  29. /*
  30. * *I*G - L3SRAM. When L3 is used as 256K SRAM, the address of the
  31. * SRAM is at 0xfffc0000, it covered the 0xfffff000.
  32. */
  33. SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
  34. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  35. 0, 0, BOOKE_PAGESZ_256K, 1),
  36. #elif defined(CONFIG_NXP_ESBC) && defined(CONFIG_SPL_BUILD)
  37. /*
  38. * *I*G - L3SRAM. When L3 is used as 256K SRAM, in case of Secure Boot
  39. * the physical address of the SRAM is at 0xbffc0000,
  40. * and virtual address is 0xfffc0000
  41. */
  42. SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_VADDR,
  43. CONFIG_SYS_INIT_L3_ADDR,
  44. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  45. 0, 0, BOOKE_PAGESZ_256K, 1),
  46. #else
  47. SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
  48. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  49. 0, 0, BOOKE_PAGESZ_4K, 1),
  50. #endif
  51. /* *I*G* - CCSRBAR */
  52. SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
  53. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  54. 0, 1, BOOKE_PAGESZ_16M, 1),
  55. /* *I*G* - Flash, localbus */
  56. /* This will be changed to *I*G* after relocation to RAM. */
  57. SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
  58. MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
  59. 0, 2, BOOKE_PAGESZ_256M, 1),
  60. #ifndef CONFIG_SPL_BUILD
  61. /* *I*G* - PCI */
  62. SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
  63. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  64. 0, 3, BOOKE_PAGESZ_1G, 1),
  65. /* *I*G* - PCI I/O */
  66. SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
  67. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  68. 0, 4, BOOKE_PAGESZ_256K, 1),
  69. /* Bman/Qman */
  70. #ifdef CONFIG_SYS_BMAN_MEM_PHYS
  71. SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS,
  72. MAS3_SX|MAS3_SW|MAS3_SR, 0,
  73. 0, 5, BOOKE_PAGESZ_16M, 1),
  74. SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000,
  75. CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000,
  76. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  77. 0, 6, BOOKE_PAGESZ_16M, 1),
  78. #endif
  79. #ifdef CONFIG_SYS_QMAN_MEM_PHYS
  80. SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS,
  81. MAS3_SX|MAS3_SW|MAS3_SR, 0,
  82. 0, 7, BOOKE_PAGESZ_16M, 1),
  83. SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000,
  84. CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000,
  85. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  86. 0, 8, BOOKE_PAGESZ_16M, 1),
  87. #endif
  88. #endif
  89. #ifdef CONFIG_SYS_DCSRBAR_PHYS
  90. SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
  91. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  92. 0, 9, BOOKE_PAGESZ_4M, 1),
  93. #endif
  94. #ifdef CONFIG_SYS_NAND_BASE
  95. /*
  96. * *I*G - NAND
  97. * entry 14 and 15 has been used hard coded, they will be disabled
  98. * in cpu_init_f, so we use entry 16 for nand.
  99. */
  100. SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
  101. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  102. 0, 10, BOOKE_PAGESZ_64K, 1),
  103. #endif
  104. #ifdef CONFIG_SYS_CPLD_BASE
  105. SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS,
  106. MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  107. 0, 11, BOOKE_PAGESZ_256K, 1),
  108. #endif
  109. #if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD)
  110. SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
  111. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
  112. 0, 12, BOOKE_PAGESZ_1G, 1),
  113. SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
  114. CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
  115. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
  116. 0, 13, BOOKE_PAGESZ_1G, 1)
  117. #endif
  118. };
  119. int num_tlb_entries = ARRAY_SIZE(tlb_table);