tlb.c 5.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2008-2011 Freescale Semiconductor, Inc.
  4. *
  5. * (C) Copyright 2000
  6. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  7. */
  8. #include <common.h>
  9. #include <asm/mmu.h>
  10. struct fsl_e_tlb_entry tlb_table[] = {
  11. /* TLB 0 - for temp stack in cache */
  12. SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
  13. CONFIG_SYS_INIT_RAM_ADDR_PHYS,
  14. MAS3_SW|MAS3_SR, 0,
  15. 0, 0, BOOKE_PAGESZ_4K, 0),
  16. SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
  17. CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
  18. MAS3_SW|MAS3_SR, 0,
  19. 0, 0, BOOKE_PAGESZ_4K, 0),
  20. SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
  21. CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
  22. MAS3_SW|MAS3_SR, 0,
  23. 0, 0, BOOKE_PAGESZ_4K, 0),
  24. SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
  25. CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
  26. MAS3_SW|MAS3_SR, 0,
  27. 0, 0, BOOKE_PAGESZ_4K, 0),
  28. #ifdef CPLD_BASE
  29. SET_TLB_ENTRY(0, CPLD_BASE, CPLD_BASE_PHYS,
  30. MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  31. 0, 0, BOOKE_PAGESZ_4K, 0),
  32. #endif
  33. #ifdef PIXIS_BASE
  34. SET_TLB_ENTRY(0, PIXIS_BASE, PIXIS_BASE_PHYS,
  35. MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  36. 0, 0, BOOKE_PAGESZ_4K, 0),
  37. #endif
  38. /* TLB 1 */
  39. /* *I*** - Covers boot page */
  40. #if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR)
  41. #if !defined(CONFIG_NXP_ESBC)
  42. /*
  43. * *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the
  44. * SRAM is at 0xfff00000, it covered the 0xfffff000.
  45. */
  46. SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
  47. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  48. 0, 0, BOOKE_PAGESZ_1M, 1),
  49. #else
  50. /*
  51. * *I*G - L3SRAM. When L3 is used as 1M SRAM, in case of Secure Boot
  52. * the physical address of the SRAM is at CONFIG_SYS_INIT_L3_ADDR,
  53. * and virtual address is CONFIG_SYS_MONITOR_BASE
  54. */
  55. SET_TLB_ENTRY(1, CONFIG_SYS_MONITOR_BASE & 0xfff00000,
  56. CONFIG_SYS_INIT_L3_ADDR & 0xfff00000,
  57. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  58. 0, 0, BOOKE_PAGESZ_1M, 1),
  59. #endif
  60. #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
  61. /*
  62. * SRIO_PCIE_BOOT-SLAVE. When slave boot, the address of the
  63. * space is at 0xfff00000, it covered the 0xfffff000.
  64. */
  65. SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR,
  66. CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS,
  67. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G,
  68. 0, 0, BOOKE_PAGESZ_1M, 1),
  69. #else
  70. SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
  71. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  72. 0, 0, BOOKE_PAGESZ_4K, 1),
  73. #endif
  74. /* *I*G* - CCSRBAR */
  75. SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
  76. MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  77. 0, 1, BOOKE_PAGESZ_16M, 1),
  78. /* *I*G* - Flash, localbus */
  79. /* This will be changed to *I*G* after relocation to RAM. */
  80. SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
  81. MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
  82. 0, 2, BOOKE_PAGESZ_256M, 1),
  83. /* *I*G* - PCI */
  84. SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
  85. MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  86. 0, 3, BOOKE_PAGESZ_1G, 1),
  87. /* *I*G* - PCI */
  88. SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x40000000,
  89. CONFIG_SYS_PCIE1_MEM_PHYS + 0x40000000,
  90. MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  91. 0, 4, BOOKE_PAGESZ_256M, 1),
  92. SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x50000000,
  93. CONFIG_SYS_PCIE1_MEM_PHYS + 0x50000000,
  94. MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  95. 0, 5, BOOKE_PAGESZ_256M, 1),
  96. /* *I*G* - PCI I/O */
  97. SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
  98. MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  99. 0, 6, BOOKE_PAGESZ_256K, 1),
  100. /* Bman/Qman */
  101. #ifdef CONFIG_SYS_BMAN_MEM_PHYS
  102. SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS,
  103. MAS3_SW|MAS3_SR, 0,
  104. 0, 9, BOOKE_PAGESZ_1M, 1),
  105. SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x00100000,
  106. CONFIG_SYS_BMAN_MEM_PHYS + 0x00100000,
  107. MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  108. 0, 10, BOOKE_PAGESZ_1M, 1),
  109. #endif
  110. #ifdef CONFIG_SYS_QMAN_MEM_PHYS
  111. SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS,
  112. MAS3_SW|MAS3_SR, 0,
  113. 0, 11, BOOKE_PAGESZ_1M, 1),
  114. SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x00100000,
  115. CONFIG_SYS_QMAN_MEM_PHYS + 0x00100000,
  116. MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  117. 0, 12, BOOKE_PAGESZ_1M, 1),
  118. #endif
  119. #ifdef CONFIG_SYS_DCSRBAR_PHYS
  120. SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
  121. MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  122. 0, 13, BOOKE_PAGESZ_4M, 1),
  123. #endif
  124. #ifdef CONFIG_SYS_NAND_BASE
  125. /*
  126. * *I*G - NAND
  127. * entry 14 and 15 has been used hard coded, they will be disabled
  128. * in cpu_init_f, so we use entry 16 for nand.
  129. */
  130. SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
  131. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  132. 0, 16, BOOKE_PAGESZ_1M, 1),
  133. #endif
  134. #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
  135. /*
  136. * SRIO_PCIE_BOOT-SLAVE. 1M space from 0xffe00000 for
  137. * fetching ucode and ENV from master
  138. */
  139. SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR,
  140. CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS,
  141. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G,
  142. 0, 17, BOOKE_PAGESZ_1M, 1),
  143. #endif
  144. };
  145. int num_tlb_entries = ARRAY_SIZE(tlb_table);