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@@ -223,6 +223,51 @@ static int zynqmp_load(xilinx_desc *desc, const void *buf, size_t bsize,
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return ret;
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}
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+#if defined(CONFIG_CMD_FPGA_LOAD_SECURE) && !defined(CONFIG_SPL_BUILD)
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+static int zynqmp_loads(xilinx_desc *desc, const void *buf, size_t bsize,
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+ struct fpga_secure_info *fpga_sec_info)
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+{
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+ int ret;
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+ u32 buf_lo, buf_hi;
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+ u32 ret_payload[PAYLOAD_ARG_CNT];
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+ u8 flag = 0;
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+
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+ flush_dcache_range((ulong)buf, (ulong)buf +
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+ ALIGN(bsize, CONFIG_SYS_CACHELINE_SIZE));
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+
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+ if (!fpga_sec_info->encflag)
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+ flag |= BIT(ZYNQMP_FPGA_BIT_ENC_DEV_KEY);
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+
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+ if (fpga_sec_info->userkey_addr &&
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+ fpga_sec_info->encflag == FPGA_ENC_USR_KEY) {
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+ flush_dcache_range((ulong)fpga_sec_info->userkey_addr,
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+ (ulong)fpga_sec_info->userkey_addr +
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+ ALIGN(KEY_PTR_LEN,
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+ CONFIG_SYS_CACHELINE_SIZE));
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+ flag |= BIT(ZYNQMP_FPGA_BIT_ENC_USR_KEY);
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+ }
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+
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+ if (!fpga_sec_info->authflag)
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+ flag |= BIT(ZYNQMP_FPGA_BIT_AUTH_OCM);
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+
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+ if (fpga_sec_info->authflag == ZYNQMP_FPGA_AUTH_DDR)
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+ flag |= BIT(ZYNQMP_FPGA_BIT_AUTH_DDR);
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+
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+ buf_lo = lower_32_bits((ulong)buf);
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+ buf_hi = upper_32_bits((ulong)buf);
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+
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+ ret = invoke_smc(ZYNQMP_SIP_SVC_PM_FPGA_LOAD, buf_lo, buf_hi,
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+ (u32)(uintptr_t)fpga_sec_info->userkey_addr,
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+ flag, ret_payload);
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+ if (ret)
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+ puts("PL FPGA LOAD fail\n");
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+ else
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+ puts("Bitstream successfully loaded\n");
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+
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+ return ret;
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+}
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+#endif
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+
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static int zynqmp_pcap_info(xilinx_desc *desc)
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{
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int ret;
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@@ -238,5 +283,8 @@ static int zynqmp_pcap_info(xilinx_desc *desc)
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struct xilinx_fpga_op zynqmp_op = {
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.load = zynqmp_load,
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+#if defined CONFIG_CMD_FPGA_LOAD_SECURE
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+ .loads = zynqmp_loads,
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+#endif
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.info = zynqmp_pcap_info,
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};
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