zynqmppl.c 6.7 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290
  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * (C) Copyright 2015 - 2016, Xilinx, Inc,
  4. * Michal Simek <michal.simek@xilinx.com>
  5. * Siva Durga Prasad <siva.durga.paladugu@xilinx.com>
  6. */
  7. #include <console.h>
  8. #include <common.h>
  9. #include <zynqmppl.h>
  10. #include <linux/sizes.h>
  11. #include <asm/arch/sys_proto.h>
  12. #include <memalign.h>
  13. #define DUMMY_WORD 0xffffffff
  14. /* Xilinx binary format header */
  15. static const u32 bin_format[] = {
  16. DUMMY_WORD, /* Dummy words */
  17. DUMMY_WORD,
  18. DUMMY_WORD,
  19. DUMMY_WORD,
  20. DUMMY_WORD,
  21. DUMMY_WORD,
  22. DUMMY_WORD,
  23. DUMMY_WORD,
  24. DUMMY_WORD,
  25. DUMMY_WORD,
  26. DUMMY_WORD,
  27. DUMMY_WORD,
  28. DUMMY_WORD,
  29. DUMMY_WORD,
  30. DUMMY_WORD,
  31. DUMMY_WORD,
  32. 0x000000bb, /* Sync word */
  33. 0x11220044, /* Sync word */
  34. DUMMY_WORD,
  35. DUMMY_WORD,
  36. 0xaa995566, /* Sync word */
  37. };
  38. #define SWAP_NO 1
  39. #define SWAP_DONE 2
  40. /*
  41. * Load the whole word from unaligned buffer
  42. * Keep in your mind that it is byte loading on little-endian system
  43. */
  44. static u32 load_word(const void *buf, u32 swap)
  45. {
  46. u32 word = 0;
  47. u8 *bitc = (u8 *)buf;
  48. int p;
  49. if (swap == SWAP_NO) {
  50. for (p = 0; p < 4; p++) {
  51. word <<= 8;
  52. word |= bitc[p];
  53. }
  54. } else {
  55. for (p = 3; p >= 0; p--) {
  56. word <<= 8;
  57. word |= bitc[p];
  58. }
  59. }
  60. return word;
  61. }
  62. static u32 check_header(const void *buf)
  63. {
  64. u32 i, pattern;
  65. int swap = SWAP_NO;
  66. u32 *test = (u32 *)buf;
  67. debug("%s: Let's check bitstream header\n", __func__);
  68. /* Checking that passing bin is not a bitstream */
  69. for (i = 0; i < ARRAY_SIZE(bin_format); i++) {
  70. pattern = load_word(&test[i], swap);
  71. /*
  72. * Bitstreams in binary format are swapped
  73. * compare to regular bistream.
  74. * Do not swap dummy word but if swap is done assume
  75. * that parsing buffer is binary format
  76. */
  77. if ((__swab32(pattern) != DUMMY_WORD) &&
  78. (__swab32(pattern) == bin_format[i])) {
  79. swap = SWAP_DONE;
  80. debug("%s: data swapped - let's swap\n", __func__);
  81. }
  82. debug("%s: %d/%px: pattern %x/%x bin_format\n", __func__, i,
  83. &test[i], pattern, bin_format[i]);
  84. }
  85. debug("%s: Found bitstream header at %px %s swapinng\n", __func__,
  86. buf, swap == SWAP_NO ? "without" : "with");
  87. return swap;
  88. }
  89. static void *check_data(u8 *buf, size_t bsize, u32 *swap)
  90. {
  91. u32 word, p = 0; /* possition */
  92. /* Because buf doesn't need to be aligned let's read it by chars */
  93. for (p = 0; p < bsize; p++) {
  94. word = load_word(&buf[p], SWAP_NO);
  95. debug("%s: word %x %x/%px\n", __func__, word, p, &buf[p]);
  96. /* Find the first bitstream dummy word */
  97. if (word == DUMMY_WORD) {
  98. debug("%s: Found dummy word at position %x/%px\n",
  99. __func__, p, &buf[p]);
  100. *swap = check_header(&buf[p]);
  101. if (*swap) {
  102. /* FIXME add full bitstream checking here */
  103. return &buf[p];
  104. }
  105. }
  106. /* Loop can be huge - support CTRL + C */
  107. if (ctrlc())
  108. return NULL;
  109. }
  110. return NULL;
  111. }
  112. static ulong zynqmp_align_dma_buffer(u32 *buf, u32 len, u32 swap)
  113. {
  114. u32 *new_buf;
  115. u32 i;
  116. if ((ulong)buf != ALIGN((ulong)buf, ARCH_DMA_MINALIGN)) {
  117. new_buf = (u32 *)ALIGN((ulong)buf, ARCH_DMA_MINALIGN);
  118. /*
  119. * This might be dangerous but permits to flash if
  120. * ARCH_DMA_MINALIGN is greater than header size
  121. */
  122. if (new_buf > (u32 *)buf) {
  123. debug("%s: Aligned buffer is after buffer start\n",
  124. __func__);
  125. new_buf -= ARCH_DMA_MINALIGN;
  126. }
  127. printf("%s: Align buffer at %px to %px(swap %d)\n", __func__,
  128. buf, new_buf, swap);
  129. for (i = 0; i < (len/4); i++)
  130. new_buf[i] = load_word(&buf[i], swap);
  131. buf = new_buf;
  132. } else if (swap != SWAP_DONE) {
  133. /* For bitstream which are aligned */
  134. u32 *new_buf = (u32 *)buf;
  135. printf("%s: Bitstream is not swapped(%d) - swap it\n", __func__,
  136. swap);
  137. for (i = 0; i < (len/4); i++)
  138. new_buf[i] = load_word(&buf[i], swap);
  139. }
  140. return (ulong)buf;
  141. }
  142. static int zynqmp_validate_bitstream(xilinx_desc *desc, const void *buf,
  143. size_t bsize, u32 blocksize, u32 *swap)
  144. {
  145. ulong *buf_start;
  146. ulong diff;
  147. buf_start = check_data((u8 *)buf, blocksize, swap);
  148. if (!buf_start)
  149. return FPGA_FAIL;
  150. /* Check if data is postpone from start */
  151. diff = (ulong)buf_start - (ulong)buf;
  152. if (diff) {
  153. printf("%s: Bitstream is not validated yet (diff %lx)\n",
  154. __func__, diff);
  155. return FPGA_FAIL;
  156. }
  157. if ((ulong)buf < SZ_1M) {
  158. printf("%s: Bitstream has to be placed up to 1MB (%px)\n",
  159. __func__, buf);
  160. return FPGA_FAIL;
  161. }
  162. return 0;
  163. }
  164. static int zynqmp_load(xilinx_desc *desc, const void *buf, size_t bsize,
  165. bitstream_type bstype)
  166. {
  167. ALLOC_CACHE_ALIGN_BUFFER(u32, bsizeptr, 1);
  168. u32 swap;
  169. ulong bin_buf;
  170. int ret;
  171. u32 buf_lo, buf_hi;
  172. u32 ret_payload[PAYLOAD_ARG_CNT];
  173. if (zynqmp_validate_bitstream(desc, buf, bsize, bsize, &swap))
  174. return FPGA_FAIL;
  175. bin_buf = zynqmp_align_dma_buffer((u32 *)buf, bsize, swap);
  176. bsizeptr = (u32 *)&bsize;
  177. debug("%s called!\n", __func__);
  178. flush_dcache_range(bin_buf, bin_buf + bsize);
  179. flush_dcache_range((ulong)bsizeptr, (ulong)bsizeptr + sizeof(size_t));
  180. buf_lo = (u32)bin_buf;
  181. buf_hi = upper_32_bits(bin_buf);
  182. bstype |= BIT(ZYNQMP_FPGA_BIT_NS);
  183. ret = invoke_smc(ZYNQMP_SIP_SVC_PM_FPGA_LOAD, buf_lo, buf_hi,
  184. (u32)(uintptr_t)bsizeptr, bstype, ret_payload);
  185. if (ret)
  186. debug("PL FPGA LOAD fail\n");
  187. return ret;
  188. }
  189. #if defined(CONFIG_CMD_FPGA_LOAD_SECURE) && !defined(CONFIG_SPL_BUILD)
  190. static int zynqmp_loads(xilinx_desc *desc, const void *buf, size_t bsize,
  191. struct fpga_secure_info *fpga_sec_info)
  192. {
  193. int ret;
  194. u32 buf_lo, buf_hi;
  195. u32 ret_payload[PAYLOAD_ARG_CNT];
  196. u8 flag = 0;
  197. flush_dcache_range((ulong)buf, (ulong)buf +
  198. ALIGN(bsize, CONFIG_SYS_CACHELINE_SIZE));
  199. if (!fpga_sec_info->encflag)
  200. flag |= BIT(ZYNQMP_FPGA_BIT_ENC_DEV_KEY);
  201. if (fpga_sec_info->userkey_addr &&
  202. fpga_sec_info->encflag == FPGA_ENC_USR_KEY) {
  203. flush_dcache_range((ulong)fpga_sec_info->userkey_addr,
  204. (ulong)fpga_sec_info->userkey_addr +
  205. ALIGN(KEY_PTR_LEN,
  206. CONFIG_SYS_CACHELINE_SIZE));
  207. flag |= BIT(ZYNQMP_FPGA_BIT_ENC_USR_KEY);
  208. }
  209. if (!fpga_sec_info->authflag)
  210. flag |= BIT(ZYNQMP_FPGA_BIT_AUTH_OCM);
  211. if (fpga_sec_info->authflag == ZYNQMP_FPGA_AUTH_DDR)
  212. flag |= BIT(ZYNQMP_FPGA_BIT_AUTH_DDR);
  213. buf_lo = lower_32_bits((ulong)buf);
  214. buf_hi = upper_32_bits((ulong)buf);
  215. ret = invoke_smc(ZYNQMP_SIP_SVC_PM_FPGA_LOAD, buf_lo, buf_hi,
  216. (u32)(uintptr_t)fpga_sec_info->userkey_addr,
  217. flag, ret_payload);
  218. if (ret)
  219. puts("PL FPGA LOAD fail\n");
  220. else
  221. puts("Bitstream successfully loaded\n");
  222. return ret;
  223. }
  224. #endif
  225. static int zynqmp_pcap_info(xilinx_desc *desc)
  226. {
  227. int ret;
  228. u32 ret_payload[PAYLOAD_ARG_CNT];
  229. ret = invoke_smc(ZYNQMP_SIP_SVC_PM_FPGA_STATUS, 0, 0, 0,
  230. 0, ret_payload);
  231. if (!ret)
  232. printf("PCAP status\t0x%x\n", ret_payload[1]);
  233. return ret;
  234. }
  235. struct xilinx_fpga_op zynqmp_op = {
  236. .load = zynqmp_load,
  237. #if defined CONFIG_CMD_FPGA_LOAD_SECURE
  238. .loads = zynqmp_loads,
  239. #endif
  240. .info = zynqmp_pcap_info,
  241. };