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@@ -2,6 +2,7 @@
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/*
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* Copyright (C) 2013-2018 Hannes Schmelzer <oe5hpm@oevsv.at>
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* B&R Industrial Automation GmbH - http://www.br-automation.com
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+ * Copyright (C) 2020 Dario Binacchi <dariobin@libero.it>
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*
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* minimal framebuffer driver for TI's AM335x SoC to be compatible with
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* Wolfgang Denk's LCD-Framework (CONFIG_LCD, common/lcd.c)
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@@ -11,19 +12,18 @@
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* - starts output DMA from gd->fb_base buffer
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*/
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#include <common.h>
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+#include <dm.h>
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#include <asm/io.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/omap.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/sys_proto.h>
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+#include <asm/utils.h>
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#include <linux/err.h>
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#include <lcd.h>
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+#include <video.h>
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#include "am335x-fb.h"
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-#if !defined(LCD_CNTL_BASE)
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-#error "hw-base address of LCD-Controller (LCD_CNTL_BASE) not defined!"
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-#endif
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-
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#define LCDC_FMAX 200000000
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/* LCD Control Register */
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@@ -41,6 +41,7 @@
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#define LCDC_DMA_CTRL_BURST_4 0x2
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#define LCDC_DMA_CTRL_BURST_8 0x3
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#define LCDC_DMA_CTRL_BURST_16 0x4
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+#define LCDC_DMA_CTRL_FIFO_TH(x) (((x) & GENMASK(2, 0)) << 8)
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/* LCD Timing_0 Register */
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#define LCDC_RASTER_TIMING_0_HORMSB(x) (((((x) >> 4) - 1) & 0x40) >> 4)
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#define LCDC_RASTER_TIMING_0_HORLSB(x) (((((x) >> 4) - 1) & GENMASK(5, 0)) << 4)
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@@ -55,19 +56,26 @@
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/* LCD Timing_2 Register */
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#define LCDC_RASTER_TIMING_2_HFPMSB(x) ((((x) - 1) & GENMASK(9, 8)) >> 8)
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#define LCDC_RASTER_TIMING_2_HBPMSB(x) ((((x) - 1) & GENMASK(9, 8)) >> 4)
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-#define LCDC_RASTER_TIMING_2_INVMASK(x) ((x) & GENMASK(25, 20))
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+#define LCDC_RASTER_TIMING_2_ACB(x) (((x) & GENMASK(7, 0)) << 8)
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+#define LCDC_RASTER_TIMING_2_ACBI(x) (((x) & GENMASK(3, 0)) << 16)
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+#define LCDC_RASTER_TIMING_2_VSYNC_INVERT BIT(20)
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+#define LCDC_RASTER_TIMING_2_HSYNC_INVERT BIT(21)
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+#define LCDC_RASTER_TIMING_2_PXCLK_INVERT BIT(22)
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+#define LCDC_RASTER_TIMING_2_DE_INVERT BIT(23)
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+#define LCDC_RASTER_TIMING_2_HSVS_RISEFALL BIT(24)
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+#define LCDC_RASTER_TIMING_2_HSVS_CONTROL BIT(25)
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#define LCDC_RASTER_TIMING_2_VERMSB(x) ((((x) - 1) & BIT(10)) << 16)
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#define LCDC_RASTER_TIMING_2_HSWMSB(x) ((((x) - 1) & GENMASK(9, 6)) << 21)
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/* LCD Raster Ctrl Register */
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#define LCDC_RASTER_CTRL_ENABLE BIT(0)
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#define LCDC_RASTER_CTRL_TFT_MODE BIT(7)
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+#define LCDC_RASTER_CTRL_DATA_ORDER BIT(8)
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+#define LCDC_RASTER_CTRL_REQDLY(x) (((x) & GENMASK(7, 0)) << 12)
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#define LCDC_RASTER_CTRL_PALMODE_RAWDATA (0x02 << 20)
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+#define LCDC_RASTER_CTRL_TFT_ALT_ENABLE BIT(23)
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#define LCDC_RASTER_CTRL_TFT_24BPP_MODE BIT(25)
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#define LCDC_RASTER_CTRL_TFT_24BPP_UNPACK BIT(26)
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-/* Macro definitions */
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-#define FBSIZE(x) ((x->hactive * x->vactive * x->bpp) >> 3)
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-
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struct am335x_lcdhw {
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unsigned int pid; /* 0x00 */
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unsigned int ctrl; /* 0x04 */
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@@ -107,8 +115,6 @@ struct dpll_data {
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u8 rounded_div;
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};
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-static struct am335x_lcdhw *lcdhw = (void *)LCD_CNTL_BASE;
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-
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DECLARE_GLOBAL_DATA_PTR;
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/**
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@@ -189,6 +195,19 @@ static ulong am335x_fb_set_pixel_clk_rate(struct am335x_lcdhw *regs, ulong rate)
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return round_rate;
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}
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+#if !CONFIG_IS_ENABLED(DM_VIDEO)
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+
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+#if !defined(LCD_CNTL_BASE)
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+#error "hw-base address of LCD-Controller (LCD_CNTL_BASE) not defined!"
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+#endif
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+
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+/* Macro definitions */
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+#define FBSIZE(x) (((x)->hactive * (x)->vactive * (x)->bpp) >> 3)
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+
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+#define LCDC_RASTER_TIMING_2_INVMASK(x) ((x) & GENMASK(25, 20))
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+
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+static struct am335x_lcdhw *lcdhw = (void *)LCD_CNTL_BASE;
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+
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int lcd_get_size(int *line_length)
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{
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*line_length = (panel_info.vl_col * NBITS(panel_info.vl_bpix)) / 8;
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@@ -299,3 +318,301 @@ int am335xfb_init(struct am335x_lcdpanel *panel)
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return 0;
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}
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+
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+#else /* CONFIG_DM_VIDEO */
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+
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+#define FBSIZE(t, p) (((t)->hactive.typ * (t)->vactive.typ * (p)->bpp) >> 3)
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+
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+enum {
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+ LCD_MAX_WIDTH = 2048,
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+ LCD_MAX_HEIGHT = 2048,
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+ LCD_MAX_LOG2_BPP = VIDEO_BPP32,
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+};
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+
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+/**
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+ * tilcdc_panel_info: Panel parameters
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+ *
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+ * @ac_bias: AC Bias Pin Frequency
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+ * @ac_bias_intrpt: AC Bias Pin Transitions per Interrupt
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+ * @dma_burst_sz: DMA burst size
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+ * @bpp: Bits per pixel
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+ * @fdd: FIFO DMA Request Delay
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+ * @tft_alt_mode: TFT Alternative Signal Mapping (Only for active)
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+ * @invert_pxl_clk: Invert pixel clock
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+ * @sync_edge: Horizontal and Vertical Sync Edge: 0=rising 1=falling
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+ * @sync_ctrl: Horizontal and Vertical Sync: Control: 0=ignore
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+ * @raster_order: Raster Data Order Select: 1=Most-to-least 0=Least-to-most
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+ * @fifo_th: DMA FIFO threshold
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+ */
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+struct tilcdc_panel_info {
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+ u32 ac_bias;
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+ u32 ac_bias_intrpt;
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+ u32 dma_burst_sz;
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+ u32 bpp;
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+ u32 fdd;
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+ bool tft_alt_mode;
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+ bool invert_pxl_clk;
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+ u32 sync_edge;
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+ u32 sync_ctrl;
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+ u32 raster_order;
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+ u32 fifo_th;
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+};
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+
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+struct am335x_fb_priv {
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+ struct am335x_lcdhw *regs;
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+ struct tilcdc_panel_info panel;
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+ struct display_timing timing;
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+};
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+
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+static int am335x_fb_remove(struct udevice *dev)
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+{
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+ struct video_uc_platdata *uc_plat = dev_get_uclass_platdata(dev);
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+
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+ uc_plat->base -= 0x20;
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+ uc_plat->size += 0x20;
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+ return 0;
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+}
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+
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+static int am335x_fb_probe(struct udevice *dev)
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+{
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+ struct video_uc_platdata *uc_plat = dev_get_uclass_platdata(dev);
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+ struct video_priv *uc_priv = dev_get_uclass_priv(dev);
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+ struct am335x_fb_priv *priv = dev_get_priv(dev);
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+ struct am335x_lcdhw *regs = priv->regs;
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+ struct tilcdc_panel_info *panel = &priv->panel;
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+ struct display_timing *timing = &priv->timing;
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+ struct cm_dpll *const cmdpll = (struct cm_dpll *)CM_DPLL;
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+ u32 reg;
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+
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+ /* Before relocation we don't need to do anything */
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+ if (!(gd->flags & GD_FLG_RELOC))
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+ return 0;
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+
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+ am335x_fb_set_pixel_clk_rate(regs, timing->pixelclock.typ);
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+
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+ /* clock source for LCDC from dispPLL M2 */
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+ writel(0, &cmdpll->clklcdcpixelclk);
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+
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+ /* palette default entry */
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+ memset((void *)uc_plat->base, 0, 0x20);
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+ *(unsigned int *)uc_plat->base = 0x4000;
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+ /* point fb behind palette */
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+ uc_plat->base += 0x20;
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+ uc_plat->size -= 0x20;
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+
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+ writel(LCDC_CLKC_ENABLE_CORECLKEN | LCDC_CLKC_ENABLE_LIDDCLKEN |
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+ LCDC_CLKC_ENABLE_DMACLKEN, ®s->clkc_enable);
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+ writel(0, ®s->raster_ctrl);
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+
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+ reg = readl(®s->ctrl) & LCDC_CTRL_CLK_DIVISOR_MASK;
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+ reg |= LCDC_CTRL_RASTER_MODE;
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+ writel(reg, ®s->ctrl);
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+
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+ writel(uc_plat->base, ®s->lcddma_fb0_base);
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+ writel(uc_plat->base + FBSIZE(timing, panel),
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+ ®s->lcddma_fb0_ceiling);
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+ writel(uc_plat->base, ®s->lcddma_fb1_base);
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+ writel(uc_plat->base + FBSIZE(timing, panel),
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+ ®s->lcddma_fb1_ceiling);
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+
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+ reg = LCDC_DMA_CTRL_FIFO_TH(panel->fifo_th);
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+ switch (panel->dma_burst_sz) {
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+ case 1:
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+ reg |= LCDC_DMA_CTRL_BURST_SIZE(LCDC_DMA_CTRL_BURST_1);
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+ break;
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+ case 2:
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+ reg |= LCDC_DMA_CTRL_BURST_SIZE(LCDC_DMA_CTRL_BURST_2);
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+ break;
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+ case 4:
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+ reg |= LCDC_DMA_CTRL_BURST_SIZE(LCDC_DMA_CTRL_BURST_4);
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+ break;
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+ case 8:
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+ reg |= LCDC_DMA_CTRL_BURST_SIZE(LCDC_DMA_CTRL_BURST_8);
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+ break;
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+ case 16:
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+ reg |= LCDC_DMA_CTRL_BURST_SIZE(LCDC_DMA_CTRL_BURST_16);
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+ break;
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+ }
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+
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+ writel(reg, ®s->lcddma_ctrl);
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+
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+ writel(LCDC_RASTER_TIMING_0_HORLSB(timing->hactive.typ) |
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+ LCDC_RASTER_TIMING_0_HORMSB(timing->hactive.typ) |
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+ LCDC_RASTER_TIMING_0_HFPLSB(timing->hfront_porch.typ) |
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+ LCDC_RASTER_TIMING_0_HBPLSB(timing->hback_porch.typ) |
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+ LCDC_RASTER_TIMING_0_HSWLSB(timing->hsync_len.typ),
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+ ®s->raster_timing0);
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+
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+ writel(LCDC_RASTER_TIMING_1_VBP(timing->vback_porch.typ) |
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+ LCDC_RASTER_TIMING_1_VFP(timing->vfront_porch.typ) |
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+ LCDC_RASTER_TIMING_1_VSW(timing->vsync_len.typ) |
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+ LCDC_RASTER_TIMING_1_VERLSB(timing->vactive.typ),
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+ ®s->raster_timing1);
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+
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+ reg = LCDC_RASTER_TIMING_2_ACB(panel->ac_bias) |
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+ LCDC_RASTER_TIMING_2_ACBI(panel->ac_bias_intrpt) |
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+ LCDC_RASTER_TIMING_2_HSWMSB(timing->hsync_len.typ) |
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+ LCDC_RASTER_TIMING_2_VERMSB(timing->vactive.typ) |
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+ LCDC_RASTER_TIMING_2_HBPMSB(timing->hback_porch.typ) |
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+ LCDC_RASTER_TIMING_2_HFPMSB(timing->hfront_porch.typ);
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+
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+ if (timing->flags & DISPLAY_FLAGS_VSYNC_LOW)
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+ reg |= LCDC_RASTER_TIMING_2_VSYNC_INVERT;
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+
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+ if (timing->flags & DISPLAY_FLAGS_HSYNC_LOW)
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+ reg |= LCDC_RASTER_TIMING_2_HSYNC_INVERT;
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+
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+ if (panel->invert_pxl_clk)
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+ reg |= LCDC_RASTER_TIMING_2_PXCLK_INVERT;
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+
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+ if (panel->sync_edge)
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+ reg |= LCDC_RASTER_TIMING_2_HSVS_RISEFALL;
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+
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+ if (panel->sync_ctrl)
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+ reg |= LCDC_RASTER_TIMING_2_HSVS_CONTROL;
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+
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+ writel(reg, ®s->raster_timing2);
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+
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+ reg = LCDC_RASTER_CTRL_PALMODE_RAWDATA | LCDC_RASTER_CTRL_TFT_MODE |
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+ LCDC_RASTER_CTRL_ENABLE | LCDC_RASTER_CTRL_REQDLY(panel->fdd);
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+
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+ if (panel->tft_alt_mode)
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+ reg |= LCDC_RASTER_CTRL_TFT_ALT_ENABLE;
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+
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+ if (panel->bpp == 24)
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+ reg |= LCDC_RASTER_CTRL_TFT_24BPP_MODE;
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+ else if (panel->bpp == 32)
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+ reg |= LCDC_RASTER_CTRL_TFT_24BPP_MODE |
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+ LCDC_RASTER_CTRL_TFT_24BPP_UNPACK;
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+
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+ if (panel->raster_order)
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+ reg |= LCDC_RASTER_CTRL_DATA_ORDER;
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+
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+ writel(reg, ®s->raster_ctrl);
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+
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+ uc_priv->xsize = timing->hactive.typ;
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+ uc_priv->ysize = timing->vactive.typ;
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+ uc_priv->bpix = log_2_n_round_up(panel->bpp);
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+ return 0;
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+}
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+
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+static int am335x_fb_ofdata_to_platdata(struct udevice *dev)
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+{
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+ struct am335x_fb_priv *priv = dev_get_priv(dev);
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+ struct tilcdc_panel_info *panel = &priv->panel;
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+ struct display_timing *timing = &priv->timing;
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+ ofnode node;
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+ int err;
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+
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+ node = ofnode_by_compatible(ofnode_null(), "ti,am33xx-tilcdc");
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+ if (!ofnode_valid(node)) {
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+ dev_err(dev, "missing 'ti,am33xx-tilcdc' node\n");
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+ return -ENXIO;
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+ }
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+
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+ priv->regs = (struct am335x_lcdhw *)ofnode_get_addr(node);
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+ dev_dbg(dev, "LCD: base address=0x%x\n", (unsigned int)priv->regs);
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+
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+ err = ofnode_decode_display_timing(dev_ofnode(dev), 0, timing);
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+ if (err) {
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+ dev_err(dev, "failed to get display timing\n");
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+ return err;
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+ }
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+
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+ if (timing->pixelclock.typ > (LCDC_FMAX / 2)) {
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+ dev_err(dev, "invalid display clock-frequency: %d Hz\n",
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+ timing->pixelclock.typ);
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+ return -EINVAL;
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+ }
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+
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+ if (timing->hactive.typ > LCD_MAX_WIDTH)
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+ timing->hactive.typ = LCD_MAX_WIDTH;
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+
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+ if (timing->vactive.typ > LCD_MAX_HEIGHT)
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+ timing->vactive.typ = LCD_MAX_HEIGHT;
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+
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+ node = ofnode_find_subnode(dev_ofnode(dev), "panel-info");
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+ if (!ofnode_valid(node)) {
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+ dev_err(dev, "missing 'panel-info' node\n");
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+ return -ENXIO;
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+ }
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+
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+ err |= ofnode_read_u32(node, "ac-bias", &panel->ac_bias);
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+ err |= ofnode_read_u32(node, "ac-bias-intrpt", &panel->ac_bias_intrpt);
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+ err |= ofnode_read_u32(node, "dma-burst-sz", &panel->dma_burst_sz);
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+ err |= ofnode_read_u32(node, "bpp", &panel->bpp);
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+ err |= ofnode_read_u32(node, "fdd", &panel->fdd);
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+ err |= ofnode_read_u32(node, "sync-edge", &panel->sync_edge);
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+ err |= ofnode_read_u32(node, "sync-ctrl", &panel->sync_ctrl);
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+ err |= ofnode_read_u32(node, "raster-order", &panel->raster_order);
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+ err |= ofnode_read_u32(node, "fifo-th", &panel->fifo_th);
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+ if (err) {
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+ dev_err(dev, "failed to get panel info\n");
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+ return err;
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+ }
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+
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+ switch (panel->bpp) {
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+ case 16:
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+ case 24:
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+ case 32:
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+ break;
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+ default:
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+ dev_err(dev, "invalid seting, bpp: %d\n", panel->bpp);
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|
+ return -EINVAL;
|
|
|
+ }
|
|
|
+
|
|
|
+ switch (panel->dma_burst_sz) {
|
|
|
+ case 1:
|
|
|
+ case 2:
|
|
|
+ case 4:
|
|
|
+ case 8:
|
|
|
+ case 16:
|
|
|
+ break;
|
|
|
+ default:
|
|
|
+ dev_err(dev, "invalid setting, dma-burst-sz: %d\n",
|
|
|
+ panel->dma_burst_sz);
|
|
|
+ return -EINVAL;
|
|
|
+ }
|
|
|
+
|
|
|
+ /* optional */
|
|
|
+ panel->tft_alt_mode = ofnode_read_bool(node, "tft-alt-mode");
|
|
|
+ panel->invert_pxl_clk = ofnode_read_bool(node, "invert-pxl-clk");
|
|
|
+
|
|
|
+ dev_dbg(dev, "LCD: %dx%d, bpp=%d, clk=%d Hz\n", timing->hactive.typ,
|
|
|
+ timing->vactive.typ, panel->bpp, timing->pixelclock.typ);
|
|
|
+ dev_dbg(dev, " hbp=%d, hfp=%d, hsw=%d\n", timing->hback_porch.typ,
|
|
|
+ timing->hfront_porch.typ, timing->hsync_len.typ);
|
|
|
+ dev_dbg(dev, " vbp=%d, vfp=%d, vsw=%d\n", timing->vback_porch.typ,
|
|
|
+ timing->vfront_porch.typ, timing->vsync_len.typ);
|
|
|
+
|
|
|
+ return 0;
|
|
|
+}
|
|
|
+
|
|
|
+static int am335x_fb_bind(struct udevice *dev)
|
|
|
+{
|
|
|
+ struct video_uc_platdata *uc_plat = dev_get_uclass_platdata(dev);
|
|
|
+
|
|
|
+ uc_plat->size = ((LCD_MAX_WIDTH * LCD_MAX_HEIGHT *
|
|
|
+ (1 << LCD_MAX_LOG2_BPP)) >> 3) + 0x20;
|
|
|
+
|
|
|
+ dev_dbg(dev, "frame buffer size 0x%x\n", uc_plat->size);
|
|
|
+ return 0;
|
|
|
+}
|
|
|
+
|
|
|
+static const struct udevice_id am335x_fb_ids[] = {
|
|
|
+ { .compatible = "ti,tilcdc,panel" },
|
|
|
+ { }
|
|
|
+};
|
|
|
+
|
|
|
+U_BOOT_DRIVER(am335x_fb) = {
|
|
|
+ .name = "am335x_fb",
|
|
|
+ .id = UCLASS_VIDEO,
|
|
|
+ .of_match = am335x_fb_ids,
|
|
|
+ .bind = am335x_fb_bind,
|
|
|
+ .ofdata_to_platdata = am335x_fb_ofdata_to_platdata,
|
|
|
+ .probe = am335x_fb_probe,
|
|
|
+ .remove = am335x_fb_remove,
|
|
|
+ .priv_auto_alloc_size = sizeof(struct am335x_fb_priv),
|
|
|
+};
|
|
|
+
|
|
|
+#endif /* CONFIG_DM_VIDEO */
|