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@@ -16,6 +16,7 @@
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#include <asm/arch/omap.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/sys_proto.h>
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+#include <linux/err.h>
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#include <lcd.h>
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#include "am335x-fb.h"
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@@ -26,6 +27,7 @@
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#define LCDC_FMAX 200000000
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/* LCD Control Register */
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+#define LCDC_CTRL_CLK_DIVISOR_MASK GENMASK(15, 8)
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#define LCDC_CTRL_RASTER_MODE BIT(0)
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#define LCDC_CTRL_CLK_DIVISOR(x) (((x) & GENMASK(7, 0)) << 8)
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/* LCD Clock Enable Register */
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@@ -98,10 +100,95 @@ struct am335x_lcdhw {
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unsigned int clkc_reset; /* 0x70 */
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};
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+struct dpll_data {
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+ unsigned long rounded_rate;
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+ u16 rounded_m;
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+ u8 rounded_n;
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+ u8 rounded_div;
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+};
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+
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static struct am335x_lcdhw *lcdhw = (void *)LCD_CNTL_BASE;
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DECLARE_GLOBAL_DATA_PTR;
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+/**
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+ * am335x_dpll_round_rate() - Round a target rate for an OMAP DPLL
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+ *
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+ * @dpll_data: struct dpll_data pointer for the DPLL
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+ * @rate: New DPLL clock rate
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+ * @return rounded rate and the computed m, n and div values in the dpll_data
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+ * structure, or -ve error code.
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+ */
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+static ulong am335x_dpll_round_rate(struct dpll_data *dd, ulong rate)
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+{
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+ unsigned int m, n, d;
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+ unsigned long rounded_rate;
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+ int err, err_r;
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+
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+ dd->rounded_rate = -EFAULT;
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+ err = rate;
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+ err_r = err;
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+
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+ for (d = 2; err && d < 255; d++) {
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+ for (m = 2; m < 2047; m++) {
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+ if ((V_OSCK * m) < (rate * d))
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+ continue;
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+
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+ n = (V_OSCK * m) / (rate * d);
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+ if (n > 127)
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+ break;
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+
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+ if (((V_OSCK * m) / n) > LCDC_FMAX)
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+ break;
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+
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+ rounded_rate = (V_OSCK * m) / n / d;
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+ err = abs(rounded_rate - rate);
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+ if (err < err_r) {
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+ err_r = err;
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+ dd->rounded_rate = rounded_rate;
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+ dd->rounded_m = m;
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+ dd->rounded_n = n;
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+ dd->rounded_div = d;
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+ if (err == 0)
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+ break;
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+ }
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+ }
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+ }
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+
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+ debug("DPLL display: best error %d Hz (M %d, N %d, DIV %d)\n",
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+ err_r, dd->rounded_m, dd->rounded_n, dd->rounded_div);
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+
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+ return dd->rounded_rate;
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+}
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+
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+/**
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+ * am335x_fb_set_pixel_clk_rate() - Set pixel clock rate.
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+ *
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+ * @am335x_lcdhw: Base address of the LCD controller registers.
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+ * @rate: New clock rate in Hz.
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+ * @return new rate, or -ve error code.
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+ */
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+static ulong am335x_fb_set_pixel_clk_rate(struct am335x_lcdhw *regs, ulong rate)
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+{
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+ struct dpll_params dpll_disp = { 1, 0, 1, -1, -1, -1, -1 };
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+ struct dpll_data dd;
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+ ulong round_rate;
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+ u32 reg;
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+
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+ round_rate = am335x_dpll_round_rate(&dd, rate);
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+ if (IS_ERR_VALUE(round_rate))
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+ return round_rate;
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+
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+ dpll_disp.m = dd.rounded_m;
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+ dpll_disp.n = dd.rounded_n;
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+ do_setup_dpll(&dpll_disp_regs, &dpll_disp);
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+
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+ reg = readl(®s->ctrl) & ~LCDC_CTRL_CLK_DIVISOR_MASK;
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+ reg |= LCDC_CTRL_CLK_DIVISOR(dd.rounded_div);
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+ writel(reg, ®s->ctrl);
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+ return round_rate;
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+}
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+
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int lcd_get_size(int *line_length)
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{
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*line_length = (panel_info.vl_col * NBITS(panel_info.vl_bpix)) / 8;
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@@ -111,11 +198,9 @@ int lcd_get_size(int *line_length)
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int am335xfb_init(struct am335x_lcdpanel *panel)
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{
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u32 raster_ctrl = 0;
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-
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struct cm_dpll *const cmdpll = (struct cm_dpll *)CM_DPLL;
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- struct dpll_params dpll_disp = { 1, 0, 1, -1, -1, -1, -1 };
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- unsigned int m, n, d, best_d = 2;
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- int err = 0, err_r = 0;
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+ ulong rate;
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+ u32 reg;
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if (gd->fb_base == 0) {
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printf("ERROR: no valid fb_base stored in GLOBAL_DATA_PTR!\n");
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@@ -156,34 +241,9 @@ int am335xfb_init(struct am335x_lcdpanel *panel)
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debug("using frambuffer at 0x%08x with size %d.\n",
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(unsigned int)gd->fb_base, FBSIZE(panel));
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- /* setup display pll for requested clock frequency */
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- err = panel->pxl_clk;
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- err_r = err;
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-
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- for (d = 2; err_r && d < 255; d++) {
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- for (m = 2; m < 2047; m++) {
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- if ((V_OSCK * m) < (panel->pxl_clk * d))
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- continue;
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- n = (V_OSCK * m) / (panel->pxl_clk * d);
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- if (n > 127)
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- break;
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- if (((V_OSCK * m) / n) > LCDC_FMAX)
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- break;
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-
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- err = abs((V_OSCK * m) / n / d - panel->pxl_clk);
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- if (err < err_r) {
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- err_r = err;
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- dpll_disp.m = m;
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- dpll_disp.n = n;
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- best_d = d;
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- if (err_r == 0)
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- break;
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- }
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- }
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- }
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- debug("%s: PLL: best error %d Hz (M %d, N %d, DIV %d)\n",
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- __func__, err_r, dpll_disp.m, dpll_disp.n, best_d);
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- do_setup_dpll(&dpll_disp_regs, &dpll_disp);
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+ rate = am335x_fb_set_pixel_clk_rate(lcdhw, panel->pxl_clk);
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+ if (IS_ERR_VALUE(rate))
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+ return rate;
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/* clock source for LCDC from dispPLL M2 */
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writel(0x0, &cmdpll->clklcdcpixelclk);
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@@ -203,7 +263,11 @@ int am335xfb_init(struct am335x_lcdpanel *panel)
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lcdhw->clkc_enable = LCDC_CLKC_ENABLE_CORECLKEN |
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LCDC_CLKC_ENABLE_LIDDCLKEN | LCDC_CLKC_ENABLE_DMACLKEN;
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lcdhw->raster_ctrl = 0;
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- lcdhw->ctrl = LCDC_CTRL_CLK_DIVISOR(best_d) | LCDC_CTRL_RASTER_MODE;
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+
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+ reg = lcdhw->ctrl & LCDC_CTRL_CLK_DIVISOR_MASK;
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+ reg |= LCDC_CTRL_RASTER_MODE;
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+ lcdhw->ctrl = reg;
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+
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lcdhw->lcddma_fb0_base = gd->fb_base;
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lcdhw->lcddma_fb0_ceiling = gd->fb_base + FBSIZE(panel);
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lcdhw->lcddma_fb1_base = gd->fb_base;
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