clock_am33xx.c 8.8 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * clock_am33xx.c
  4. *
  5. * clocks for AM33XX based boards
  6. *
  7. * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
  8. */
  9. #include <common.h>
  10. #include <asm/arch/cpu.h>
  11. #include <asm/arch/sys_proto.h>
  12. #include <asm/arch/clock.h>
  13. #include <asm/arch/hardware.h>
  14. #include <asm/io.h>
  15. #define OSC (V_OSCK/1000000)
  16. struct cm_perpll *const cmper = (struct cm_perpll *)CM_PER;
  17. struct cm_wkuppll *const cmwkup = (struct cm_wkuppll *)CM_WKUP;
  18. struct cm_dpll *const cmdpll = (struct cm_dpll *)CM_DPLL;
  19. struct cm_rtc *const cmrtc = (struct cm_rtc *)CM_RTC;
  20. const struct dpll_regs dpll_mpu_regs = {
  21. .cm_clkmode_dpll = CM_WKUP + 0x88,
  22. .cm_idlest_dpll = CM_WKUP + 0x20,
  23. .cm_clksel_dpll = CM_WKUP + 0x2C,
  24. .cm_div_m2_dpll = CM_WKUP + 0xA8,
  25. };
  26. const struct dpll_regs dpll_core_regs = {
  27. .cm_clkmode_dpll = CM_WKUP + 0x90,
  28. .cm_idlest_dpll = CM_WKUP + 0x5C,
  29. .cm_clksel_dpll = CM_WKUP + 0x68,
  30. .cm_div_m4_dpll = CM_WKUP + 0x80,
  31. .cm_div_m5_dpll = CM_WKUP + 0x84,
  32. .cm_div_m6_dpll = CM_WKUP + 0xD8,
  33. };
  34. const struct dpll_regs dpll_per_regs = {
  35. .cm_clkmode_dpll = CM_WKUP + 0x8C,
  36. .cm_idlest_dpll = CM_WKUP + 0x70,
  37. .cm_clksel_dpll = CM_WKUP + 0x9C,
  38. .cm_div_m2_dpll = CM_WKUP + 0xAC,
  39. };
  40. const struct dpll_regs dpll_ddr_regs = {
  41. .cm_clkmode_dpll = CM_WKUP + 0x94,
  42. .cm_idlest_dpll = CM_WKUP + 0x34,
  43. .cm_clksel_dpll = CM_WKUP + 0x40,
  44. .cm_div_m2_dpll = CM_WKUP + 0xA0,
  45. };
  46. const struct dpll_regs dpll_disp_regs = {
  47. .cm_clkmode_dpll = CM_WKUP + 0x98,
  48. .cm_idlest_dpll = CM_WKUP + 0x48,
  49. .cm_clksel_dpll = CM_WKUP + 0x54,
  50. .cm_div_m2_dpll = CM_WKUP + 0xA4,
  51. };
  52. struct dpll_params dpll_mpu_opp100 = {
  53. CONFIG_SYS_MPUCLK, OSC-1, 1, -1, -1, -1, -1};
  54. const struct dpll_params dpll_core_opp100 = {
  55. 1000, OSC-1, -1, -1, 10, 8, 4};
  56. const struct dpll_params dpll_mpu_opp[NUM_CRYSTAL_FREQ][NUM_OPPS] = {
  57. { /* 19.2 MHz */
  58. {125, 3, 2, -1, -1, -1, -1}, /* OPP 50 */
  59. {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */
  60. {125, 3, 1, -1, -1, -1, -1}, /* OPP 100 */
  61. {150, 3, 1, -1, -1, -1, -1}, /* OPP 120 */
  62. {125, 2, 1, -1, -1, -1, -1}, /* OPP TB */
  63. {625, 11, 1, -1, -1, -1, -1} /* OPP NT */
  64. },
  65. { /* 24 MHz */
  66. {25, 0, 2, -1, -1, -1, -1}, /* OPP 50 */
  67. {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */
  68. {25, 0, 1, -1, -1, -1, -1}, /* OPP 100 */
  69. {30, 0, 1, -1, -1, -1, -1}, /* OPP 120 */
  70. {100, 2, 1, -1, -1, -1, -1}, /* OPP TB */
  71. {125, 2, 1, -1, -1, -1, -1} /* OPP NT */
  72. },
  73. { /* 25 MHz */
  74. {24, 0, 2, -1, -1, -1, -1}, /* OPP 50 */
  75. {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */
  76. {24, 0, 1, -1, -1, -1, -1}, /* OPP 100 */
  77. {144, 4, 1, -1, -1, -1, -1}, /* OPP 120 */
  78. {32, 0, 1, -1, -1, -1, -1}, /* OPP TB */
  79. {40, 0, 1, -1, -1, -1, -1} /* OPP NT */
  80. },
  81. { /* 26 MHz */
  82. {300, 12, 2, -1, -1, -1, -1}, /* OPP 50 */
  83. {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */
  84. {300, 12, 1, -1, -1, -1, -1}, /* OPP 100 */
  85. {360, 12, 1, -1, -1, -1, -1}, /* OPP 120 */
  86. {400, 12, 1, -1, -1, -1, -1}, /* OPP TB */
  87. {500, 12, 1, -1, -1, -1, -1} /* OPP NT */
  88. },
  89. };
  90. const struct dpll_params dpll_core_1000MHz[NUM_CRYSTAL_FREQ] = {
  91. {625, 11, -1, -1, 10, 8, 4}, /* 19.2 MHz */
  92. {125, 2, -1, -1, 10, 8, 4}, /* 24 MHz */
  93. {40, 0, -1, -1, 10, 8, 4}, /* 25 MHz */
  94. {500, 12, -1, -1, 10, 8, 4} /* 26 MHz */
  95. };
  96. const struct dpll_params dpll_per_192MHz[NUM_CRYSTAL_FREQ] = {
  97. {400, 7, 5, -1, -1, -1, -1}, /* 19.2 MHz */
  98. {400, 9, 5, -1, -1, -1, -1}, /* 24 MHz */
  99. {384, 9, 5, -1, -1, -1, -1}, /* 25 MHz */
  100. {480, 12, 5, -1, -1, -1, -1} /* 26 MHz */
  101. };
  102. const struct dpll_params dpll_ddr3_303MHz[NUM_CRYSTAL_FREQ] = {
  103. {505, 15, 2, -1, -1, -1, -1}, /*19.2*/
  104. {101, 3, 2, -1, -1, -1, -1}, /* 24 MHz */
  105. {303, 24, 1, -1, -1, -1, -1}, /* 25 MHz */
  106. {303, 12, 2, -1, -1, -1, -1} /* 26 MHz */
  107. };
  108. const struct dpll_params dpll_ddr3_400MHz[NUM_CRYSTAL_FREQ] = {
  109. {125, 5, 1, -1, -1, -1, -1}, /*19.2*/
  110. {50, 2, 1, -1, -1, -1, -1}, /* 24 MHz */
  111. {16, 0, 1, -1, -1, -1, -1}, /* 25 MHz */
  112. {200, 12, 1, -1, -1, -1, -1} /* 26 MHz */
  113. };
  114. const struct dpll_params dpll_ddr2_266MHz[NUM_CRYSTAL_FREQ] = {
  115. {665, 47, 1, -1, -1, -1, -1}, /*19.2*/
  116. {133, 11, 1, -1, -1, -1, -1}, /* 24 MHz */
  117. {266, 24, 1, -1, -1, -1, -1}, /* 25 MHz */
  118. {133, 12, 1, -1, -1, -1, -1} /* 26 MHz */
  119. };
  120. __weak const struct dpll_params *get_dpll_mpu_params(void)
  121. {
  122. return &dpll_mpu_opp100;
  123. }
  124. const struct dpll_params *get_dpll_core_params(void)
  125. {
  126. int ind = get_sys_clk_index();
  127. return &dpll_core_1000MHz[ind];
  128. }
  129. const struct dpll_params *get_dpll_per_params(void)
  130. {
  131. int ind = get_sys_clk_index();
  132. return &dpll_per_192MHz[ind];
  133. }
  134. void setup_clocks_for_console(void)
  135. {
  136. clrsetbits_le32(&cmwkup->wkclkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK,
  137. CD_CLKCTRL_CLKTRCTRL_SW_WKUP <<
  138. CD_CLKCTRL_CLKTRCTRL_SHIFT);
  139. clrsetbits_le32(&cmper->l4hsclkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK,
  140. CD_CLKCTRL_CLKTRCTRL_SW_WKUP <<
  141. CD_CLKCTRL_CLKTRCTRL_SHIFT);
  142. clrsetbits_le32(&cmwkup->wkup_uart0ctrl,
  143. MODULE_CLKCTRL_MODULEMODE_MASK,
  144. MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
  145. MODULE_CLKCTRL_MODULEMODE_SHIFT);
  146. clrsetbits_le32(&cmper->uart1clkctrl,
  147. MODULE_CLKCTRL_MODULEMODE_MASK,
  148. MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
  149. MODULE_CLKCTRL_MODULEMODE_SHIFT);
  150. clrsetbits_le32(&cmper->uart2clkctrl,
  151. MODULE_CLKCTRL_MODULEMODE_MASK,
  152. MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
  153. MODULE_CLKCTRL_MODULEMODE_SHIFT);
  154. clrsetbits_le32(&cmper->uart3clkctrl,
  155. MODULE_CLKCTRL_MODULEMODE_MASK,
  156. MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
  157. MODULE_CLKCTRL_MODULEMODE_SHIFT);
  158. clrsetbits_le32(&cmper->uart4clkctrl,
  159. MODULE_CLKCTRL_MODULEMODE_MASK,
  160. MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
  161. MODULE_CLKCTRL_MODULEMODE_SHIFT);
  162. clrsetbits_le32(&cmper->uart5clkctrl,
  163. MODULE_CLKCTRL_MODULEMODE_MASK,
  164. MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
  165. MODULE_CLKCTRL_MODULEMODE_SHIFT);
  166. }
  167. void enable_basic_clocks(void)
  168. {
  169. u32 *const clk_domains[] = {
  170. &cmper->l3clkstctrl,
  171. &cmper->l4fwclkstctrl,
  172. &cmper->l3sclkstctrl,
  173. &cmper->l4lsclkstctrl,
  174. &cmwkup->wkclkstctrl,
  175. &cmper->emiffwclkctrl,
  176. &cmrtc->clkstctrl,
  177. 0
  178. };
  179. u32 *const clk_modules_explicit_en[] = {
  180. &cmper->l3clkctrl,
  181. &cmper->l4lsclkctrl,
  182. &cmper->l4fwclkctrl,
  183. &cmwkup->wkl4wkclkctrl,
  184. &cmper->l3instrclkctrl,
  185. &cmper->l4hsclkctrl,
  186. &cmwkup->wkgpio0clkctrl,
  187. &cmwkup->wkctrlclkctrl,
  188. &cmper->timer2clkctrl,
  189. &cmper->gpmcclkctrl,
  190. &cmper->elmclkctrl,
  191. &cmper->mmc0clkctrl,
  192. &cmper->mmc1clkctrl,
  193. &cmwkup->wkup_i2c0ctrl,
  194. &cmper->gpio1clkctrl,
  195. &cmper->gpio2clkctrl,
  196. &cmper->gpio3clkctrl,
  197. &cmper->i2c1clkctrl,
  198. &cmper->cpgmac0clkctrl,
  199. &cmper->spi0clkctrl,
  200. &cmrtc->rtcclkctrl,
  201. &cmper->usb0clkctrl,
  202. &cmper->emiffwclkctrl,
  203. &cmper->emifclkctrl,
  204. #if CONFIG_IS_ENABLED(AM335X_LCD)
  205. &cmper->lcdclkctrl,
  206. &cmper->lcdcclkstctrl,
  207. #endif
  208. 0
  209. };
  210. do_enable_clocks(clk_domains, clk_modules_explicit_en, 1);
  211. /* Select the Master osc 24 MHZ as Timer2 clock source */
  212. writel(0x1, &cmdpll->clktimer2clk);
  213. }
  214. /*
  215. * Enable Spread Spectrum for the MPU by calculating the required
  216. * values and setting the registers accordingly.
  217. * @param permille The spreading in permille (10th of a percent)
  218. */
  219. void set_mpu_spreadspectrum(int permille)
  220. {
  221. u32 multiplier_m;
  222. u32 predivider_n;
  223. u32 cm_clksel_dpll_mpu;
  224. u32 cm_clkmode_dpll_mpu;
  225. u32 ref_clock;
  226. u32 pll_bandwidth;
  227. u32 mod_freq_divider;
  228. u32 exponent;
  229. u32 mantissa;
  230. u32 delta_m_step;
  231. printf("Enabling Spread Spectrum of %d permille for MPU\n",
  232. permille);
  233. /* Read PLL parameter m and n */
  234. cm_clksel_dpll_mpu = readl(&cmwkup->clkseldpllmpu);
  235. multiplier_m = (cm_clksel_dpll_mpu >> 8) & 0x3FF;
  236. predivider_n = cm_clksel_dpll_mpu & 0x7F;
  237. /*
  238. * Calculate reference clock (clock after pre-divider),
  239. * its max. PLL bandwidth,
  240. * and resulting mod_freq_divider
  241. */
  242. ref_clock = V_OSCK / (predivider_n + 1);
  243. pll_bandwidth = ref_clock / 70;
  244. mod_freq_divider = ref_clock / (4 * pll_bandwidth);
  245. /* Calculate Mantissa/Exponent */
  246. exponent = 0;
  247. mantissa = mod_freq_divider;
  248. while ((mantissa > 127) && (exponent < 7)) {
  249. exponent++;
  250. mantissa /= 2;
  251. }
  252. if (mantissa > 127)
  253. mantissa = 127;
  254. mod_freq_divider = mantissa << exponent;
  255. /*
  256. * Calculate Modulation steps
  257. * As we use Downspread only, the spread is twice the value of
  258. * permille, so Div2!
  259. * As it takes the value in percent, divide by ten!
  260. */
  261. delta_m_step = ((u32)((multiplier_m * permille) / 10 / 2)) << 18;
  262. delta_m_step /= 100;
  263. delta_m_step /= mod_freq_divider;
  264. if (delta_m_step > 0xFFFFF)
  265. delta_m_step = 0xFFFFF;
  266. /* Setup Spread Spectrum */
  267. writel(delta_m_step, &cmwkup->sscdeltamstepdllmpu);
  268. writel((exponent << 8) | mantissa, &cmwkup->sscmodfreqdivdpllmpu);
  269. cm_clkmode_dpll_mpu = readl(&cmwkup->clkmoddpllmpu);
  270. /* clear all SSC flags */
  271. cm_clkmode_dpll_mpu &= ~(0xF << CM_CLKMODE_DPLL_SSC_EN_SHIFT);
  272. /* enable SSC with Downspread only */
  273. cm_clkmode_dpll_mpu |= CM_CLKMODE_DPLL_SSC_EN_MASK |
  274. CM_CLKMODE_DPLL_SSC_DOWNSPREAD_MASK;
  275. writel(cm_clkmode_dpll_mpu, &cmwkup->clkmoddpllmpu);
  276. while (!(readl(&cmwkup->clkmoddpllmpu) & 0x2000))
  277. ;
  278. }