|
@@ -86,6 +86,7 @@
|
|
|
#clock-cells = <0>;
|
|
|
compatible = "fixed-clock";
|
|
|
clock-frequency = <24000000>;
|
|
|
+ clock-accuracy = <50000>;
|
|
|
clock-output-names = "osc24M";
|
|
|
};
|
|
|
|
|
@@ -93,15 +94,8 @@
|
|
|
#clock-cells = <0>;
|
|
|
compatible = "fixed-clock";
|
|
|
clock-frequency = <32768>;
|
|
|
- clock-output-names = "osc32k";
|
|
|
- };
|
|
|
-
|
|
|
- iosc: internal-osc-clk {
|
|
|
- #clock-cells = <0>;
|
|
|
- compatible = "fixed-clock";
|
|
|
- clock-frequency = <16000000>;
|
|
|
- clock-accuracy = <300000000>;
|
|
|
- clock-output-names = "iosc";
|
|
|
+ clock-accuracy = <50000>;
|
|
|
+ clock-output-names = "ext_osc32k";
|
|
|
};
|
|
|
};
|
|
|
|
|
@@ -115,15 +109,16 @@
|
|
|
compatible = "simple-bus";
|
|
|
#address-cells = <1>;
|
|
|
#size-cells = <1>;
|
|
|
+ dma-ranges;
|
|
|
ranges;
|
|
|
|
|
|
display_clocks: clock@1000000 {
|
|
|
/* compatible is in per SoC .dtsi file */
|
|
|
reg = <0x01000000 0x100000>;
|
|
|
- clocks = <&ccu CLK_DE>,
|
|
|
- <&ccu CLK_BUS_DE>;
|
|
|
- clock-names = "mod",
|
|
|
- "bus";
|
|
|
+ clocks = <&ccu CLK_BUS_DE>,
|
|
|
+ <&ccu CLK_DE>;
|
|
|
+ clock-names = "bus",
|
|
|
+ "mod";
|
|
|
resets = <&ccu RST_BUS_DE>;
|
|
|
#clock-cells = <1>;
|
|
|
#reset-cells = <1>;
|
|
@@ -152,12 +147,6 @@
|
|
|
};
|
|
|
};
|
|
|
|
|
|
- syscon: syscon@1c00000 {
|
|
|
- compatible = "allwinner,sun8i-h3-system-controller",
|
|
|
- "syscon";
|
|
|
- reg = <0x01c00000 0x1000>;
|
|
|
- };
|
|
|
-
|
|
|
dma: dma-controller@1c02000 {
|
|
|
compatible = "allwinner,sun8i-h3-dma";
|
|
|
reg = <0x01c02000 0x1000>;
|
|
@@ -239,6 +228,17 @@
|
|
|
#size-cells = <0>;
|
|
|
};
|
|
|
|
|
|
+ sid: eeprom@1c14000 {
|
|
|
+ /* compatible is in per SoC .dtsi file */
|
|
|
+ reg = <0x1c14000 0x400>;
|
|
|
+ #address-cells = <1>;
|
|
|
+ #size-cells = <1>;
|
|
|
+
|
|
|
+ ths_calibration: thermal-sensor-calibration@34 {
|
|
|
+ reg = <0x34 4>;
|
|
|
+ };
|
|
|
+ };
|
|
|
+
|
|
|
usb_otg: usb@1c19000 {
|
|
|
compatible = "allwinner,sun8i-h3-musb";
|
|
|
reg = <0x01c19000 0x400>;
|
|
@@ -249,6 +249,7 @@
|
|
|
phys = <&usbphy 0>;
|
|
|
phy-names = "usb";
|
|
|
extcon = <&usbphy 0>;
|
|
|
+ dr_mode = "otg";
|
|
|
status = "disabled";
|
|
|
};
|
|
|
|
|
@@ -375,7 +376,7 @@
|
|
|
ccu: clock@1c20000 {
|
|
|
/* compatible is in per SoC .dtsi file */
|
|
|
reg = <0x01c20000 0x400>;
|
|
|
- clocks = <&osc24M>, <&osc32k>;
|
|
|
+ clocks = <&osc24M>, <&rtc 0>;
|
|
|
clock-names = "hosc", "losc";
|
|
|
#clock-cells = <1>;
|
|
|
#reset-cells = <1>;
|
|
@@ -386,14 +387,21 @@
|
|
|
reg = <0x01c20800 0x400>;
|
|
|
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
- clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>;
|
|
|
+ clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&rtc 0>;
|
|
|
clock-names = "apb", "hosc", "losc";
|
|
|
gpio-controller;
|
|
|
#gpio-cells = <3>;
|
|
|
interrupt-controller;
|
|
|
#interrupt-cells = <3>;
|
|
|
|
|
|
- emac_rgmii_pins: emac0 {
|
|
|
+ csi_pins: csi-pins {
|
|
|
+ pins = "PE0", "PE2", "PE3", "PE4", "PE5",
|
|
|
+ "PE6", "PE7", "PE8", "PE9", "PE10",
|
|
|
+ "PE11";
|
|
|
+ function = "csi";
|
|
|
+ };
|
|
|
+
|
|
|
+ emac_rgmii_pins: emac-rgmii-pins {
|
|
|
pins = "PD0", "PD1", "PD2", "PD3", "PD4",
|
|
|
"PD5", "PD7", "PD8", "PD9", "PD10",
|
|
|
"PD12", "PD13", "PD15", "PD16", "PD17";
|
|
@@ -401,22 +409,22 @@
|
|
|
drive-strength = <40>;
|
|
|
};
|
|
|
|
|
|
- i2c0_pins: i2c0 {
|
|
|
+ i2c0_pins: i2c0-pins {
|
|
|
pins = "PA11", "PA12";
|
|
|
function = "i2c0";
|
|
|
};
|
|
|
|
|
|
- i2c1_pins: i2c1 {
|
|
|
+ i2c1_pins: i2c1-pins {
|
|
|
pins = "PA18", "PA19";
|
|
|
function = "i2c1";
|
|
|
};
|
|
|
|
|
|
- i2c2_pins: i2c2 {
|
|
|
+ i2c2_pins: i2c2-pins {
|
|
|
pins = "PE12", "PE13";
|
|
|
function = "i2c2";
|
|
|
};
|
|
|
|
|
|
- mmc0_pins: mmc0 {
|
|
|
+ mmc0_pins: mmc0-pins {
|
|
|
pins = "PF0", "PF1", "PF2", "PF3",
|
|
|
"PF4", "PF5";
|
|
|
function = "mmc0";
|
|
@@ -424,7 +432,7 @@
|
|
|
bias-pull-up;
|
|
|
};
|
|
|
|
|
|
- mmc1_pins: mmc1 {
|
|
|
+ mmc1_pins: mmc1-pins {
|
|
|
pins = "PG0", "PG1", "PG2", "PG3",
|
|
|
"PG4", "PG5";
|
|
|
function = "mmc1";
|
|
@@ -432,7 +440,7 @@
|
|
|
bias-pull-up;
|
|
|
};
|
|
|
|
|
|
- mmc2_8bit_pins: mmc2_8bit {
|
|
|
+ mmc2_8bit_pins: mmc2-8bit-pins {
|
|
|
pins = "PC5", "PC6", "PC8",
|
|
|
"PC9", "PC10", "PC11",
|
|
|
"PC12", "PC13", "PC14",
|
|
@@ -442,54 +450,59 @@
|
|
|
bias-pull-up;
|
|
|
};
|
|
|
|
|
|
- spdif_tx_pins_a: spdif {
|
|
|
+ spdif_tx_pin: spdif-tx-pin {
|
|
|
pins = "PA17";
|
|
|
function = "spdif";
|
|
|
};
|
|
|
|
|
|
- spi0_pins: spi0 {
|
|
|
+ spi0_pins: spi0-pins {
|
|
|
pins = "PC0", "PC1", "PC2", "PC3";
|
|
|
function = "spi0";
|
|
|
};
|
|
|
|
|
|
- spi1_pins: spi1 {
|
|
|
+ spi1_pins: spi1-pins {
|
|
|
pins = "PA15", "PA16", "PA14", "PA13";
|
|
|
function = "spi1";
|
|
|
};
|
|
|
|
|
|
- uart0_pins_a: uart0 {
|
|
|
+ uart0_pa_pins: uart0-pa-pins {
|
|
|
pins = "PA4", "PA5";
|
|
|
function = "uart0";
|
|
|
};
|
|
|
|
|
|
- uart1_pins: uart1 {
|
|
|
+ uart1_pins: uart1-pins {
|
|
|
pins = "PG6", "PG7";
|
|
|
function = "uart1";
|
|
|
};
|
|
|
|
|
|
- uart1_rts_cts_pins: uart1_rts_cts {
|
|
|
+ uart1_rts_cts_pins: uart1-rts-cts-pins {
|
|
|
pins = "PG8", "PG9";
|
|
|
function = "uart1";
|
|
|
};
|
|
|
|
|
|
- uart2_pins: uart2 {
|
|
|
+ uart2_pins: uart2-pins {
|
|
|
pins = "PA0", "PA1";
|
|
|
function = "uart2";
|
|
|
};
|
|
|
|
|
|
- uart3_pins: uart3 {
|
|
|
+ uart2_rts_cts_pins: uart2-rts-cts-pins {
|
|
|
+ pins = "PA2", "PA3";
|
|
|
+ function = "uart2";
|
|
|
+ };
|
|
|
+
|
|
|
+ uart3_pins: uart3-pins {
|
|
|
pins = "PA13", "PA14";
|
|
|
function = "uart3";
|
|
|
};
|
|
|
|
|
|
- uart3_rts_cts_pins: uart3_rts_cts {
|
|
|
+ uart3_rts_cts_pins: uart3-rts-cts-pins {
|
|
|
pins = "PA15", "PA16";
|
|
|
function = "uart3";
|
|
|
};
|
|
|
};
|
|
|
|
|
|
timer@1c20c00 {
|
|
|
- compatible = "allwinner,sun4i-a10-timer";
|
|
|
+ compatible = "allwinner,sun8i-a23-timer";
|
|
|
reg = <0x01c20c00 0xa0>;
|
|
|
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
<GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
|
|
@@ -543,6 +556,14 @@
|
|
|
};
|
|
|
};
|
|
|
|
|
|
+ mbus: dram-controller@1c62000 {
|
|
|
+ compatible = "allwinner,sun8i-h3-mbus";
|
|
|
+ reg = <0x01c62000 0x1000>;
|
|
|
+ clocks = <&ccu CLK_MBUS>;
|
|
|
+ dma-ranges = <0x00000000 0x40000000 0xc0000000>;
|
|
|
+ #interconnect-cells = <1>;
|
|
|
+ };
|
|
|
+
|
|
|
spi0: spi@1c68000 {
|
|
|
compatible = "allwinner,sun8i-h3-spi";
|
|
|
reg = <0x01c68000 0x1000>;
|
|
@@ -579,6 +600,7 @@
|
|
|
compatible = "allwinner,sun6i-a31-wdt";
|
|
|
reg = <0x01c20ca0 0x20>;
|
|
|
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
+ clocks = <&osc24M>;
|
|
|
};
|
|
|
|
|
|
spdif: spdif@1c21000 {
|
|
@@ -744,6 +766,20 @@
|
|
|
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
|
|
|
};
|
|
|
|
|
|
+ csi: camera@1cb0000 {
|
|
|
+ compatible = "allwinner,sun8i-h3-csi";
|
|
|
+ reg = <0x01cb0000 0x1000>;
|
|
|
+ interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
+ clocks = <&ccu CLK_BUS_CSI>,
|
|
|
+ <&ccu CLK_CSI_SCLK>,
|
|
|
+ <&ccu CLK_DRAM_CSI>;
|
|
|
+ clock-names = "bus", "mod", "ram";
|
|
|
+ resets = <&ccu RST_BUS_CSI>;
|
|
|
+ pinctrl-names = "default";
|
|
|
+ pinctrl-0 = <&csi_pins>;
|
|
|
+ status = "disabled";
|
|
|
+ };
|
|
|
+
|
|
|
hdmi: hdmi@1ee0000 {
|
|
|
compatible = "allwinner,sun8i-h3-dw-hdmi",
|
|
|
"allwinner,sun8i-a83t-dw-hdmi";
|
|
@@ -756,7 +792,7 @@
|
|
|
resets = <&ccu RST_BUS_HDMI1>;
|
|
|
reset-names = "ctrl";
|
|
|
phys = <&hdmi_phy>;
|
|
|
- phy-names = "hdmi-phy";
|
|
|
+ phy-names = "phy";
|
|
|
status = "disabled";
|
|
|
|
|
|
ports {
|
|
@@ -781,7 +817,7 @@
|
|
|
compatible = "allwinner,sun8i-h3-hdmi-phy";
|
|
|
reg = <0x01ef0000 0x10000>;
|
|
|
clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>,
|
|
|
- <&ccu 6>;
|
|
|
+ <&ccu CLK_PLL_VIDEO>;
|
|
|
clock-names = "bus", "mod", "pll-0";
|
|
|
resets = <&ccu RST_BUS_HDMI0>;
|
|
|
reset-names = "phy";
|
|
@@ -789,17 +825,20 @@
|
|
|
};
|
|
|
|
|
|
rtc: rtc@1f00000 {
|
|
|
- compatible = "allwinner,sun6i-a31-rtc";
|
|
|
- reg = <0x01f00000 0x54>;
|
|
|
+ /* compatible is in per SoC .dtsi file */
|
|
|
+ reg = <0x01f00000 0x400>;
|
|
|
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
+ clock-output-names = "osc32k", "osc32k-out", "iosc";
|
|
|
+ clocks = <&osc32k>;
|
|
|
+ #clock-cells = <1>;
|
|
|
};
|
|
|
|
|
|
r_ccu: clock@1f01400 {
|
|
|
compatible = "allwinner,sun8i-h3-r-ccu";
|
|
|
reg = <0x01f01400 0x100>;
|
|
|
- clocks = <&osc24M>, <&osc32k>, <&iosc>,
|
|
|
- <&ccu 9>;
|
|
|
+ clocks = <&osc24M>, <&rtc 0>, <&rtc 2>,
|
|
|
+ <&ccu CLK_PLL_PERIPH0>;
|
|
|
clock-names = "hosc", "losc", "iosc", "pll-periph";
|
|
|
#clock-cells = <1>;
|
|
|
#reset-cells = <1>;
|
|
@@ -811,12 +850,12 @@
|
|
|
};
|
|
|
|
|
|
ir: ir@1f02000 {
|
|
|
- compatible = "allwinner,sun5i-a13-ir";
|
|
|
+ compatible = "allwinner,sun6i-a31-ir";
|
|
|
clocks = <&r_ccu CLK_APB0_IR>, <&r_ccu CLK_IR>;
|
|
|
clock-names = "apb", "ir";
|
|
|
resets = <&r_ccu RST_APB0_IR>;
|
|
|
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
- reg = <0x01f02000 0x40>;
|
|
|
+ reg = <0x01f02000 0x400>;
|
|
|
status = "disabled";
|
|
|
};
|
|
|
|
|
@@ -837,19 +876,19 @@
|
|
|
compatible = "allwinner,sun8i-h3-r-pinctrl";
|
|
|
reg = <0x01f02c00 0x400>;
|
|
|
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
- clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>;
|
|
|
+ clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, <&rtc 0>;
|
|
|
clock-names = "apb", "hosc", "losc";
|
|
|
gpio-controller;
|
|
|
#gpio-cells = <3>;
|
|
|
interrupt-controller;
|
|
|
#interrupt-cells = <3>;
|
|
|
|
|
|
- ir_pins_a: ir {
|
|
|
+ r_ir_rx_pin: r-ir-rx-pin {
|
|
|
pins = "PL11";
|
|
|
function = "s_cir_rx";
|
|
|
};
|
|
|
|
|
|
- r_i2c_pins: r-i2c {
|
|
|
+ r_i2c_pins: r-i2c-pins {
|
|
|
pins = "PL0", "PL1";
|
|
|
function = "s_i2c";
|
|
|
};
|