sun50i-h5.dtsi 5.1 KB

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  1. // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  2. // Copyright (C) 2016 ARM Ltd.
  3. #include <sunxi-h3-h5.dtsi>
  4. / {
  5. cpus {
  6. #address-cells = <1>;
  7. #size-cells = <0>;
  8. cpu0: cpu@0 {
  9. compatible = "arm,cortex-a53";
  10. device_type = "cpu";
  11. reg = <0>;
  12. enable-method = "psci";
  13. };
  14. cpu1: cpu@1 {
  15. compatible = "arm,cortex-a53";
  16. device_type = "cpu";
  17. reg = <1>;
  18. enable-method = "psci";
  19. };
  20. cpu2: cpu@2 {
  21. compatible = "arm,cortex-a53";
  22. device_type = "cpu";
  23. reg = <2>;
  24. enable-method = "psci";
  25. };
  26. cpu3: cpu@3 {
  27. compatible = "arm,cortex-a53";
  28. device_type = "cpu";
  29. reg = <3>;
  30. enable-method = "psci";
  31. };
  32. };
  33. pmu {
  34. compatible = "arm,cortex-a53-pmu",
  35. "arm,armv8-pmuv3";
  36. interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
  37. <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
  38. <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
  39. <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
  40. interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
  41. };
  42. psci {
  43. compatible = "arm,psci-0.2";
  44. method = "smc";
  45. };
  46. timer {
  47. compatible = "arm,armv8-timer";
  48. interrupts = <GIC_PPI 13
  49. (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  50. <GIC_PPI 14
  51. (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  52. <GIC_PPI 11
  53. (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  54. <GIC_PPI 10
  55. (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
  56. };
  57. soc {
  58. syscon: system-control@1c00000 {
  59. compatible = "allwinner,sun50i-h5-system-control";
  60. reg = <0x01c00000 0x1000>;
  61. #address-cells = <1>;
  62. #size-cells = <1>;
  63. ranges;
  64. sram_c1: sram@18000 {
  65. compatible = "mmio-sram";
  66. reg = <0x00018000 0x1c000>;
  67. #address-cells = <1>;
  68. #size-cells = <1>;
  69. ranges = <0 0x00018000 0x1c000>;
  70. ve_sram: sram-section@0 {
  71. compatible = "allwinner,sun50i-h5-sram-c1",
  72. "allwinner,sun4i-a10-sram-c1";
  73. reg = <0x000000 0x1c000>;
  74. };
  75. };
  76. };
  77. video-codec@1c0e000 {
  78. compatible = "allwinner,sun50i-h5-video-engine";
  79. reg = <0x01c0e000 0x1000>;
  80. clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>,
  81. <&ccu CLK_DRAM_VE>;
  82. clock-names = "ahb", "mod", "ram";
  83. resets = <&ccu RST_BUS_VE>;
  84. interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
  85. allwinner,sram = <&ve_sram 1>;
  86. };
  87. crypto: crypto@1c15000 {
  88. compatible = "allwinner,sun50i-h5-crypto";
  89. reg = <0x01c15000 0x1000>;
  90. interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
  91. clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>;
  92. clock-names = "bus", "mod";
  93. resets = <&ccu RST_BUS_CE>;
  94. };
  95. mali: gpu@1e80000 {
  96. compatible = "allwinner,sun50i-h5-mali", "arm,mali-450";
  97. reg = <0x01e80000 0x30000>;
  98. /*
  99. * While the datasheet lists an interrupt for the
  100. * PMU, the actual silicon does not have the PMU
  101. * block. Reads all return zero, and writes are
  102. * ignored.
  103. */
  104. interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
  105. <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
  106. <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
  107. <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
  108. <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
  109. <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
  110. <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
  111. <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
  112. <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
  113. <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
  114. <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
  115. <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
  116. interrupt-names = "gp",
  117. "gpmmu",
  118. "pp",
  119. "pp0",
  120. "ppmmu0",
  121. "pp1",
  122. "ppmmu1",
  123. "pp2",
  124. "ppmmu2",
  125. "pp3",
  126. "ppmmu3",
  127. "pmu";
  128. clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>;
  129. clock-names = "bus", "core";
  130. resets = <&ccu RST_BUS_GPU>;
  131. assigned-clocks = <&ccu CLK_GPU>;
  132. assigned-clock-rates = <384000000>;
  133. };
  134. ths: thermal-sensor@1c25000 {
  135. compatible = "allwinner,sun50i-h5-ths";
  136. reg = <0x01c25000 0x400>;
  137. interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
  138. resets = <&ccu RST_BUS_THS>;
  139. clocks = <&ccu CLK_BUS_THS>, <&ccu CLK_THS>;
  140. clock-names = "bus", "mod";
  141. nvmem-cells = <&ths_calibration>;
  142. nvmem-cell-names = "calibration";
  143. #thermal-sensor-cells = <1>;
  144. };
  145. };
  146. thermal-zones {
  147. cpu_thermal: cpu-thermal {
  148. polling-delay-passive = <0>;
  149. polling-delay = <0>;
  150. thermal-sensors = <&ths 0>;
  151. };
  152. gpu_thermal {
  153. polling-delay-passive = <0>;
  154. polling-delay = <0>;
  155. thermal-sensors = <&ths 1>;
  156. };
  157. };
  158. };
  159. &ccu {
  160. compatible = "allwinner,sun50i-h5-ccu";
  161. };
  162. &display_clocks {
  163. compatible = "allwinner,sun50i-h5-de2-clk";
  164. };
  165. &mmc0 {
  166. compatible = "allwinner,sun50i-h5-mmc",
  167. "allwinner,sun50i-a64-mmc";
  168. clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
  169. clock-names = "ahb", "mmc";
  170. };
  171. &mmc1 {
  172. compatible = "allwinner,sun50i-h5-mmc",
  173. "allwinner,sun50i-a64-mmc";
  174. clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
  175. clock-names = "ahb", "mmc";
  176. };
  177. &mmc2 {
  178. compatible = "allwinner,sun50i-h5-emmc",
  179. "allwinner,sun50i-a64-emmc";
  180. clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
  181. clock-names = "ahb", "mmc";
  182. };
  183. &pio {
  184. interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
  185. <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
  186. <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
  187. compatible = "allwinner,sun50i-h5-pinctrl";
  188. };
  189. &rtc {
  190. compatible = "allwinner,sun50i-h5-rtc";
  191. };
  192. &sid {
  193. compatible = "allwinner,sun50i-h5-sid";
  194. };