sunxi-h3-h5.dtsi 23 KB

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  1. /*
  2. * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>
  3. *
  4. * This file is dual-licensed: you can use it either under the terms
  5. * of the GPL or the X11 license, at your option. Note that this dual
  6. * licensing only applies to this file, and not this project as a
  7. * whole.
  8. *
  9. * a) This file is free software; you can redistribute it and/or
  10. * modify it under the terms of the GNU General Public License as
  11. * published by the Free Software Foundation; either version 2 of the
  12. * License, or (at your option) any later version.
  13. *
  14. * This file is distributed in the hope that it will be useful,
  15. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17. * GNU General Public License for more details.
  18. *
  19. * Or, alternatively,
  20. *
  21. * b) Permission is hereby granted, free of charge, to any person
  22. * obtaining a copy of this software and associated documentation
  23. * files (the "Software"), to deal in the Software without
  24. * restriction, including without limitation the rights to use,
  25. * copy, modify, merge, publish, distribute, sublicense, and/or
  26. * sell copies of the Software, and to permit persons to whom the
  27. * Software is furnished to do so, subject to the following
  28. * conditions:
  29. *
  30. * The above copyright notice and this permission notice shall be
  31. * included in all copies or substantial portions of the Software.
  32. *
  33. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35. * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37. * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38. * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40. * OTHER DEALINGS IN THE SOFTWARE.
  41. */
  42. #include <dt-bindings/clock/sun8i-de2.h>
  43. #include <dt-bindings/clock/sun8i-h3-ccu.h>
  44. #include <dt-bindings/clock/sun8i-r-ccu.h>
  45. #include <dt-bindings/interrupt-controller/arm-gic.h>
  46. #include <dt-bindings/reset/sun8i-de2.h>
  47. #include <dt-bindings/reset/sun8i-h3-ccu.h>
  48. #include <dt-bindings/reset/sun8i-r-ccu.h>
  49. / {
  50. interrupt-parent = <&gic>;
  51. #address-cells = <1>;
  52. #size-cells = <1>;
  53. chosen {
  54. #address-cells = <1>;
  55. #size-cells = <1>;
  56. ranges;
  57. framebuffer-hdmi {
  58. compatible = "allwinner,simple-framebuffer",
  59. "simple-framebuffer";
  60. allwinner,pipeline = "mixer0-lcd0-hdmi";
  61. clocks = <&display_clocks CLK_MIXER0>,
  62. <&ccu CLK_TCON0>, <&ccu CLK_HDMI>;
  63. status = "disabled";
  64. };
  65. framebuffer-tve {
  66. compatible = "allwinner,simple-framebuffer",
  67. "simple-framebuffer";
  68. allwinner,pipeline = "mixer1-lcd1-tve";
  69. clocks = <&display_clocks CLK_MIXER1>,
  70. <&ccu CLK_TVE>;
  71. status = "disabled";
  72. };
  73. };
  74. clocks {
  75. #address-cells = <1>;
  76. #size-cells = <1>;
  77. ranges;
  78. osc24M: osc24M_clk {
  79. #clock-cells = <0>;
  80. compatible = "fixed-clock";
  81. clock-frequency = <24000000>;
  82. clock-accuracy = <50000>;
  83. clock-output-names = "osc24M";
  84. };
  85. osc32k: osc32k_clk {
  86. #clock-cells = <0>;
  87. compatible = "fixed-clock";
  88. clock-frequency = <32768>;
  89. clock-accuracy = <50000>;
  90. clock-output-names = "ext_osc32k";
  91. };
  92. };
  93. de: display-engine {
  94. compatible = "allwinner,sun8i-h3-display-engine";
  95. allwinner,pipelines = <&mixer0>;
  96. status = "disabled";
  97. };
  98. soc {
  99. compatible = "simple-bus";
  100. #address-cells = <1>;
  101. #size-cells = <1>;
  102. dma-ranges;
  103. ranges;
  104. display_clocks: clock@1000000 {
  105. /* compatible is in per SoC .dtsi file */
  106. reg = <0x01000000 0x100000>;
  107. clocks = <&ccu CLK_BUS_DE>,
  108. <&ccu CLK_DE>;
  109. clock-names = "bus",
  110. "mod";
  111. resets = <&ccu RST_BUS_DE>;
  112. #clock-cells = <1>;
  113. #reset-cells = <1>;
  114. };
  115. mixer0: mixer@1100000 {
  116. compatible = "allwinner,sun8i-h3-de2-mixer-0";
  117. reg = <0x01100000 0x100000>;
  118. clocks = <&display_clocks CLK_BUS_MIXER0>,
  119. <&display_clocks CLK_MIXER0>;
  120. clock-names = "bus",
  121. "mod";
  122. resets = <&display_clocks RST_MIXER0>;
  123. ports {
  124. #address-cells = <1>;
  125. #size-cells = <0>;
  126. mixer0_out: port@1 {
  127. reg = <1>;
  128. mixer0_out_tcon0: endpoint {
  129. remote-endpoint = <&tcon0_in_mixer0>;
  130. };
  131. };
  132. };
  133. };
  134. dma: dma-controller@1c02000 {
  135. compatible = "allwinner,sun8i-h3-dma";
  136. reg = <0x01c02000 0x1000>;
  137. interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
  138. clocks = <&ccu CLK_BUS_DMA>;
  139. resets = <&ccu RST_BUS_DMA>;
  140. #dma-cells = <1>;
  141. };
  142. tcon0: lcd-controller@1c0c000 {
  143. compatible = "allwinner,sun8i-h3-tcon-tv",
  144. "allwinner,sun8i-a83t-tcon-tv";
  145. reg = <0x01c0c000 0x1000>;
  146. interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
  147. clocks = <&ccu CLK_BUS_TCON0>, <&ccu CLK_TCON0>;
  148. clock-names = "ahb", "tcon-ch1";
  149. resets = <&ccu RST_BUS_TCON0>;
  150. reset-names = "lcd";
  151. ports {
  152. #address-cells = <1>;
  153. #size-cells = <0>;
  154. tcon0_in: port@0 {
  155. reg = <0>;
  156. tcon0_in_mixer0: endpoint {
  157. remote-endpoint = <&mixer0_out_tcon0>;
  158. };
  159. };
  160. tcon0_out: port@1 {
  161. #address-cells = <1>;
  162. #size-cells = <0>;
  163. reg = <1>;
  164. tcon0_out_hdmi: endpoint@1 {
  165. reg = <1>;
  166. remote-endpoint = <&hdmi_in_tcon0>;
  167. };
  168. };
  169. };
  170. };
  171. mmc0: mmc@1c0f000 {
  172. /* compatible and clocks are in per SoC .dtsi file */
  173. reg = <0x01c0f000 0x1000>;
  174. pinctrl-names = "default";
  175. pinctrl-0 = <&mmc0_pins>;
  176. resets = <&ccu RST_BUS_MMC0>;
  177. reset-names = "ahb";
  178. interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
  179. status = "disabled";
  180. #address-cells = <1>;
  181. #size-cells = <0>;
  182. };
  183. mmc1: mmc@1c10000 {
  184. /* compatible and clocks are in per SoC .dtsi file */
  185. reg = <0x01c10000 0x1000>;
  186. pinctrl-names = "default";
  187. pinctrl-0 = <&mmc1_pins>;
  188. resets = <&ccu RST_BUS_MMC1>;
  189. reset-names = "ahb";
  190. interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
  191. status = "disabled";
  192. #address-cells = <1>;
  193. #size-cells = <0>;
  194. };
  195. mmc2: mmc@1c11000 {
  196. /* compatible and clocks are in per SoC .dtsi file */
  197. reg = <0x01c11000 0x1000>;
  198. resets = <&ccu RST_BUS_MMC2>;
  199. reset-names = "ahb";
  200. interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
  201. status = "disabled";
  202. #address-cells = <1>;
  203. #size-cells = <0>;
  204. };
  205. sid: eeprom@1c14000 {
  206. /* compatible is in per SoC .dtsi file */
  207. reg = <0x1c14000 0x400>;
  208. #address-cells = <1>;
  209. #size-cells = <1>;
  210. ths_calibration: thermal-sensor-calibration@34 {
  211. reg = <0x34 4>;
  212. };
  213. };
  214. usb_otg: usb@1c19000 {
  215. compatible = "allwinner,sun8i-h3-musb";
  216. reg = <0x01c19000 0x400>;
  217. clocks = <&ccu CLK_BUS_OTG>;
  218. resets = <&ccu RST_BUS_OTG>;
  219. interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
  220. interrupt-names = "mc";
  221. phys = <&usbphy 0>;
  222. phy-names = "usb";
  223. extcon = <&usbphy 0>;
  224. dr_mode = "otg";
  225. status = "disabled";
  226. };
  227. usbphy: phy@1c19400 {
  228. compatible = "allwinner,sun8i-h3-usb-phy";
  229. reg = <0x01c19400 0x2c>,
  230. <0x01c1a800 0x4>,
  231. <0x01c1b800 0x4>,
  232. <0x01c1c800 0x4>,
  233. <0x01c1d800 0x4>;
  234. reg-names = "phy_ctrl",
  235. "pmu0",
  236. "pmu1",
  237. "pmu2",
  238. "pmu3";
  239. clocks = <&ccu CLK_USB_PHY0>,
  240. <&ccu CLK_USB_PHY1>,
  241. <&ccu CLK_USB_PHY2>,
  242. <&ccu CLK_USB_PHY3>;
  243. clock-names = "usb0_phy",
  244. "usb1_phy",
  245. "usb2_phy",
  246. "usb3_phy";
  247. resets = <&ccu RST_USB_PHY0>,
  248. <&ccu RST_USB_PHY1>,
  249. <&ccu RST_USB_PHY2>,
  250. <&ccu RST_USB_PHY3>;
  251. reset-names = "usb0_reset",
  252. "usb1_reset",
  253. "usb2_reset",
  254. "usb3_reset";
  255. status = "disabled";
  256. #phy-cells = <1>;
  257. };
  258. ehci0: usb@1c1a000 {
  259. compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
  260. reg = <0x01c1a000 0x100>;
  261. interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
  262. clocks = <&ccu CLK_BUS_EHCI0>, <&ccu CLK_BUS_OHCI0>;
  263. resets = <&ccu RST_BUS_EHCI0>, <&ccu RST_BUS_OHCI0>;
  264. status = "disabled";
  265. };
  266. ohci0: usb@1c1a400 {
  267. compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
  268. reg = <0x01c1a400 0x100>;
  269. interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
  270. clocks = <&ccu CLK_BUS_EHCI0>, <&ccu CLK_BUS_OHCI0>,
  271. <&ccu CLK_USB_OHCI0>;
  272. resets = <&ccu RST_BUS_EHCI0>, <&ccu RST_BUS_OHCI0>;
  273. status = "disabled";
  274. };
  275. ehci1: usb@1c1b000 {
  276. compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
  277. reg = <0x01c1b000 0x100>;
  278. interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
  279. clocks = <&ccu CLK_BUS_EHCI1>, <&ccu CLK_BUS_OHCI1>;
  280. resets = <&ccu RST_BUS_EHCI1>, <&ccu RST_BUS_OHCI1>;
  281. phys = <&usbphy 1>;
  282. phy-names = "usb";
  283. status = "disabled";
  284. };
  285. ohci1: usb@1c1b400 {
  286. compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
  287. reg = <0x01c1b400 0x100>;
  288. interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
  289. clocks = <&ccu CLK_BUS_EHCI1>, <&ccu CLK_BUS_OHCI1>,
  290. <&ccu CLK_USB_OHCI1>;
  291. resets = <&ccu RST_BUS_EHCI1>, <&ccu RST_BUS_OHCI1>;
  292. phys = <&usbphy 1>;
  293. phy-names = "usb";
  294. status = "disabled";
  295. };
  296. ehci2: usb@1c1c000 {
  297. compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
  298. reg = <0x01c1c000 0x100>;
  299. interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
  300. clocks = <&ccu CLK_BUS_EHCI2>, <&ccu CLK_BUS_OHCI2>;
  301. resets = <&ccu RST_BUS_EHCI2>, <&ccu RST_BUS_OHCI2>;
  302. phys = <&usbphy 2>;
  303. phy-names = "usb";
  304. status = "disabled";
  305. };
  306. ohci2: usb@1c1c400 {
  307. compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
  308. reg = <0x01c1c400 0x100>;
  309. interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
  310. clocks = <&ccu CLK_BUS_EHCI2>, <&ccu CLK_BUS_OHCI2>,
  311. <&ccu CLK_USB_OHCI2>;
  312. resets = <&ccu RST_BUS_EHCI2>, <&ccu RST_BUS_OHCI2>;
  313. phys = <&usbphy 2>;
  314. phy-names = "usb";
  315. status = "disabled";
  316. };
  317. ehci3: usb@1c1d000 {
  318. compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
  319. reg = <0x01c1d000 0x100>;
  320. interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
  321. clocks = <&ccu CLK_BUS_EHCI3>, <&ccu CLK_BUS_OHCI3>;
  322. resets = <&ccu RST_BUS_EHCI3>, <&ccu RST_BUS_OHCI3>;
  323. phys = <&usbphy 3>;
  324. phy-names = "usb";
  325. status = "disabled";
  326. };
  327. ohci3: usb@1c1d400 {
  328. compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
  329. reg = <0x01c1d400 0x100>;
  330. interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
  331. clocks = <&ccu CLK_BUS_EHCI3>, <&ccu CLK_BUS_OHCI3>,
  332. <&ccu CLK_USB_OHCI3>;
  333. resets = <&ccu RST_BUS_EHCI3>, <&ccu RST_BUS_OHCI3>;
  334. phys = <&usbphy 3>;
  335. phy-names = "usb";
  336. status = "disabled";
  337. };
  338. ccu: clock@1c20000 {
  339. /* compatible is in per SoC .dtsi file */
  340. reg = <0x01c20000 0x400>;
  341. clocks = <&osc24M>, <&rtc 0>;
  342. clock-names = "hosc", "losc";
  343. #clock-cells = <1>;
  344. #reset-cells = <1>;
  345. };
  346. pio: pinctrl@1c20800 {
  347. /* compatible is in per SoC .dtsi file */
  348. reg = <0x01c20800 0x400>;
  349. interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
  350. <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
  351. clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&rtc 0>;
  352. clock-names = "apb", "hosc", "losc";
  353. gpio-controller;
  354. #gpio-cells = <3>;
  355. interrupt-controller;
  356. #interrupt-cells = <3>;
  357. csi_pins: csi-pins {
  358. pins = "PE0", "PE2", "PE3", "PE4", "PE5",
  359. "PE6", "PE7", "PE8", "PE9", "PE10",
  360. "PE11";
  361. function = "csi";
  362. };
  363. emac_rgmii_pins: emac-rgmii-pins {
  364. pins = "PD0", "PD1", "PD2", "PD3", "PD4",
  365. "PD5", "PD7", "PD8", "PD9", "PD10",
  366. "PD12", "PD13", "PD15", "PD16", "PD17";
  367. function = "emac";
  368. drive-strength = <40>;
  369. };
  370. i2c0_pins: i2c0-pins {
  371. pins = "PA11", "PA12";
  372. function = "i2c0";
  373. };
  374. i2c1_pins: i2c1-pins {
  375. pins = "PA18", "PA19";
  376. function = "i2c1";
  377. };
  378. i2c2_pins: i2c2-pins {
  379. pins = "PE12", "PE13";
  380. function = "i2c2";
  381. };
  382. mmc0_pins: mmc0-pins {
  383. pins = "PF0", "PF1", "PF2", "PF3",
  384. "PF4", "PF5";
  385. function = "mmc0";
  386. drive-strength = <30>;
  387. bias-pull-up;
  388. };
  389. mmc1_pins: mmc1-pins {
  390. pins = "PG0", "PG1", "PG2", "PG3",
  391. "PG4", "PG5";
  392. function = "mmc1";
  393. drive-strength = <30>;
  394. bias-pull-up;
  395. };
  396. mmc2_8bit_pins: mmc2-8bit-pins {
  397. pins = "PC5", "PC6", "PC8",
  398. "PC9", "PC10", "PC11",
  399. "PC12", "PC13", "PC14",
  400. "PC15", "PC16";
  401. function = "mmc2";
  402. drive-strength = <30>;
  403. bias-pull-up;
  404. };
  405. spdif_tx_pin: spdif-tx-pin {
  406. pins = "PA17";
  407. function = "spdif";
  408. };
  409. spi0_pins: spi0-pins {
  410. pins = "PC0", "PC1", "PC2", "PC3";
  411. function = "spi0";
  412. };
  413. spi1_pins: spi1-pins {
  414. pins = "PA15", "PA16", "PA14", "PA13";
  415. function = "spi1";
  416. };
  417. uart0_pa_pins: uart0-pa-pins {
  418. pins = "PA4", "PA5";
  419. function = "uart0";
  420. };
  421. uart1_pins: uart1-pins {
  422. pins = "PG6", "PG7";
  423. function = "uart1";
  424. };
  425. uart1_rts_cts_pins: uart1-rts-cts-pins {
  426. pins = "PG8", "PG9";
  427. function = "uart1";
  428. };
  429. uart2_pins: uart2-pins {
  430. pins = "PA0", "PA1";
  431. function = "uart2";
  432. };
  433. uart2_rts_cts_pins: uart2-rts-cts-pins {
  434. pins = "PA2", "PA3";
  435. function = "uart2";
  436. };
  437. uart3_pins: uart3-pins {
  438. pins = "PA13", "PA14";
  439. function = "uart3";
  440. };
  441. uart3_rts_cts_pins: uart3-rts-cts-pins {
  442. pins = "PA15", "PA16";
  443. function = "uart3";
  444. };
  445. };
  446. timer@1c20c00 {
  447. compatible = "allwinner,sun8i-a23-timer";
  448. reg = <0x01c20c00 0xa0>;
  449. interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
  450. <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
  451. clocks = <&osc24M>;
  452. };
  453. emac: ethernet@1c30000 {
  454. compatible = "allwinner,sun8i-h3-emac";
  455. syscon = <&syscon>;
  456. reg = <0x01c30000 0x10000>;
  457. interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
  458. interrupt-names = "macirq";
  459. resets = <&ccu RST_BUS_EMAC>;
  460. reset-names = "stmmaceth";
  461. clocks = <&ccu CLK_BUS_EMAC>;
  462. clock-names = "stmmaceth";
  463. status = "disabled";
  464. mdio: mdio {
  465. #address-cells = <1>;
  466. #size-cells = <0>;
  467. compatible = "snps,dwmac-mdio";
  468. };
  469. mdio-mux {
  470. compatible = "allwinner,sun8i-h3-mdio-mux";
  471. #address-cells = <1>;
  472. #size-cells = <0>;
  473. mdio-parent-bus = <&mdio>;
  474. /* Only one MDIO is usable at the time */
  475. internal_mdio: mdio@1 {
  476. compatible = "allwinner,sun8i-h3-mdio-internal";
  477. reg = <1>;
  478. #address-cells = <1>;
  479. #size-cells = <0>;
  480. int_mii_phy: ethernet-phy@1 {
  481. compatible = "ethernet-phy-ieee802.3-c22";
  482. reg = <1>;
  483. clocks = <&ccu CLK_BUS_EPHY>;
  484. resets = <&ccu RST_BUS_EPHY>;
  485. };
  486. };
  487. external_mdio: mdio@2 {
  488. reg = <2>;
  489. #address-cells = <1>;
  490. #size-cells = <0>;
  491. };
  492. };
  493. };
  494. mbus: dram-controller@1c62000 {
  495. compatible = "allwinner,sun8i-h3-mbus";
  496. reg = <0x01c62000 0x1000>;
  497. clocks = <&ccu CLK_MBUS>;
  498. dma-ranges = <0x00000000 0x40000000 0xc0000000>;
  499. #interconnect-cells = <1>;
  500. };
  501. spi0: spi@1c68000 {
  502. compatible = "allwinner,sun8i-h3-spi";
  503. reg = <0x01c68000 0x1000>;
  504. interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
  505. clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
  506. clock-names = "ahb", "mod";
  507. dmas = <&dma 23>, <&dma 23>;
  508. dma-names = "rx", "tx";
  509. pinctrl-names = "default";
  510. pinctrl-0 = <&spi0_pins>;
  511. resets = <&ccu RST_BUS_SPI0>;
  512. status = "disabled";
  513. #address-cells = <1>;
  514. #size-cells = <0>;
  515. };
  516. spi1: spi@1c69000 {
  517. compatible = "allwinner,sun8i-h3-spi";
  518. reg = <0x01c69000 0x1000>;
  519. interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
  520. clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
  521. clock-names = "ahb", "mod";
  522. dmas = <&dma 24>, <&dma 24>;
  523. dma-names = "rx", "tx";
  524. pinctrl-names = "default";
  525. pinctrl-0 = <&spi1_pins>;
  526. resets = <&ccu RST_BUS_SPI1>;
  527. status = "disabled";
  528. #address-cells = <1>;
  529. #size-cells = <0>;
  530. };
  531. wdt0: watchdog@1c20ca0 {
  532. compatible = "allwinner,sun6i-a31-wdt";
  533. reg = <0x01c20ca0 0x20>;
  534. interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
  535. clocks = <&osc24M>;
  536. };
  537. spdif: spdif@1c21000 {
  538. #sound-dai-cells = <0>;
  539. compatible = "allwinner,sun8i-h3-spdif";
  540. reg = <0x01c21000 0x400>;
  541. interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
  542. clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>;
  543. resets = <&ccu RST_BUS_SPDIF>;
  544. clock-names = "apb", "spdif";
  545. dmas = <&dma 2>;
  546. dma-names = "tx";
  547. status = "disabled";
  548. };
  549. pwm: pwm@1c21400 {
  550. compatible = "allwinner,sun8i-h3-pwm";
  551. reg = <0x01c21400 0x8>;
  552. clocks = <&osc24M>;
  553. #pwm-cells = <3>;
  554. status = "disabled";
  555. };
  556. i2s0: i2s@1c22000 {
  557. #sound-dai-cells = <0>;
  558. compatible = "allwinner,sun8i-h3-i2s";
  559. reg = <0x01c22000 0x400>;
  560. interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
  561. clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>;
  562. clock-names = "apb", "mod";
  563. dmas = <&dma 3>, <&dma 3>;
  564. resets = <&ccu RST_BUS_I2S0>;
  565. dma-names = "rx", "tx";
  566. status = "disabled";
  567. };
  568. i2s1: i2s@1c22400 {
  569. #sound-dai-cells = <0>;
  570. compatible = "allwinner,sun8i-h3-i2s";
  571. reg = <0x01c22400 0x400>;
  572. interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
  573. clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>;
  574. clock-names = "apb", "mod";
  575. dmas = <&dma 4>, <&dma 4>;
  576. resets = <&ccu RST_BUS_I2S1>;
  577. dma-names = "rx", "tx";
  578. status = "disabled";
  579. };
  580. codec: codec@1c22c00 {
  581. #sound-dai-cells = <0>;
  582. compatible = "allwinner,sun8i-h3-codec";
  583. reg = <0x01c22c00 0x400>;
  584. interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
  585. clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>;
  586. clock-names = "apb", "codec";
  587. resets = <&ccu RST_BUS_CODEC>;
  588. dmas = <&dma 15>, <&dma 15>;
  589. dma-names = "rx", "tx";
  590. allwinner,codec-analog-controls = <&codec_analog>;
  591. status = "disabled";
  592. };
  593. uart0: serial@1c28000 {
  594. compatible = "snps,dw-apb-uart";
  595. reg = <0x01c28000 0x400>;
  596. interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
  597. reg-shift = <2>;
  598. reg-io-width = <4>;
  599. clocks = <&ccu CLK_BUS_UART0>;
  600. resets = <&ccu RST_BUS_UART0>;
  601. dmas = <&dma 6>, <&dma 6>;
  602. dma-names = "rx", "tx";
  603. status = "disabled";
  604. };
  605. uart1: serial@1c28400 {
  606. compatible = "snps,dw-apb-uart";
  607. reg = <0x01c28400 0x400>;
  608. interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
  609. reg-shift = <2>;
  610. reg-io-width = <4>;
  611. clocks = <&ccu CLK_BUS_UART1>;
  612. resets = <&ccu RST_BUS_UART1>;
  613. dmas = <&dma 7>, <&dma 7>;
  614. dma-names = "rx", "tx";
  615. status = "disabled";
  616. };
  617. uart2: serial@1c28800 {
  618. compatible = "snps,dw-apb-uart";
  619. reg = <0x01c28800 0x400>;
  620. interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
  621. reg-shift = <2>;
  622. reg-io-width = <4>;
  623. clocks = <&ccu CLK_BUS_UART2>;
  624. resets = <&ccu RST_BUS_UART2>;
  625. dmas = <&dma 8>, <&dma 8>;
  626. dma-names = "rx", "tx";
  627. status = "disabled";
  628. };
  629. uart3: serial@1c28c00 {
  630. compatible = "snps,dw-apb-uart";
  631. reg = <0x01c28c00 0x400>;
  632. interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
  633. reg-shift = <2>;
  634. reg-io-width = <4>;
  635. clocks = <&ccu CLK_BUS_UART3>;
  636. resets = <&ccu RST_BUS_UART3>;
  637. dmas = <&dma 9>, <&dma 9>;
  638. dma-names = "rx", "tx";
  639. status = "disabled";
  640. };
  641. i2c0: i2c@1c2ac00 {
  642. compatible = "allwinner,sun6i-a31-i2c";
  643. reg = <0x01c2ac00 0x400>;
  644. interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
  645. clocks = <&ccu CLK_BUS_I2C0>;
  646. resets = <&ccu RST_BUS_I2C0>;
  647. pinctrl-names = "default";
  648. pinctrl-0 = <&i2c0_pins>;
  649. status = "disabled";
  650. #address-cells = <1>;
  651. #size-cells = <0>;
  652. };
  653. i2c1: i2c@1c2b000 {
  654. compatible = "allwinner,sun6i-a31-i2c";
  655. reg = <0x01c2b000 0x400>;
  656. interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
  657. clocks = <&ccu CLK_BUS_I2C1>;
  658. resets = <&ccu RST_BUS_I2C1>;
  659. pinctrl-names = "default";
  660. pinctrl-0 = <&i2c1_pins>;
  661. status = "disabled";
  662. #address-cells = <1>;
  663. #size-cells = <0>;
  664. };
  665. i2c2: i2c@1c2b400 {
  666. compatible = "allwinner,sun6i-a31-i2c";
  667. reg = <0x01c2b400 0x400>;
  668. interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
  669. clocks = <&ccu CLK_BUS_I2C2>;
  670. resets = <&ccu RST_BUS_I2C2>;
  671. pinctrl-names = "default";
  672. pinctrl-0 = <&i2c2_pins>;
  673. status = "disabled";
  674. #address-cells = <1>;
  675. #size-cells = <0>;
  676. };
  677. gic: interrupt-controller@1c81000 {
  678. compatible = "arm,gic-400";
  679. reg = <0x01c81000 0x1000>,
  680. <0x01c82000 0x2000>,
  681. <0x01c84000 0x2000>,
  682. <0x01c86000 0x2000>;
  683. interrupt-controller;
  684. #interrupt-cells = <3>;
  685. interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
  686. };
  687. csi: camera@1cb0000 {
  688. compatible = "allwinner,sun8i-h3-csi";
  689. reg = <0x01cb0000 0x1000>;
  690. interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
  691. clocks = <&ccu CLK_BUS_CSI>,
  692. <&ccu CLK_CSI_SCLK>,
  693. <&ccu CLK_DRAM_CSI>;
  694. clock-names = "bus", "mod", "ram";
  695. resets = <&ccu RST_BUS_CSI>;
  696. pinctrl-names = "default";
  697. pinctrl-0 = <&csi_pins>;
  698. status = "disabled";
  699. };
  700. hdmi: hdmi@1ee0000 {
  701. compatible = "allwinner,sun8i-h3-dw-hdmi",
  702. "allwinner,sun8i-a83t-dw-hdmi";
  703. reg = <0x01ee0000 0x10000>;
  704. reg-io-width = <1>;
  705. interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
  706. clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>,
  707. <&ccu CLK_HDMI>;
  708. clock-names = "iahb", "isfr", "tmds";
  709. resets = <&ccu RST_BUS_HDMI1>;
  710. reset-names = "ctrl";
  711. phys = <&hdmi_phy>;
  712. phy-names = "phy";
  713. status = "disabled";
  714. ports {
  715. #address-cells = <1>;
  716. #size-cells = <0>;
  717. hdmi_in: port@0 {
  718. reg = <0>;
  719. hdmi_in_tcon0: endpoint {
  720. remote-endpoint = <&tcon0_out_hdmi>;
  721. };
  722. };
  723. hdmi_out: port@1 {
  724. reg = <1>;
  725. };
  726. };
  727. };
  728. hdmi_phy: hdmi-phy@1ef0000 {
  729. compatible = "allwinner,sun8i-h3-hdmi-phy";
  730. reg = <0x01ef0000 0x10000>;
  731. clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>,
  732. <&ccu CLK_PLL_VIDEO>;
  733. clock-names = "bus", "mod", "pll-0";
  734. resets = <&ccu RST_BUS_HDMI0>;
  735. reset-names = "phy";
  736. #phy-cells = <0>;
  737. };
  738. rtc: rtc@1f00000 {
  739. /* compatible is in per SoC .dtsi file */
  740. reg = <0x01f00000 0x400>;
  741. interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
  742. <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
  743. clock-output-names = "osc32k", "osc32k-out", "iosc";
  744. clocks = <&osc32k>;
  745. #clock-cells = <1>;
  746. };
  747. r_ccu: clock@1f01400 {
  748. compatible = "allwinner,sun8i-h3-r-ccu";
  749. reg = <0x01f01400 0x100>;
  750. clocks = <&osc24M>, <&rtc 0>, <&rtc 2>,
  751. <&ccu CLK_PLL_PERIPH0>;
  752. clock-names = "hosc", "losc", "iosc", "pll-periph";
  753. #clock-cells = <1>;
  754. #reset-cells = <1>;
  755. };
  756. codec_analog: codec-analog@1f015c0 {
  757. compatible = "allwinner,sun8i-h3-codec-analog";
  758. reg = <0x01f015c0 0x4>;
  759. };
  760. ir: ir@1f02000 {
  761. compatible = "allwinner,sun6i-a31-ir";
  762. clocks = <&r_ccu CLK_APB0_IR>, <&r_ccu CLK_IR>;
  763. clock-names = "apb", "ir";
  764. resets = <&r_ccu RST_APB0_IR>;
  765. interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
  766. reg = <0x01f02000 0x400>;
  767. status = "disabled";
  768. };
  769. r_i2c: i2c@1f02400 {
  770. compatible = "allwinner,sun6i-a31-i2c";
  771. reg = <0x01f02400 0x400>;
  772. interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
  773. pinctrl-names = "default";
  774. pinctrl-0 = <&r_i2c_pins>;
  775. clocks = <&r_ccu CLK_APB0_I2C>;
  776. resets = <&r_ccu RST_APB0_I2C>;
  777. status = "disabled";
  778. #address-cells = <1>;
  779. #size-cells = <0>;
  780. };
  781. r_pio: pinctrl@1f02c00 {
  782. compatible = "allwinner,sun8i-h3-r-pinctrl";
  783. reg = <0x01f02c00 0x400>;
  784. interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
  785. clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, <&rtc 0>;
  786. clock-names = "apb", "hosc", "losc";
  787. gpio-controller;
  788. #gpio-cells = <3>;
  789. interrupt-controller;
  790. #interrupt-cells = <3>;
  791. r_ir_rx_pin: r-ir-rx-pin {
  792. pins = "PL11";
  793. function = "s_cir_rx";
  794. };
  795. r_i2c_pins: r-i2c-pins {
  796. pins = "PL0", "PL1";
  797. function = "s_i2c";
  798. };
  799. };
  800. };
  801. };