Thomas De Schampheleire 18b8d360bb arch/mips: add (Marvell) Octeon III processor %!s(int64=5) %!d(string=hai) anos
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Config.in cf2b12cbfb arch: drop BR2_GCC_TARGET_CPU_REVISION option %!s(int64=5) %!d(string=hai) anos
Config.in.arc 7e26b8886b arch/Config.in*: fix attributes order %!s(int64=6) %!d(string=hai) anos
Config.in.arm 354781dd96 arch/arm: add an armv8.3a core %!s(int64=5) %!d(string=hai) anos
Config.in.csky d04ea6e4e8 arch: add BR2_READELF_ARCH_NAME hidden config option %!s(int64=7) %!d(string=hai) anos
Config.in.m68k 7e26b8886b arch/Config.in*: fix attributes order %!s(int64=6) %!d(string=hai) anos
Config.in.microblaze d04ea6e4e8 arch: add BR2_READELF_ARCH_NAME hidden config option %!s(int64=7) %!d(string=hai) anos
Config.in.mips 18b8d360bb arch/mips: add (Marvell) Octeon III processor %!s(int64=5) %!d(string=hai) anos
Config.in.nios2 d04ea6e4e8 arch: add BR2_READELF_ARCH_NAME hidden config option %!s(int64=7) %!d(string=hai) anos
Config.in.or1k d04ea6e4e8 arch: add BR2_READELF_ARCH_NAME hidden config option %!s(int64=7) %!d(string=hai) anos
Config.in.powerpc 7e26b8886b arch/Config.in*: fix attributes order %!s(int64=6) %!d(string=hai) anos
Config.in.riscv ae99fa6d64 arch: add support for RISC-V 32-bit (riscv32) architecture %!s(int64=5) %!d(string=hai) anos
Config.in.sh 7e26b8886b arch/Config.in*: fix attributes order %!s(int64=6) %!d(string=hai) anos
Config.in.sparc 7e26b8886b arch/Config.in*: fix attributes order %!s(int64=6) %!d(string=hai) anos
Config.in.x86 7e26b8886b arch/Config.in*: fix attributes order %!s(int64=6) %!d(string=hai) anos
Config.in.xtensa b2b8a3c3e4 arch/Config.in*: re-wrap help text %!s(int64=6) %!d(string=hai) anos
arch.mk cf2b12cbfb arch: drop BR2_GCC_TARGET_CPU_REVISION option %!s(int64=5) %!d(string=hai) anos
arch.mk.riscv ae99fa6d64 arch: add support for RISC-V 32-bit (riscv32) architecture %!s(int64=5) %!d(string=hai) anos
arch.mk.xtensa 01c1889f9f arc/xtensa: store the Xtensa overlay in the per-package DL_DIR %!s(int64=6) %!d(string=hai) anos