Config.in 11 KB

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  1. menu "Target options"
  2. config BR2_ARCH_IS_64
  3. bool
  4. config BR2_KERNEL_64_USERLAND_32
  5. bool
  6. config BR2_SOFT_FLOAT
  7. bool
  8. config BR2_ARCH_HAS_MMU_MANDATORY
  9. bool
  10. config BR2_ARCH_HAS_MMU_OPTIONAL
  11. bool
  12. choice
  13. prompt "Target Architecture"
  14. default BR2_i386
  15. help
  16. Select the target architecture family to build for.
  17. config BR2_arcle
  18. bool "ARC (little endian)"
  19. select BR2_ARCH_HAS_MMU_MANDATORY
  20. help
  21. Synopsys' DesignWare ARC Processor Cores are a family of
  22. 32-bit CPUs that can be used from deeply embedded to high
  23. performance host applications. Little endian.
  24. config BR2_arceb
  25. bool "ARC (big endian)"
  26. select BR2_ARCH_HAS_MMU_MANDATORY
  27. help
  28. Synopsys' DesignWare ARC Processor Cores are a family of
  29. 32-bit CPUs that can be used from deeply embedded to high
  30. performance host applications. Big endian.
  31. config BR2_arm
  32. bool "ARM (little endian)"
  33. # MMU support is set by the subarchitecture file, arch/Config.in.arm
  34. help
  35. ARM is a 32-bit reduced instruction set computer (RISC)
  36. instruction set architecture (ISA) developed by ARM Holdings.
  37. Little endian.
  38. http://www.arm.com/
  39. http://en.wikipedia.org/wiki/ARM
  40. config BR2_armeb
  41. bool "ARM (big endian)"
  42. # MMU support is set by the subarchitecture file, arch/Config.in.arm
  43. help
  44. ARM is a 32-bit reduced instruction set computer (RISC)
  45. instruction set architecture (ISA) developed by ARM Holdings.
  46. Big endian.
  47. http://www.arm.com/
  48. http://en.wikipedia.org/wiki/ARM
  49. config BR2_aarch64
  50. bool "AArch64 (little endian)"
  51. select BR2_ARCH_IS_64
  52. select BR2_ARCH_HAS_MMU_MANDATORY
  53. help
  54. Aarch64 is a 64-bit architecture developed by ARM Holdings.
  55. http://www.arm.com/products/processors/instruction-set-architectures/armv8-architecture.php
  56. http://en.wikipedia.org/wiki/ARM
  57. config BR2_aarch64_be
  58. bool "AArch64 (big endian)"
  59. select BR2_ARCH_IS_64
  60. select BR2_ARCH_HAS_MMU_MANDATORY
  61. help
  62. Aarch64 is a 64-bit architecture developed by ARM Holdings.
  63. http://www.arm.com/products/processors/instruction-set-architectures/armv8-architecture.php
  64. http://en.wikipedia.org/wiki/ARM
  65. config BR2_csky
  66. bool "csky"
  67. select BR2_ARCH_HAS_NO_TOOLCHAIN_BUILDROOT
  68. select BR2_ARCH_HAS_MMU_MANDATORY
  69. help
  70. csky is processor IP from china.
  71. http://www.c-sky.com/
  72. http://www.github.com/c-sky
  73. config BR2_i386
  74. bool "i386"
  75. select BR2_ARCH_HAS_MMU_MANDATORY
  76. help
  77. Intel i386 architecture compatible microprocessor
  78. http://en.wikipedia.org/wiki/I386
  79. config BR2_m68k
  80. bool "m68k"
  81. # MMU support is set by the subarchitecture file, arch/Config.in.m68k
  82. help
  83. Motorola 68000 family microprocessor
  84. http://en.wikipedia.org/wiki/M68k
  85. config BR2_microblazeel
  86. bool "Microblaze AXI (little endian)"
  87. select BR2_ARCH_HAS_MMU_MANDATORY
  88. help
  89. Soft processor core designed for Xilinx FPGAs from Xilinx. AXI
  90. bus based architecture (little endian)
  91. http://www.xilinx.com
  92. http://en.wikipedia.org/wiki/Microblaze
  93. config BR2_microblazebe
  94. bool "Microblaze non-AXI (big endian)"
  95. select BR2_ARCH_HAS_MMU_MANDATORY
  96. help
  97. Soft processor core designed for Xilinx FPGAs from Xilinx. PLB
  98. bus based architecture (non-AXI, big endian)
  99. http://www.xilinx.com
  100. http://en.wikipedia.org/wiki/Microblaze
  101. config BR2_mips
  102. bool "MIPS (big endian)"
  103. select BR2_ARCH_HAS_MMU_MANDATORY
  104. help
  105. MIPS is a RISC microprocessor from MIPS Technologies. Big
  106. endian.
  107. http://www.mips.com/
  108. http://en.wikipedia.org/wiki/MIPS_Technologies
  109. config BR2_mipsel
  110. bool "MIPS (little endian)"
  111. select BR2_ARCH_HAS_MMU_MANDATORY
  112. help
  113. MIPS is a RISC microprocessor from MIPS Technologies. Little
  114. endian.
  115. http://www.mips.com/
  116. http://en.wikipedia.org/wiki/MIPS_Technologies
  117. config BR2_mips64
  118. bool "MIPS64 (big endian)"
  119. select BR2_ARCH_IS_64
  120. select BR2_ARCH_HAS_MMU_MANDATORY
  121. help
  122. MIPS is a RISC microprocessor from MIPS Technologies. Big
  123. endian.
  124. http://www.mips.com/
  125. http://en.wikipedia.org/wiki/MIPS_Technologies
  126. config BR2_mips64el
  127. bool "MIPS64 (little endian)"
  128. select BR2_ARCH_IS_64
  129. select BR2_ARCH_HAS_MMU_MANDATORY
  130. help
  131. MIPS is a RISC microprocessor from MIPS Technologies. Little
  132. endian.
  133. http://www.mips.com/
  134. http://en.wikipedia.org/wiki/MIPS_Technologies
  135. config BR2_nios2
  136. bool "Nios II"
  137. select BR2_ARCH_HAS_MMU_MANDATORY
  138. help
  139. Nios II is a soft core processor from Altera Corporation.
  140. http://www.altera.com/
  141. http://en.wikipedia.org/wiki/Nios_II
  142. config BR2_or1k
  143. bool "OpenRISC"
  144. select BR2_ARCH_HAS_MMU_MANDATORY
  145. help
  146. OpenRISC is a free and open processor for embedded system.
  147. http://openrisc.io
  148. config BR2_powerpc
  149. bool "PowerPC"
  150. select BR2_ARCH_HAS_MMU_MANDATORY
  151. help
  152. PowerPC is a RISC architecture created by Apple-IBM-Motorola
  153. alliance. Big endian.
  154. http://www.power.org/
  155. http://en.wikipedia.org/wiki/Powerpc
  156. config BR2_powerpc64
  157. bool "PowerPC64 (big endian)"
  158. select BR2_ARCH_IS_64
  159. select BR2_ARCH_HAS_MMU_MANDATORY
  160. help
  161. PowerPC is a RISC architecture created by Apple-IBM-Motorola
  162. alliance. Big endian.
  163. http://www.power.org/
  164. http://en.wikipedia.org/wiki/Powerpc
  165. config BR2_powerpc64le
  166. bool "PowerPC64 (little endian)"
  167. select BR2_ARCH_IS_64
  168. select BR2_ARCH_HAS_MMU_MANDATORY
  169. help
  170. PowerPC is a RISC architecture created by Apple-IBM-Motorola
  171. alliance. Little endian.
  172. http://www.power.org/
  173. http://en.wikipedia.org/wiki/Powerpc
  174. config BR2_riscv
  175. bool "RISCV"
  176. select BR2_ARCH_HAS_MMU_MANDATORY
  177. select BR2_ARCH_NEEDS_GCC_AT_LEAST_7
  178. help
  179. RISC-V is an open, free Instruction Set Architecture created
  180. by the UC Berkeley Architecture Research group and supported
  181. and promoted by RISC-V Foundation.
  182. https://riscv.org/
  183. https://en.wikipedia.org/wiki/RISC-V
  184. config BR2_sh
  185. bool "SuperH"
  186. select BR2_ARCH_HAS_MMU_OPTIONAL
  187. help
  188. SuperH (or SH) is a 32-bit reduced instruction set computer
  189. (RISC) instruction set architecture (ISA) developed by
  190. Hitachi.
  191. http://www.hitachi.com/
  192. http://en.wikipedia.org/wiki/SuperH
  193. config BR2_sparc
  194. bool "SPARC"
  195. select BR2_ARCH_HAS_MMU_MANDATORY
  196. help
  197. SPARC (from Scalable Processor Architecture) is a RISC
  198. instruction set architecture (ISA) developed by Sun
  199. Microsystems.
  200. http://www.oracle.com/sun
  201. http://en.wikipedia.org/wiki/Sparc
  202. config BR2_sparc64
  203. bool "SPARC64"
  204. select BR2_ARCH_IS_64
  205. select BR2_ARCH_HAS_MMU_MANDATORY
  206. help
  207. SPARC (from Scalable Processor Architecture) is a RISC
  208. instruction set architecture (ISA) developed by Sun
  209. Microsystems.
  210. http://www.oracle.com/sun
  211. http://en.wikipedia.org/wiki/Sparc
  212. config BR2_x86_64
  213. bool "x86_64"
  214. select BR2_ARCH_IS_64
  215. select BR2_ARCH_HAS_MMU_MANDATORY
  216. help
  217. x86-64 is an extension of the x86 instruction set (Intel i386
  218. architecture compatible microprocessor).
  219. http://en.wikipedia.org/wiki/X86_64
  220. config BR2_xtensa
  221. bool "Xtensa"
  222. # MMU support is set by the subarchitecture file, arch/Config.in.xtensa
  223. help
  224. Xtensa is a Tensilica processor IP architecture.
  225. http://en.wikipedia.org/wiki/Xtensa
  226. http://www.tensilica.com/
  227. endchoice
  228. # For some architectures or specific cores, our internal toolchain
  229. # backend is not suitable (like, missing support in upstream gcc, or
  230. # no ChipCo fork exists...)
  231. config BR2_ARCH_HAS_NO_TOOLCHAIN_BUILDROOT
  232. bool
  233. config BR2_ARCH_HAS_TOOLCHAIN_BUILDROOT
  234. bool
  235. default y if !BR2_ARCH_HAS_NO_TOOLCHAIN_BUILDROOT
  236. # The following symbols are selected by the individual
  237. # Config.in.$ARCH files
  238. config BR2_ARCH_NEEDS_GCC_AT_LEAST_4_8
  239. bool
  240. config BR2_ARCH_NEEDS_GCC_AT_LEAST_4_9
  241. bool
  242. select BR2_ARCH_NEEDS_GCC_AT_LEAST_4_8
  243. config BR2_ARCH_NEEDS_GCC_AT_LEAST_5
  244. bool
  245. select BR2_ARCH_NEEDS_GCC_AT_LEAST_4_9
  246. config BR2_ARCH_NEEDS_GCC_AT_LEAST_6
  247. bool
  248. select BR2_ARCH_NEEDS_GCC_AT_LEAST_5
  249. config BR2_ARCH_NEEDS_GCC_AT_LEAST_7
  250. bool
  251. select BR2_ARCH_NEEDS_GCC_AT_LEAST_6
  252. config BR2_ARCH_NEEDS_GCC_AT_LEAST_8
  253. bool
  254. select BR2_ARCH_NEEDS_GCC_AT_LEAST_7
  255. # The following string values are defined by the individual
  256. # Config.in.$ARCH files
  257. config BR2_ARCH
  258. string
  259. config BR2_ENDIAN
  260. string
  261. config BR2_GCC_TARGET_ARCH
  262. string
  263. config BR2_GCC_TARGET_ABI
  264. string
  265. config BR2_GCC_TARGET_NAN
  266. string
  267. config BR2_GCC_TARGET_FP32_MODE
  268. string
  269. config BR2_GCC_TARGET_CPU
  270. string
  271. # The value of this option will be passed as --with-fpu=<value> when
  272. # building gcc (internal backend) or -mfpu=<value> in the toolchain
  273. # wrapper (external toolchain)
  274. config BR2_GCC_TARGET_FPU
  275. string
  276. # The value of this option will be passed as --with-float=<value> when
  277. # building gcc (internal backend) or -mfloat-abi=<value> in the toolchain
  278. # wrapper (external toolchain)
  279. config BR2_GCC_TARGET_FLOAT_ABI
  280. string
  281. # The value of this option will be passed as --with-mode=<value> when
  282. # building gcc (internal backend) or -m<value> in the toolchain
  283. # wrapper (external toolchain)
  284. config BR2_GCC_TARGET_MODE
  285. string
  286. # Must be selected by binary formats that support shared libraries.
  287. config BR2_BINFMT_SUPPORTS_SHARED
  288. bool
  289. # Must match the name of the architecture from readelf point of view,
  290. # i.e the "Machine:" field of readelf output. See get_machine_name()
  291. # in binutils/readelf.c for the list of possible values.
  292. config BR2_READELF_ARCH_NAME
  293. string
  294. # Set up target binary format
  295. choice
  296. prompt "Target Binary Format"
  297. default BR2_BINFMT_ELF if BR2_USE_MMU
  298. default BR2_BINFMT_FLAT
  299. config BR2_BINFMT_ELF
  300. bool "ELF"
  301. depends on BR2_USE_MMU
  302. select BR2_BINFMT_SUPPORTS_SHARED
  303. help
  304. ELF (Executable and Linkable Format) is a format for libraries
  305. and executables used across different architectures and
  306. operating systems.
  307. config BR2_BINFMT_FLAT
  308. bool "FLAT"
  309. depends on !BR2_USE_MMU
  310. help
  311. FLAT binary is a relatively simple and lightweight executable
  312. format based on the original a.out format. It is widely used
  313. in environment where no MMU is available.
  314. endchoice
  315. # Set up flat binary type
  316. choice
  317. prompt "FLAT Binary type"
  318. default BR2_BINFMT_FLAT_ONE
  319. depends on BR2_BINFMT_FLAT
  320. config BR2_BINFMT_FLAT_ONE
  321. bool "One memory region"
  322. help
  323. All segments are linked into one memory region.
  324. config BR2_BINFMT_FLAT_SHARED
  325. bool "Shared binary"
  326. depends on BR2_m68k
  327. # Even though this really generates shared binaries, there is no libdl
  328. # and dlopen() cannot be used. So packages that require shared
  329. # libraries cannot be built. Therefore, we don't select
  330. # BR2_BINFMT_SUPPORTS_SHARED and therefore force BR2_STATIC_LIBS.
  331. # Although this adds -static to the compilation, that's not a problem
  332. # because the -mid-shared-library option overrides it.
  333. help
  334. Allow to load and link indiviual FLAT binaries at run time.
  335. endchoice
  336. if BR2_arcle || BR2_arceb
  337. source "arch/Config.in.arc"
  338. endif
  339. if BR2_arm || BR2_armeb || BR2_aarch64 || BR2_aarch64_be
  340. source "arch/Config.in.arm"
  341. endif
  342. if BR2_csky
  343. source "arch/Config.in.csky"
  344. endif
  345. if BR2_m68k
  346. source "arch/Config.in.m68k"
  347. endif
  348. if BR2_microblazeel || BR2_microblazebe
  349. source "arch/Config.in.microblaze"
  350. endif
  351. if BR2_mips || BR2_mips64 || BR2_mipsel || BR2_mips64el
  352. source "arch/Config.in.mips"
  353. endif
  354. if BR2_nios2
  355. source "arch/Config.in.nios2"
  356. endif
  357. if BR2_or1k
  358. source "arch/Config.in.or1k"
  359. endif
  360. if BR2_powerpc || BR2_powerpc64 || BR2_powerpc64le
  361. source "arch/Config.in.powerpc"
  362. endif
  363. if BR2_riscv
  364. source "arch/Config.in.riscv"
  365. endif
  366. if BR2_sh
  367. source "arch/Config.in.sh"
  368. endif
  369. if BR2_sparc || BR2_sparc64
  370. source "arch/Config.in.sparc"
  371. endif
  372. if BR2_i386 || BR2_x86_64
  373. source "arch/Config.in.x86"
  374. endif
  375. if BR2_xtensa
  376. source "arch/Config.in.xtensa"
  377. endif
  378. endmenu # Target options