wandboard.c 12 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2013 Freescale Semiconductor, Inc.
  4. * Copyright (C) 2014 O.S. Systems Software LTDA.
  5. *
  6. * Author: Fabio Estevam <fabio.estevam@freescale.com>
  7. */
  8. #include <init.h>
  9. #include <asm/arch/clock.h>
  10. #include <asm/arch/crm_regs.h>
  11. #include <asm/arch/iomux.h>
  12. #include <asm/arch/imx-regs.h>
  13. #include <asm/arch/mx6-pins.h>
  14. #include <asm/arch/mxc_hdmi.h>
  15. #include <asm/arch/sys_proto.h>
  16. #include <asm/gpio.h>
  17. #include <asm/mach-imx/iomux-v3.h>
  18. #include <asm/mach-imx/mxc_i2c.h>
  19. #include <asm/mach-imx/boot_mode.h>
  20. #include <asm/mach-imx/video.h>
  21. #include <asm/mach-imx/sata.h>
  22. #include <asm/io.h>
  23. #include <env.h>
  24. #include <linux/sizes.h>
  25. #include <common.h>
  26. #include <miiphy.h>
  27. #include <netdev.h>
  28. #include <phy.h>
  29. #include <i2c.h>
  30. #include <power/pmic.h>
  31. #include <power/pfuze100_pmic.h>
  32. DECLARE_GLOBAL_DATA_PTR;
  33. #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
  34. PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
  35. PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  36. #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
  37. PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  38. #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
  39. PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
  40. PAD_CTL_ODE | PAD_CTL_SRE_FAST)
  41. #define ETH_PHY_RESET IMX_GPIO_NR(3, 29)
  42. #define ETH_PHY_AR8035_POWER IMX_GPIO_NR(7, 13)
  43. #define REV_DETECTION IMX_GPIO_NR(2, 28)
  44. /* Speed defined in Kconfig is only applicable when not using DM_I2C. */
  45. #ifdef CONFIG_DM_I2C
  46. #define I2C1_SPEED_NON_DM 0
  47. #define I2C2_SPEED_NON_DM 0
  48. #else
  49. #define I2C1_SPEED_NON_DM CONFIG_SYS_MXC_I2C1_SPEED
  50. #define I2C2_SPEED_NON_DM CONFIG_SYS_MXC_I2C2_SPEED
  51. #endif
  52. static bool with_pmic;
  53. int dram_init(void)
  54. {
  55. gd->ram_size = imx_ddr_size();
  56. return 0;
  57. }
  58. static iomux_v3_cfg_t const uart1_pads[] = {
  59. IOMUX_PADS(PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
  60. IOMUX_PADS(PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
  61. };
  62. static iomux_v3_cfg_t const enet_pads[] = {
  63. /* AR8031 PHY Reset */
  64. IOMUX_PADS(PAD_EIM_D29__GPIO3_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  65. };
  66. static iomux_v3_cfg_t const enet_ar8035_power_pads[] = {
  67. /* AR8035 POWER */
  68. IOMUX_PADS(PAD_GPIO_18__GPIO7_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  69. };
  70. static iomux_v3_cfg_t const rev_detection_pad[] = {
  71. IOMUX_PADS(PAD_EIM_EB0__GPIO2_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  72. };
  73. static void setup_iomux_uart(void)
  74. {
  75. SETUP_IOMUX_PADS(uart1_pads);
  76. }
  77. static void setup_iomux_enet(void)
  78. {
  79. SETUP_IOMUX_PADS(enet_pads);
  80. if (with_pmic) {
  81. SETUP_IOMUX_PADS(enet_ar8035_power_pads);
  82. /* enable AR8035 POWER */
  83. gpio_request(ETH_PHY_AR8035_POWER, "PHY_POWER");
  84. gpio_direction_output(ETH_PHY_AR8035_POWER, 0);
  85. }
  86. /* wait until 3.3V of PHY and clock become stable */
  87. mdelay(10);
  88. /* Reset AR8031 PHY */
  89. gpio_request(ETH_PHY_RESET, "PHY_RESET");
  90. gpio_direction_output(ETH_PHY_RESET, 0);
  91. mdelay(10);
  92. gpio_set_value(ETH_PHY_RESET, 1);
  93. udelay(100);
  94. }
  95. static int ar8031_phy_fixup(struct phy_device *phydev)
  96. {
  97. unsigned short val;
  98. int mask;
  99. /* To enable AR8031 ouput a 125MHz clk from CLK_25M */
  100. phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
  101. phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
  102. phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
  103. val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
  104. if (with_pmic)
  105. mask = 0xffe7; /* AR8035 */
  106. else
  107. mask = 0xffe3; /* AR8031 */
  108. val &= mask;
  109. val |= 0x18;
  110. phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
  111. /* introduce tx clock delay */
  112. phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
  113. val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
  114. val |= 0x0100;
  115. phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
  116. return 0;
  117. }
  118. int board_phy_config(struct phy_device *phydev)
  119. {
  120. ar8031_phy_fixup(phydev);
  121. if (phydev->drv->config)
  122. phydev->drv->config(phydev);
  123. return 0;
  124. }
  125. #if defined(CONFIG_VIDEO_IPUV3)
  126. struct i2c_pads_info mx6q_i2c2_pad_info = {
  127. .scl = {
  128. .i2c_mode = MX6Q_PAD_KEY_COL3__I2C2_SCL
  129. | MUX_PAD_CTRL(I2C_PAD_CTRL),
  130. .gpio_mode = MX6Q_PAD_KEY_COL3__GPIO4_IO12
  131. | MUX_PAD_CTRL(I2C_PAD_CTRL),
  132. .gp = IMX_GPIO_NR(4, 12)
  133. },
  134. .sda = {
  135. .i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA
  136. | MUX_PAD_CTRL(I2C_PAD_CTRL),
  137. .gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO4_IO13
  138. | MUX_PAD_CTRL(I2C_PAD_CTRL),
  139. .gp = IMX_GPIO_NR(4, 13)
  140. }
  141. };
  142. struct i2c_pads_info mx6dl_i2c2_pad_info = {
  143. .scl = {
  144. .i2c_mode = MX6DL_PAD_KEY_COL3__I2C2_SCL
  145. | MUX_PAD_CTRL(I2C_PAD_CTRL),
  146. .gpio_mode = MX6DL_PAD_KEY_COL3__GPIO4_IO12
  147. | MUX_PAD_CTRL(I2C_PAD_CTRL),
  148. .gp = IMX_GPIO_NR(4, 12)
  149. },
  150. .sda = {
  151. .i2c_mode = MX6DL_PAD_KEY_ROW3__I2C2_SDA
  152. | MUX_PAD_CTRL(I2C_PAD_CTRL),
  153. .gpio_mode = MX6DL_PAD_KEY_ROW3__GPIO4_IO13
  154. | MUX_PAD_CTRL(I2C_PAD_CTRL),
  155. .gp = IMX_GPIO_NR(4, 13)
  156. }
  157. };
  158. struct i2c_pads_info mx6q_i2c3_pad_info = {
  159. .scl = {
  160. .i2c_mode = MX6Q_PAD_GPIO_5__I2C3_SCL
  161. | MUX_PAD_CTRL(I2C_PAD_CTRL),
  162. .gpio_mode = MX6Q_PAD_GPIO_5__GPIO1_IO05
  163. | MUX_PAD_CTRL(I2C_PAD_CTRL),
  164. .gp = IMX_GPIO_NR(1, 5)
  165. },
  166. .sda = {
  167. .i2c_mode = MX6Q_PAD_GPIO_16__I2C3_SDA
  168. | MUX_PAD_CTRL(I2C_PAD_CTRL),
  169. .gpio_mode = MX6Q_PAD_GPIO_16__GPIO7_IO11
  170. | MUX_PAD_CTRL(I2C_PAD_CTRL),
  171. .gp = IMX_GPIO_NR(7, 11)
  172. }
  173. };
  174. struct i2c_pads_info mx6dl_i2c3_pad_info = {
  175. .scl = {
  176. .i2c_mode = MX6DL_PAD_GPIO_5__I2C3_SCL
  177. | MUX_PAD_CTRL(I2C_PAD_CTRL),
  178. .gpio_mode = MX6DL_PAD_GPIO_5__GPIO1_IO05
  179. | MUX_PAD_CTRL(I2C_PAD_CTRL),
  180. .gp = IMX_GPIO_NR(1, 5)
  181. },
  182. .sda = {
  183. .i2c_mode = MX6DL_PAD_GPIO_16__I2C3_SDA
  184. | MUX_PAD_CTRL(I2C_PAD_CTRL),
  185. .gpio_mode = MX6DL_PAD_GPIO_16__GPIO7_IO11
  186. | MUX_PAD_CTRL(I2C_PAD_CTRL),
  187. .gp = IMX_GPIO_NR(7, 11)
  188. }
  189. };
  190. static iomux_v3_cfg_t const fwadapt_7wvga_pads[] = {
  191. IOMUX_PADS(PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK),
  192. IOMUX_PADS(PAD_DI0_PIN2__IPU1_DI0_PIN02), /* HSync */
  193. IOMUX_PADS(PAD_DI0_PIN3__IPU1_DI0_PIN03), /* VSync */
  194. IOMUX_PADS(PAD_DI0_PIN4__IPU1_DI0_PIN04 | MUX_PAD_CTRL(PAD_CTL_DSE_120ohm)), /* Contrast */
  195. IOMUX_PADS(PAD_DI0_PIN15__IPU1_DI0_PIN15), /* DISP0_DRDY */
  196. IOMUX_PADS(PAD_DISP0_DAT0__IPU1_DISP0_DATA00),
  197. IOMUX_PADS(PAD_DISP0_DAT1__IPU1_DISP0_DATA01),
  198. IOMUX_PADS(PAD_DISP0_DAT2__IPU1_DISP0_DATA02),
  199. IOMUX_PADS(PAD_DISP0_DAT3__IPU1_DISP0_DATA03),
  200. IOMUX_PADS(PAD_DISP0_DAT4__IPU1_DISP0_DATA04),
  201. IOMUX_PADS(PAD_DISP0_DAT5__IPU1_DISP0_DATA05),
  202. IOMUX_PADS(PAD_DISP0_DAT6__IPU1_DISP0_DATA06),
  203. IOMUX_PADS(PAD_DISP0_DAT7__IPU1_DISP0_DATA07),
  204. IOMUX_PADS(PAD_DISP0_DAT8__IPU1_DISP0_DATA08),
  205. IOMUX_PADS(PAD_DISP0_DAT9__IPU1_DISP0_DATA09),
  206. IOMUX_PADS(PAD_DISP0_DAT10__IPU1_DISP0_DATA10),
  207. IOMUX_PADS(PAD_DISP0_DAT11__IPU1_DISP0_DATA11),
  208. IOMUX_PADS(PAD_DISP0_DAT12__IPU1_DISP0_DATA12),
  209. IOMUX_PADS(PAD_DISP0_DAT13__IPU1_DISP0_DATA13),
  210. IOMUX_PADS(PAD_DISP0_DAT14__IPU1_DISP0_DATA14),
  211. IOMUX_PADS(PAD_DISP0_DAT15__IPU1_DISP0_DATA15),
  212. IOMUX_PADS(PAD_DISP0_DAT16__IPU1_DISP0_DATA16),
  213. IOMUX_PADS(PAD_DISP0_DAT17__IPU1_DISP0_DATA17),
  214. IOMUX_PADS(PAD_SD4_DAT2__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* DISP0_BKLEN */
  215. IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* DISP0_VDDEN */
  216. };
  217. static void do_enable_hdmi(struct display_info_t const *dev)
  218. {
  219. imx_enable_hdmi_phy();
  220. }
  221. static int detect_i2c(struct display_info_t const *dev)
  222. {
  223. #ifdef CONFIG_DM_I2C
  224. struct udevice *bus, *udev;
  225. int rc;
  226. rc = uclass_get_device_by_seq(UCLASS_I2C, dev->bus, &bus);
  227. if (rc)
  228. return rc;
  229. rc = dm_i2c_probe(bus, dev->addr, 0, &udev);
  230. if (rc)
  231. return 0;
  232. return 1;
  233. #else
  234. return (0 == i2c_set_bus_num(dev->bus)) &&
  235. (0 == i2c_probe(dev->addr));
  236. #endif
  237. }
  238. static void enable_fwadapt_7wvga(struct display_info_t const *dev)
  239. {
  240. SETUP_IOMUX_PADS(fwadapt_7wvga_pads);
  241. gpio_request(IMX_GPIO_NR(2, 10), "DISP0_BKLEN");
  242. gpio_request(IMX_GPIO_NR(2, 11), "DISP0_VDDEN");
  243. gpio_direction_output(IMX_GPIO_NR(2, 10), 1);
  244. gpio_direction_output(IMX_GPIO_NR(2, 11), 1);
  245. }
  246. struct display_info_t const displays[] = {{
  247. .bus = -1,
  248. .addr = 0,
  249. .pixfmt = IPU_PIX_FMT_RGB24,
  250. .detect = detect_hdmi,
  251. .enable = do_enable_hdmi,
  252. .mode = {
  253. .name = "HDMI",
  254. .refresh = 60,
  255. .xres = 1024,
  256. .yres = 768,
  257. .pixclock = 15385,
  258. .left_margin = 220,
  259. .right_margin = 40,
  260. .upper_margin = 21,
  261. .lower_margin = 7,
  262. .hsync_len = 60,
  263. .vsync_len = 10,
  264. .sync = FB_SYNC_EXT,
  265. .vmode = FB_VMODE_NONINTERLACED
  266. } }, {
  267. .bus = 1,
  268. .addr = 0x10,
  269. .pixfmt = IPU_PIX_FMT_RGB666,
  270. .detect = detect_i2c,
  271. .enable = enable_fwadapt_7wvga,
  272. .mode = {
  273. .name = "FWBADAPT-LCD-F07A-0102",
  274. .refresh = 60,
  275. .xres = 800,
  276. .yres = 480,
  277. .pixclock = 33260,
  278. .left_margin = 128,
  279. .right_margin = 128,
  280. .upper_margin = 22,
  281. .lower_margin = 22,
  282. .hsync_len = 1,
  283. .vsync_len = 1,
  284. .sync = 0,
  285. .vmode = FB_VMODE_NONINTERLACED
  286. } } };
  287. size_t display_count = ARRAY_SIZE(displays);
  288. static void setup_display(void)
  289. {
  290. struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  291. int reg;
  292. enable_ipu_clock();
  293. imx_setup_hdmi();
  294. reg = readl(&mxc_ccm->chsccdr);
  295. reg |= (CHSCCDR_CLK_SEL_LDB_DI0
  296. << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
  297. writel(reg, &mxc_ccm->chsccdr);
  298. /* Disable LCD backlight */
  299. SETUP_IOMUX_PAD(PAD_DI0_PIN4__GPIO4_IO20);
  300. gpio_request(IMX_GPIO_NR(4, 20), "LCD_BKLEN");
  301. gpio_direction_input(IMX_GPIO_NR(4, 20));
  302. }
  303. #endif /* CONFIG_VIDEO_IPUV3 */
  304. int board_early_init_f(void)
  305. {
  306. setup_iomux_uart();
  307. #ifdef CONFIG_SATA
  308. setup_sata();
  309. #endif
  310. return 0;
  311. }
  312. #define PMIC_I2C_BUS 2
  313. int power_init_board(void)
  314. {
  315. struct udevice *dev;
  316. int reg, ret;
  317. puts("PMIC: ");
  318. ret = pmic_get("pfuze100", &dev);
  319. if (ret < 0) {
  320. printf("pmic_get() ret %d\n", ret);
  321. return 0;
  322. }
  323. reg = pmic_reg_read(dev, PFUZE100_DEVICEID);
  324. if (reg < 0) {
  325. printf("pmic_reg_read() ret %d\n", reg);
  326. return 0;
  327. }
  328. printf("PMIC: PFUZE100 ID=0x%02x\n", reg);
  329. with_pmic = true;
  330. /* Set VGEN2 to 1.5V and enable */
  331. reg = pmic_reg_read(dev, PFUZE100_VGEN2VOL);
  332. reg &= ~(LDO_VOL_MASK);
  333. reg |= (LDOA_1_50V | (1 << (LDO_EN)));
  334. pmic_reg_write(dev, PFUZE100_VGEN2VOL, reg);
  335. return 0;
  336. }
  337. /*
  338. * Do not overwrite the console
  339. * Use always serial for U-Boot console
  340. */
  341. int overwrite_console(void)
  342. {
  343. return 1;
  344. }
  345. #ifdef CONFIG_CMD_BMODE
  346. static const struct boot_mode board_boot_modes[] = {
  347. /* 4 bit bus width */
  348. {"mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
  349. {"mmc1", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
  350. {NULL, 0},
  351. };
  352. #endif
  353. static bool is_revc1(void)
  354. {
  355. SETUP_IOMUX_PADS(rev_detection_pad);
  356. gpio_direction_input(REV_DETECTION);
  357. if (gpio_get_value(REV_DETECTION))
  358. return true;
  359. else
  360. return false;
  361. }
  362. static bool is_revd1(void)
  363. {
  364. if (with_pmic)
  365. return true;
  366. else
  367. return false;
  368. }
  369. int board_late_init(void)
  370. {
  371. #ifdef CONFIG_CMD_BMODE
  372. add_board_boot_modes(board_boot_modes);
  373. #endif
  374. #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
  375. if (is_mx6dqp())
  376. env_set("board_rev", "MX6QP");
  377. else if (is_mx6dq())
  378. env_set("board_rev", "MX6Q");
  379. else
  380. env_set("board_rev", "MX6DL");
  381. if (is_revd1())
  382. env_set("board_name", "D1");
  383. else if (is_revc1())
  384. env_set("board_name", "C1");
  385. else
  386. env_set("board_name", "B1");
  387. #endif
  388. setup_iomux_enet();
  389. return 0;
  390. }
  391. int board_init(void)
  392. {
  393. /* address of boot parameters */
  394. gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
  395. #if defined(CONFIG_VIDEO_IPUV3)
  396. setup_i2c(1, I2C1_SPEED_NON_DM, 0x7f, &mx6dl_i2c2_pad_info);
  397. if (is_mx6dq() || is_mx6dqp()) {
  398. setup_i2c(1, I2C1_SPEED_NON_DM, 0x7f, &mx6q_i2c2_pad_info);
  399. setup_i2c(2, I2C2_SPEED_NON_DM, 0x7f, &mx6q_i2c3_pad_info);
  400. } else {
  401. setup_i2c(1, I2C1_SPEED_NON_DM, 0x7f, &mx6dl_i2c2_pad_info);
  402. setup_i2c(2, I2C2_SPEED_NON_DM, 0x7f, &mx6dl_i2c3_pad_info);
  403. }
  404. setup_display();
  405. #endif
  406. return 0;
  407. }
  408. int checkboard(void)
  409. {
  410. gpio_request(REV_DETECTION, "REV_DETECT");
  411. if (is_revd1())
  412. puts("Board: Wandboard rev D1\n");
  413. else if (is_revc1())
  414. puts("Board: Wandboard rev C1\n");
  415. else
  416. puts("Board: Wandboard rev B1\n");
  417. return 0;
  418. }
  419. #ifdef CONFIG_SPL_LOAD_FIT
  420. int board_fit_config_name_match(const char *name)
  421. {
  422. if (is_mx6dq()) {
  423. if (!strcmp(name, "imx6q-wandboard-revb1"))
  424. return 0;
  425. } else if (is_mx6dqp()) {
  426. if (!strcmp(name, "imx6qp-wandboard-revd1"))
  427. return 0;
  428. } else if (is_mx6dl() || is_mx6solo()) {
  429. if (!strcmp(name, "imx6dl-wandboard-revb1"))
  430. return 0;
  431. }
  432. return -EINVAL;
  433. }
  434. #endif