spl.c 15 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2014 Wandboard
  4. * Author: Tungyi Lin <tungyilin1127@gmail.com>
  5. * Richard Hu <hakahu@gmail.com>
  6. */
  7. #include <asm/arch/clock.h>
  8. #include <asm/arch/imx-regs.h>
  9. #include <asm/arch/iomux.h>
  10. #include <asm/arch/mx6-pins.h>
  11. #include <linux/errno.h>
  12. #include <asm/gpio.h>
  13. #include <asm/mach-imx/iomux-v3.h>
  14. #include <asm/mach-imx/video.h>
  15. #include <mmc.h>
  16. #include <fsl_esdhc_imx.h>
  17. #include <asm/arch/crm_regs.h>
  18. #include <asm/io.h>
  19. #include <asm/arch/sys_proto.h>
  20. #include <spl.h>
  21. #include <asm/arch/mx6-ddr.h>
  22. /*
  23. * Driving strength:
  24. * 0x30 == 40 Ohm
  25. * 0x28 == 48 Ohm
  26. */
  27. #define IMX6DQ_DRIVE_STRENGTH 0x30
  28. #define IMX6SDL_DRIVE_STRENGTH 0x28
  29. #define IMX6QP_DRIVE_STRENGTH 0x28
  30. /* configure MX6Q/DUAL mmdc DDR io registers */
  31. static struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = {
  32. .dram_sdclk_0 = IMX6DQ_DRIVE_STRENGTH,
  33. .dram_sdclk_1 = IMX6DQ_DRIVE_STRENGTH,
  34. .dram_cas = IMX6DQ_DRIVE_STRENGTH,
  35. .dram_ras = IMX6DQ_DRIVE_STRENGTH,
  36. .dram_reset = IMX6DQ_DRIVE_STRENGTH,
  37. .dram_sdcke0 = IMX6DQ_DRIVE_STRENGTH,
  38. .dram_sdcke1 = IMX6DQ_DRIVE_STRENGTH,
  39. .dram_sdba2 = 0x00000000,
  40. .dram_sdodt0 = IMX6DQ_DRIVE_STRENGTH,
  41. .dram_sdodt1 = IMX6DQ_DRIVE_STRENGTH,
  42. .dram_sdqs0 = IMX6DQ_DRIVE_STRENGTH,
  43. .dram_sdqs1 = IMX6DQ_DRIVE_STRENGTH,
  44. .dram_sdqs2 = IMX6DQ_DRIVE_STRENGTH,
  45. .dram_sdqs3 = IMX6DQ_DRIVE_STRENGTH,
  46. .dram_sdqs4 = IMX6DQ_DRIVE_STRENGTH,
  47. .dram_sdqs5 = IMX6DQ_DRIVE_STRENGTH,
  48. .dram_sdqs6 = IMX6DQ_DRIVE_STRENGTH,
  49. .dram_sdqs7 = IMX6DQ_DRIVE_STRENGTH,
  50. .dram_dqm0 = IMX6DQ_DRIVE_STRENGTH,
  51. .dram_dqm1 = IMX6DQ_DRIVE_STRENGTH,
  52. .dram_dqm2 = IMX6DQ_DRIVE_STRENGTH,
  53. .dram_dqm3 = IMX6DQ_DRIVE_STRENGTH,
  54. .dram_dqm4 = IMX6DQ_DRIVE_STRENGTH,
  55. .dram_dqm5 = IMX6DQ_DRIVE_STRENGTH,
  56. .dram_dqm6 = IMX6DQ_DRIVE_STRENGTH,
  57. .dram_dqm7 = IMX6DQ_DRIVE_STRENGTH,
  58. };
  59. /* configure MX6QP mmdc DDR io registers */
  60. static struct mx6dq_iomux_ddr_regs mx6qp_ddr_ioregs = {
  61. .dram_sdclk_0 = IMX6QP_DRIVE_STRENGTH,
  62. .dram_sdclk_1 = IMX6QP_DRIVE_STRENGTH,
  63. .dram_cas = IMX6QP_DRIVE_STRENGTH,
  64. .dram_ras = IMX6QP_DRIVE_STRENGTH,
  65. .dram_reset = IMX6QP_DRIVE_STRENGTH,
  66. .dram_sdcke0 = IMX6QP_DRIVE_STRENGTH,
  67. .dram_sdcke1 = IMX6QP_DRIVE_STRENGTH,
  68. .dram_sdba2 = 0x00000000,
  69. .dram_sdodt0 = IMX6QP_DRIVE_STRENGTH,
  70. .dram_sdodt1 = IMX6QP_DRIVE_STRENGTH,
  71. .dram_sdqs0 = IMX6QP_DRIVE_STRENGTH,
  72. .dram_sdqs1 = IMX6QP_DRIVE_STRENGTH,
  73. .dram_sdqs2 = IMX6QP_DRIVE_STRENGTH,
  74. .dram_sdqs3 = IMX6QP_DRIVE_STRENGTH,
  75. .dram_sdqs4 = IMX6QP_DRIVE_STRENGTH,
  76. .dram_sdqs5 = IMX6QP_DRIVE_STRENGTH,
  77. .dram_sdqs6 = IMX6QP_DRIVE_STRENGTH,
  78. .dram_sdqs7 = IMX6QP_DRIVE_STRENGTH,
  79. .dram_dqm0 = IMX6QP_DRIVE_STRENGTH,
  80. .dram_dqm1 = IMX6QP_DRIVE_STRENGTH,
  81. .dram_dqm2 = IMX6QP_DRIVE_STRENGTH,
  82. .dram_dqm3 = IMX6QP_DRIVE_STRENGTH,
  83. .dram_dqm4 = IMX6QP_DRIVE_STRENGTH,
  84. .dram_dqm5 = IMX6QP_DRIVE_STRENGTH,
  85. .dram_dqm6 = IMX6QP_DRIVE_STRENGTH,
  86. .dram_dqm7 = IMX6QP_DRIVE_STRENGTH,
  87. };
  88. /* configure MX6Q/DUAL mmdc GRP io registers */
  89. static struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = {
  90. .grp_ddr_type = 0x000c0000,
  91. .grp_ddrmode_ctl = 0x00020000,
  92. .grp_ddrpke = 0x00000000,
  93. .grp_addds = IMX6DQ_DRIVE_STRENGTH,
  94. .grp_ctlds = IMX6DQ_DRIVE_STRENGTH,
  95. .grp_ddrmode = 0x00020000,
  96. .grp_b0ds = IMX6DQ_DRIVE_STRENGTH,
  97. .grp_b1ds = IMX6DQ_DRIVE_STRENGTH,
  98. .grp_b2ds = IMX6DQ_DRIVE_STRENGTH,
  99. .grp_b3ds = IMX6DQ_DRIVE_STRENGTH,
  100. .grp_b4ds = IMX6DQ_DRIVE_STRENGTH,
  101. .grp_b5ds = IMX6DQ_DRIVE_STRENGTH,
  102. .grp_b6ds = IMX6DQ_DRIVE_STRENGTH,
  103. .grp_b7ds = IMX6DQ_DRIVE_STRENGTH,
  104. };
  105. /* configure MX6QP mmdc GRP io registers */
  106. static struct mx6dq_iomux_grp_regs mx6qp_grp_ioregs = {
  107. .grp_ddr_type = 0x000c0000,
  108. .grp_ddrmode_ctl = 0x00020000,
  109. .grp_ddrpke = 0x00000000,
  110. .grp_addds = IMX6QP_DRIVE_STRENGTH,
  111. .grp_ctlds = IMX6QP_DRIVE_STRENGTH,
  112. .grp_ddrmode = 0x00020000,
  113. .grp_b0ds = IMX6QP_DRIVE_STRENGTH,
  114. .grp_b1ds = IMX6QP_DRIVE_STRENGTH,
  115. .grp_b2ds = IMX6QP_DRIVE_STRENGTH,
  116. .grp_b3ds = IMX6QP_DRIVE_STRENGTH,
  117. .grp_b4ds = IMX6QP_DRIVE_STRENGTH,
  118. .grp_b5ds = IMX6QP_DRIVE_STRENGTH,
  119. .grp_b6ds = IMX6QP_DRIVE_STRENGTH,
  120. .grp_b7ds = IMX6QP_DRIVE_STRENGTH,
  121. };
  122. /* configure MX6SOLO/DUALLITE mmdc DDR io registers */
  123. struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = {
  124. .dram_sdclk_0 = IMX6SDL_DRIVE_STRENGTH,
  125. .dram_sdclk_1 = IMX6SDL_DRIVE_STRENGTH,
  126. .dram_cas = IMX6SDL_DRIVE_STRENGTH,
  127. .dram_ras = IMX6SDL_DRIVE_STRENGTH,
  128. .dram_reset = IMX6SDL_DRIVE_STRENGTH,
  129. .dram_sdcke0 = IMX6SDL_DRIVE_STRENGTH,
  130. .dram_sdcke1 = IMX6SDL_DRIVE_STRENGTH,
  131. .dram_sdba2 = 0x00000000,
  132. .dram_sdodt0 = IMX6SDL_DRIVE_STRENGTH,
  133. .dram_sdodt1 = IMX6SDL_DRIVE_STRENGTH,
  134. .dram_sdqs0 = IMX6SDL_DRIVE_STRENGTH,
  135. .dram_sdqs1 = IMX6SDL_DRIVE_STRENGTH,
  136. .dram_sdqs2 = IMX6SDL_DRIVE_STRENGTH,
  137. .dram_sdqs3 = IMX6SDL_DRIVE_STRENGTH,
  138. .dram_sdqs4 = IMX6SDL_DRIVE_STRENGTH,
  139. .dram_sdqs5 = IMX6SDL_DRIVE_STRENGTH,
  140. .dram_sdqs6 = IMX6SDL_DRIVE_STRENGTH,
  141. .dram_sdqs7 = IMX6SDL_DRIVE_STRENGTH,
  142. .dram_dqm0 = IMX6SDL_DRIVE_STRENGTH,
  143. .dram_dqm1 = IMX6SDL_DRIVE_STRENGTH,
  144. .dram_dqm2 = IMX6SDL_DRIVE_STRENGTH,
  145. .dram_dqm3 = IMX6SDL_DRIVE_STRENGTH,
  146. .dram_dqm4 = IMX6SDL_DRIVE_STRENGTH,
  147. .dram_dqm5 = IMX6SDL_DRIVE_STRENGTH,
  148. .dram_dqm6 = IMX6SDL_DRIVE_STRENGTH,
  149. .dram_dqm7 = IMX6SDL_DRIVE_STRENGTH,
  150. };
  151. /* configure MX6SOLO/DUALLITE mmdc GRP io registers */
  152. struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = {
  153. .grp_ddr_type = 0x000c0000,
  154. .grp_ddrmode_ctl = 0x00020000,
  155. .grp_ddrpke = 0x00000000,
  156. .grp_addds = IMX6SDL_DRIVE_STRENGTH,
  157. .grp_ctlds = IMX6SDL_DRIVE_STRENGTH,
  158. .grp_ddrmode = 0x00020000,
  159. .grp_b0ds = IMX6SDL_DRIVE_STRENGTH,
  160. .grp_b1ds = IMX6SDL_DRIVE_STRENGTH,
  161. .grp_b2ds = IMX6SDL_DRIVE_STRENGTH,
  162. .grp_b3ds = IMX6SDL_DRIVE_STRENGTH,
  163. .grp_b4ds = IMX6SDL_DRIVE_STRENGTH,
  164. .grp_b5ds = IMX6SDL_DRIVE_STRENGTH,
  165. .grp_b6ds = IMX6SDL_DRIVE_STRENGTH,
  166. .grp_b7ds = IMX6SDL_DRIVE_STRENGTH,
  167. };
  168. /* H5T04G63AFR-PB */
  169. static struct mx6_ddr3_cfg h5t04g63afr = {
  170. .mem_speed = 1600,
  171. .density = 4,
  172. .width = 16,
  173. .banks = 8,
  174. .rowaddr = 15,
  175. .coladdr = 10,
  176. .pagesz = 2,
  177. .trcd = 1375,
  178. .trcmin = 4875,
  179. .trasmin = 3500,
  180. };
  181. /* H5TQ2G63DFR-H9 */
  182. static struct mx6_ddr3_cfg h5tq2g63dfr = {
  183. .mem_speed = 1333,
  184. .density = 2,
  185. .width = 16,
  186. .banks = 8,
  187. .rowaddr = 14,
  188. .coladdr = 10,
  189. .pagesz = 2,
  190. .trcd = 1350,
  191. .trcmin = 4950,
  192. .trasmin = 3600,
  193. };
  194. static struct mx6_mmdc_calibration mx6q_2g_mmdc_calib = {
  195. .p0_mpwldectrl0 = 0x001f001f,
  196. .p0_mpwldectrl1 = 0x001f001f,
  197. .p1_mpwldectrl0 = 0x001f001f,
  198. .p1_mpwldectrl1 = 0x001f001f,
  199. .p0_mpdgctrl0 = 0x4301030d,
  200. .p0_mpdgctrl1 = 0x03020277,
  201. .p1_mpdgctrl0 = 0x4300030a,
  202. .p1_mpdgctrl1 = 0x02780248,
  203. .p0_mprddlctl = 0x4536393b,
  204. .p1_mprddlctl = 0x36353441,
  205. .p0_mpwrdlctl = 0x41414743,
  206. .p1_mpwrdlctl = 0x462f453f,
  207. };
  208. /* DDR 64bit 2GB */
  209. static struct mx6_ddr_sysinfo mem_q = {
  210. .dsize = 2,
  211. .cs1_mirror = 0,
  212. /* config for full 4GB range so that get_mem_size() works */
  213. .cs_density = 32,
  214. .ncs = 1,
  215. .bi_on = 1,
  216. .rtt_nom = 1,
  217. .rtt_wr = 0,
  218. .ralat = 5,
  219. .walat = 0,
  220. .mif3_mode = 3,
  221. .rst_to_cke = 0x23,
  222. .sde_to_rst = 0x10,
  223. .refsel = 1, /* Refresh cycles at 32KHz */
  224. .refr = 3, /* 4 refresh commands per refresh cycle */
  225. };
  226. static struct mx6_mmdc_calibration mx6dl_1g_mmdc_calib = {
  227. .p0_mpwldectrl0 = 0x001f001f,
  228. .p0_mpwldectrl1 = 0x001f001f,
  229. .p1_mpwldectrl0 = 0x001f001f,
  230. .p1_mpwldectrl1 = 0x001f001f,
  231. .p0_mpdgctrl0 = 0x420e020e,
  232. .p0_mpdgctrl1 = 0x02000200,
  233. .p1_mpdgctrl0 = 0x42020202,
  234. .p1_mpdgctrl1 = 0x01720172,
  235. .p0_mprddlctl = 0x494c4f4c,
  236. .p1_mprddlctl = 0x4a4c4c49,
  237. .p0_mpwrdlctl = 0x3f3f3133,
  238. .p1_mpwrdlctl = 0x39373f2e,
  239. };
  240. static struct mx6_mmdc_calibration mx6s_512m_mmdc_calib = {
  241. .p0_mpwldectrl0 = 0x0040003c,
  242. .p0_mpwldectrl1 = 0x0032003e,
  243. .p0_mpdgctrl0 = 0x42350231,
  244. .p0_mpdgctrl1 = 0x021a0218,
  245. .p0_mprddlctl = 0x4b4b4e49,
  246. .p0_mpwrdlctl = 0x3f3f3035,
  247. };
  248. /* DDR 64bit 1GB */
  249. static struct mx6_ddr_sysinfo mem_dl = {
  250. .dsize = 2,
  251. .cs1_mirror = 0,
  252. /* config for full 4GB range so that get_mem_size() works */
  253. .cs_density = 32,
  254. .ncs = 1,
  255. .bi_on = 1,
  256. .rtt_nom = 1,
  257. .rtt_wr = 0,
  258. .ralat = 5,
  259. .walat = 0,
  260. .mif3_mode = 3,
  261. .rst_to_cke = 0x23,
  262. .sde_to_rst = 0x10,
  263. .refsel = 1, /* Refresh cycles at 32KHz */
  264. .refr = 3, /* 4 refresh commands per refresh cycle */
  265. };
  266. /* DDR 32bit 512MB */
  267. static struct mx6_ddr_sysinfo mem_s = {
  268. .dsize = 1,
  269. .cs1_mirror = 0,
  270. /* config for full 4GB range so that get_mem_size() works */
  271. .cs_density = 32,
  272. .ncs = 1,
  273. .bi_on = 1,
  274. .rtt_nom = 1,
  275. .rtt_wr = 0,
  276. .ralat = 5,
  277. .walat = 0,
  278. .mif3_mode = 3,
  279. .rst_to_cke = 0x23,
  280. .sde_to_rst = 0x10,
  281. .refsel = 1, /* Refresh cycles at 32KHz */
  282. .refr = 3, /* 4 refresh commands per refresh cycle */
  283. };
  284. static void ccgr_init(void)
  285. {
  286. struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  287. writel(0x00C03F3F, &ccm->CCGR0);
  288. writel(0x0030FC03, &ccm->CCGR1);
  289. writel(0x0FFFC000, &ccm->CCGR2);
  290. writel(0x3FF03000, &ccm->CCGR3);
  291. writel(0x00FFF300, &ccm->CCGR4);
  292. writel(0x0F0000C3, &ccm->CCGR5);
  293. writel(0x000003FF, &ccm->CCGR6);
  294. }
  295. static void spl_dram_init_imx6qp_lpddr3(void)
  296. {
  297. /* MMDC0_MDSCR set the Configuration request bit during MMDC set up */
  298. writel(0x00008000, MMDC_P0_BASE_ADDR + 0x01c);
  299. /* Calibrations - ZQ */
  300. writel(0xa1390003, MMDC_P0_BASE_ADDR + 0x800);
  301. /* write leveling */
  302. writel(0x00060004, MMDC_P0_BASE_ADDR + 0x80c);
  303. writel(0x000B0004, MMDC_P0_BASE_ADDR + 0x810);
  304. writel(0x00000004, MMDC_P1_BASE_ADDR + 0x80c);
  305. writel(0x00000000, MMDC_P1_BASE_ADDR + 0x810);
  306. /*
  307. * DQS gating, read delay, write delay calibration values
  308. * based on calibration compare of 0x00ffff00
  309. */
  310. writel(0x03040314, MMDC_P0_BASE_ADDR + 0x83c);
  311. writel(0x03080300, MMDC_P0_BASE_ADDR + 0x840);
  312. writel(0x03000310, MMDC_P1_BASE_ADDR + 0x83c);
  313. writel(0x0268023C, MMDC_P1_BASE_ADDR + 0x840);
  314. writel(0x4034363A, MMDC_P0_BASE_ADDR + 0x848);
  315. writel(0x36302C3C, MMDC_P1_BASE_ADDR + 0x848);
  316. writel(0x3E3E4046, MMDC_P0_BASE_ADDR + 0x850);
  317. writel(0x483A4844, MMDC_P1_BASE_ADDR + 0x850);
  318. writel(0x33333333, MMDC_P0_BASE_ADDR + 0x81c);
  319. writel(0x33333333, MMDC_P0_BASE_ADDR + 0x820);
  320. writel(0x33333333, MMDC_P0_BASE_ADDR + 0x824);
  321. writel(0x33333333, MMDC_P0_BASE_ADDR + 0x828);
  322. writel(0x33333333, MMDC_P1_BASE_ADDR + 0x81c);
  323. writel(0x33333333, MMDC_P1_BASE_ADDR + 0x820);
  324. writel(0x33333333, MMDC_P1_BASE_ADDR + 0x824);
  325. writel(0x33333333, MMDC_P1_BASE_ADDR + 0x828);
  326. writel(0x24912489, MMDC_P0_BASE_ADDR + 0x8c0);
  327. writel(0x24914452, MMDC_P1_BASE_ADDR + 0x8c0);
  328. writel(0x00000800, MMDC_P0_BASE_ADDR + 0x8b8);
  329. writel(0x00000800, MMDC_P1_BASE_ADDR + 0x8b8);
  330. /* MMDC init: in DDR3, 64-bit mode, only MMDC0 is initiated */
  331. writel(0x00020036, MMDC_P0_BASE_ADDR + 0x004);
  332. writel(0x09444040, MMDC_P0_BASE_ADDR + 0x008);
  333. writel(0x898E79A4, MMDC_P0_BASE_ADDR + 0x00c);
  334. writel(0xDB538F64, MMDC_P0_BASE_ADDR + 0x010);
  335. writel(0x01FF00DD, MMDC_P0_BASE_ADDR + 0x014);
  336. writel(0x00011740, MMDC_P0_BASE_ADDR + 0x018);
  337. writel(0x00008000, MMDC_P0_BASE_ADDR + 0x01c);
  338. writel(0x000026D2, MMDC_P0_BASE_ADDR + 0x02c);
  339. writel(0x008E1023, MMDC_P0_BASE_ADDR + 0x030);
  340. writel(0x00000047, MMDC_P0_BASE_ADDR + 0x040);
  341. writel(0x14420000, MMDC_P0_BASE_ADDR + 0x400);
  342. writel(0x841A0000, MMDC_P0_BASE_ADDR + 0x000);
  343. writel(0x00400c58, MMDC_P0_BASE_ADDR + 0x890);
  344. /* add NOC DDR configuration */
  345. writel(0x00000000, NOC_DDR_BASE_ADDR + 0x008);
  346. writel(0x2871C39B, NOC_DDR_BASE_ADDR + 0x00c);
  347. writel(0x000005B4, NOC_DDR_BASE_ADDR + 0x038);
  348. writel(0x00000040, NOC_DDR_BASE_ADDR + 0x014);
  349. writel(0x00000020, NOC_DDR_BASE_ADDR + 0x028);
  350. writel(0x00000020, NOC_DDR_BASE_ADDR + 0x02c);
  351. writel(0x02088032, MMDC_P0_BASE_ADDR + 0x01c);
  352. writel(0x00008033, MMDC_P0_BASE_ADDR + 0x01c);
  353. writel(0x00048031, MMDC_P0_BASE_ADDR + 0x01c);
  354. writel(0x19308030, MMDC_P0_BASE_ADDR + 0x01c);
  355. writel(0x04008040, MMDC_P0_BASE_ADDR + 0x01c);
  356. writel(0x00007800, MMDC_P0_BASE_ADDR + 0x020);
  357. writel(0x00022227, MMDC_P0_BASE_ADDR + 0x818);
  358. writel(0x00022227, MMDC_P1_BASE_ADDR + 0x818);
  359. writel(0x00025576, MMDC_P0_BASE_ADDR + 0x004);
  360. writel(0x00011006, MMDC_P0_BASE_ADDR + 0x404);
  361. writel(0x00000000, MMDC_P0_BASE_ADDR + 0x01c);
  362. }
  363. static void spl_dram_init(void)
  364. {
  365. if (is_mx6dqp()) {
  366. mx6dq_dram_iocfg(64, &mx6qp_ddr_ioregs, &mx6qp_grp_ioregs);
  367. spl_dram_init_imx6qp_lpddr3();
  368. } else if (is_cpu_type(MXC_CPU_MX6SOLO)) {
  369. mx6sdl_dram_iocfg(32, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
  370. mx6_dram_cfg(&mem_s, &mx6s_512m_mmdc_calib, &h5tq2g63dfr);
  371. } else if (is_cpu_type(MXC_CPU_MX6DL)) {
  372. mx6sdl_dram_iocfg(64, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
  373. mx6_dram_cfg(&mem_dl, &mx6dl_1g_mmdc_calib, &h5tq2g63dfr);
  374. } else if (is_cpu_type(MXC_CPU_MX6Q)) {
  375. mx6dq_dram_iocfg(64, &mx6dq_ddr_ioregs, &mx6dq_grp_ioregs);
  376. mx6_dram_cfg(&mem_q, &mx6q_2g_mmdc_calib, &h5t04g63afr);
  377. }
  378. udelay(100);
  379. }
  380. void board_init_f(ulong dummy)
  381. {
  382. ccgr_init();
  383. /* setup AIPS and disable watchdog */
  384. arch_cpu_init();
  385. gpr_init();
  386. /* iomux */
  387. board_early_init_f();
  388. /* setup GP timer */
  389. timer_init();
  390. /* UART clocks enabled and gd valid - init serial console */
  391. preloader_console_init();
  392. /* DDR initialization */
  393. spl_dram_init();
  394. }
  395. #define USDHC1_CD_GPIO IMX_GPIO_NR(1, 2)
  396. #define USDHC3_CD_GPIO IMX_GPIO_NR(3, 9)
  397. #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
  398. PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
  399. PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  400. static struct fsl_esdhc_cfg usdhc_cfg[2] = {
  401. {USDHC3_BASE_ADDR},
  402. {USDHC1_BASE_ADDR},
  403. };
  404. static iomux_v3_cfg_t const usdhc1_pads[] = {
  405. IOMUX_PADS(PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  406. IOMUX_PADS(PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  407. IOMUX_PADS(PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  408. IOMUX_PADS(PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  409. IOMUX_PADS(PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  410. IOMUX_PADS(PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  411. /* Carrier MicroSD Card Detect */
  412. IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  413. };
  414. static iomux_v3_cfg_t const usdhc3_pads[] = {
  415. IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  416. IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  417. IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  418. IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  419. IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  420. IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  421. /* SOM MicroSD Card Detect */
  422. IOMUX_PADS(PAD_EIM_DA9__GPIO3_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  423. };
  424. int board_mmc_getcd(struct mmc *mmc)
  425. {
  426. struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
  427. int ret = 0;
  428. switch (cfg->esdhc_base) {
  429. case USDHC1_BASE_ADDR:
  430. ret = !gpio_get_value(USDHC1_CD_GPIO);
  431. break;
  432. case USDHC3_BASE_ADDR:
  433. ret = !gpio_get_value(USDHC3_CD_GPIO);
  434. break;
  435. }
  436. return ret;
  437. }
  438. int board_mmc_init(bd_t *bis)
  439. {
  440. int ret;
  441. u32 index = 0;
  442. /*
  443. * Following map is done:
  444. * (U-Boot device node) (Physical Port)
  445. * mmc0 SOM MicroSD
  446. * mmc1 Carrier board MicroSD
  447. */
  448. for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
  449. switch (index) {
  450. case 0:
  451. SETUP_IOMUX_PADS(usdhc3_pads);
  452. usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
  453. usdhc_cfg[0].max_bus_width = 4;
  454. gpio_direction_input(USDHC3_CD_GPIO);
  455. break;
  456. case 1:
  457. SETUP_IOMUX_PADS(usdhc1_pads);
  458. usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
  459. usdhc_cfg[1].max_bus_width = 4;
  460. gpio_direction_input(USDHC1_CD_GPIO);
  461. break;
  462. default:
  463. printf("Warning: you configured more USDHC controllers"
  464. "(%d) then supported by the board (%d)\n",
  465. index + 1, CONFIG_SYS_FSL_USDHC_NUM);
  466. return -EINVAL;
  467. }
  468. ret = fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
  469. if (ret)
  470. return ret;
  471. }
  472. return 0;
  473. }