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+From 68fa519a6cb455005317bd61f95214b58b2f1e69 Mon Sep 17 00:00:00 2001
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+From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= <f4bug@amsat.org>
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+Date: Fri, 16 Oct 2020 15:20:37 +0200
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+Subject: [PATCH] target/mips: Increase number of TLB entries on the 34Kf core
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+ (16 -> 64)
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+MIME-Version: 1.0
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+Content-Type: text/plain; charset=UTF-8
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+Content-Transfer-Encoding: 8bit
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+
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+Per "MIPS32 34K Processor Core Family Software User's Manual,
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+Revision 01.13" page 8 in "Joint TLB (JTLB)" section:
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+
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+ "The JTLB is a fully associative TLB cache containing 16, 32,
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+ or 64-dual-entries mapping up to 128 virtual pages to their
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+ corresponding physical addresses."
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+
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+There is no particular reason to restrict the 34Kf core model to
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+16 TLB entries, so raise its config to 64.
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+
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+This is helpful for other projects, in particular the Yocto Project:
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+
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+ Yocto Project uses qemu-system-mips 34Kf cpu model, to run 32bit
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+ MIPS CI loop. It was observed that in this case CI test execution
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+ time was almost twice longer than 64bit MIPS variant that runs
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+ under MIPS64R2-generic model. It was investigated and concluded
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+ that the difference in number of TLBs 16 in 34Kf case vs 64 in
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+ MIPS64R2-generic is responsible for most of CI real time execution
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+ difference. Because with 16 TLBs linux user-land trashes TLB more
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+ and it needs to execute more instructions in TLB refill handler
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+ calls, as result it runs much longer.
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+
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+(https://lists.gnu.org/archive/html/qemu-devel/2020-10/msg03428.html)
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+
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+Buglink: https://bugzilla.yoctoproject.org/show_bug.cgi?id=13992
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+Reported-by: Victor Kamensky <kamensky@cisco.com>
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+Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
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+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
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+Message-Id: <20201016133317.553068-1-f4bug@amsat.org>
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+
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+Upstream-Status: Backport [https://github.com/qemu/qemu/commit/68fa519a6cb455005317bd61f95214b58b2f1e69]
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+Signed-off-by: Victor Kamensky <kamensky@cisco.com>
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+
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+---
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+ target/mips/translate_init.c.inc | 2 +-
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+ 1 file changed, 1 insertion(+), 1 deletion(-)
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+
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+Index: qemu-5.1.0/target/mips/translate_init.inc.c
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+===================================================================
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+--- qemu-5.1.0.orig/target/mips/translate_init.inc.c
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++++ qemu-5.1.0/target/mips/translate_init.inc.c
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+@@ -254,7 +254,7 @@ const mips_def_t mips_defs[] =
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+ .CP0_PRid = 0x00019500,
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+ .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
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+ (MMU_TYPE_R4000 << CP0C0_MT),
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+- .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) |
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++ .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (63 << CP0C1_MMU) |
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+ (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
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+ (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
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+ (1 << CP0C1_CA),
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