0001-target-mips-Increase-number-of-TLB-entries-on-the-34.patch 2.7 KB

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  1. From 68fa519a6cb455005317bd61f95214b58b2f1e69 Mon Sep 17 00:00:00 2001
  2. From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= <f4bug@amsat.org>
  3. Date: Fri, 16 Oct 2020 15:20:37 +0200
  4. Subject: [PATCH] target/mips: Increase number of TLB entries on the 34Kf core
  5. (16 -> 64)
  6. MIME-Version: 1.0
  7. Content-Type: text/plain; charset=UTF-8
  8. Content-Transfer-Encoding: 8bit
  9. Per "MIPS32 34K Processor Core Family Software User's Manual,
  10. Revision 01.13" page 8 in "Joint TLB (JTLB)" section:
  11. "The JTLB is a fully associative TLB cache containing 16, 32,
  12. or 64-dual-entries mapping up to 128 virtual pages to their
  13. corresponding physical addresses."
  14. There is no particular reason to restrict the 34Kf core model to
  15. 16 TLB entries, so raise its config to 64.
  16. This is helpful for other projects, in particular the Yocto Project:
  17. Yocto Project uses qemu-system-mips 34Kf cpu model, to run 32bit
  18. MIPS CI loop. It was observed that in this case CI test execution
  19. time was almost twice longer than 64bit MIPS variant that runs
  20. under MIPS64R2-generic model. It was investigated and concluded
  21. that the difference in number of TLBs 16 in 34Kf case vs 64 in
  22. MIPS64R2-generic is responsible for most of CI real time execution
  23. difference. Because with 16 TLBs linux user-land trashes TLB more
  24. and it needs to execute more instructions in TLB refill handler
  25. calls, as result it runs much longer.
  26. (https://lists.gnu.org/archive/html/qemu-devel/2020-10/msg03428.html)
  27. Buglink: https://bugzilla.yoctoproject.org/show_bug.cgi?id=13992
  28. Reported-by: Victor Kamensky <kamensky@cisco.com>
  29. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
  30. Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
  31. Message-Id: <20201016133317.553068-1-f4bug@amsat.org>
  32. Upstream-Status: Backport [https://github.com/qemu/qemu/commit/68fa519a6cb455005317bd61f95214b58b2f1e69]
  33. Signed-off-by: Victor Kamensky <kamensky@cisco.com>
  34. ---
  35. target/mips/translate_init.c.inc | 2 +-
  36. 1 file changed, 1 insertion(+), 1 deletion(-)
  37. Index: qemu-5.1.0/target/mips/translate_init.inc.c
  38. ===================================================================
  39. --- qemu-5.1.0.orig/target/mips/translate_init.inc.c
  40. +++ qemu-5.1.0/target/mips/translate_init.inc.c
  41. @@ -254,7 +254,7 @@ const mips_def_t mips_defs[] =
  42. .CP0_PRid = 0x00019500,
  43. .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
  44. (MMU_TYPE_R4000 << CP0C0_MT),
  45. - .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) |
  46. + .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (63 << CP0C1_MMU) |
  47. (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
  48. (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
  49. (1 << CP0C1_CA),