vha_cr_mirage.h 170 KB

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  1. /*************************************************************************/ /*!
  2. @Title Hardware definition file vha_cr_mirage.h
  3. @Copyright Copyright (c) Imagination Technologies Ltd. All Rights Reserved
  4. */ /**************************************************************************/
  5. /* **** Autogenerated C -- do not edit **** */
  6. /*
  7. */
  8. #ifndef _VHA_CR_MIRAGE_H_
  9. #define _VHA_CR_MIRAGE_H_
  10. #define VHA_CR_MIRAGE_REVISION 1
  11. #define VHA_CR_MH_CONTROL_PERSISTENCE_TYPE_MASK (0x00000003U)
  12. #define VHA_CR_MH_CONTROL_MAX_BURST_LENGTH_MASK (0x00000003U)
  13. #define VHA_CR_CLK_CTRL0_MODE_MASK (0x00000003U)
  14. /*
  15. The domain clock is forced off */
  16. #define VHA_CR_CLK_CTRL0_MODE_OFF (0x00000000U)
  17. /*
  18. The domain clock is forced on */
  19. #define VHA_CR_CLK_CTRL0_MODE_ON (0x00000001U)
  20. /*
  21. Automatic clock gating is active, the domain clock is only on whilst data is being processed */
  22. #define VHA_CR_CLK_CTRL0_MODE_AUTO (0x00000002U)
  23. /*
  24. Register VHA_CR_CLK_CTRL0
  25. */
  26. #define VHA_CR_CLK_CTRL0 (0x0000U)
  27. #define VHA_CR_CLK_CTRL0_MASKFULL (IMG_UINT64_C(0x03FFFFFF30000330))
  28. #define VHA_CR_CLK_CTRL0_CNN_EWO_SHIFT (56U)
  29. #define VHA_CR_CLK_CTRL0_CNN_EWO_CLRMSK (IMG_UINT64_C(0XFCFFFFFFFFFFFFFF))
  30. #define VHA_CR_CLK_CTRL0_CNN_EWO_OFF (IMG_UINT64_C(0000000000000000))
  31. #define VHA_CR_CLK_CTRL0_CNN_EWO_ON (IMG_UINT64_C(0x0100000000000000))
  32. #define VHA_CR_CLK_CTRL0_CNN_EWO_AUTO (IMG_UINT64_C(0x0200000000000000))
  33. #define VHA_CR_CLK_CTRL0_CNN_PACK_SHIFT (54U)
  34. #define VHA_CR_CLK_CTRL0_CNN_PACK_CLRMSK (IMG_UINT64_C(0XFF3FFFFFFFFFFFFF))
  35. #define VHA_CR_CLK_CTRL0_CNN_PACK_OFF (IMG_UINT64_C(0000000000000000))
  36. #define VHA_CR_CLK_CTRL0_CNN_PACK_ON (IMG_UINT64_C(0x0040000000000000))
  37. #define VHA_CR_CLK_CTRL0_CNN_PACK_AUTO (IMG_UINT64_C(0x0080000000000000))
  38. #define VHA_CR_CLK_CTRL0_CNN_OIN_SHIFT (52U)
  39. #define VHA_CR_CLK_CTRL0_CNN_OIN_CLRMSK (IMG_UINT64_C(0XFFCFFFFFFFFFFFFF))
  40. #define VHA_CR_CLK_CTRL0_CNN_OIN_OFF (IMG_UINT64_C(0000000000000000))
  41. #define VHA_CR_CLK_CTRL0_CNN_OIN_ON (IMG_UINT64_C(0x0010000000000000))
  42. #define VHA_CR_CLK_CTRL0_CNN_OIN_AUTO (IMG_UINT64_C(0x0020000000000000))
  43. #define VHA_CR_CLK_CTRL0_CNN_POOL_SHIFT (50U)
  44. #define VHA_CR_CLK_CTRL0_CNN_POOL_CLRMSK (IMG_UINT64_C(0XFFF3FFFFFFFFFFFF))
  45. #define VHA_CR_CLK_CTRL0_CNN_POOL_OFF (IMG_UINT64_C(0000000000000000))
  46. #define VHA_CR_CLK_CTRL0_CNN_POOL_ON (IMG_UINT64_C(0x0004000000000000))
  47. #define VHA_CR_CLK_CTRL0_CNN_POOL_AUTO (IMG_UINT64_C(0x0008000000000000))
  48. #define VHA_CR_CLK_CTRL0_CNN_SB_SHIFT (48U)
  49. #define VHA_CR_CLK_CTRL0_CNN_SB_CLRMSK (IMG_UINT64_C(0XFFFCFFFFFFFFFFFF))
  50. #define VHA_CR_CLK_CTRL0_CNN_SB_OFF (IMG_UINT64_C(0000000000000000))
  51. #define VHA_CR_CLK_CTRL0_CNN_SB_ON (IMG_UINT64_C(0x0001000000000000))
  52. #define VHA_CR_CLK_CTRL0_CNN_SB_AUTO (IMG_UINT64_C(0x0002000000000000))
  53. #define VHA_CR_CLK_CTRL0_CNN_XBAR_SHIFT (46U)
  54. #define VHA_CR_CLK_CTRL0_CNN_XBAR_CLRMSK (IMG_UINT64_C(0XFFFF3FFFFFFFFFFF))
  55. #define VHA_CR_CLK_CTRL0_CNN_XBAR_OFF (IMG_UINT64_C(0000000000000000))
  56. #define VHA_CR_CLK_CTRL0_CNN_XBAR_ON (IMG_UINT64_C(0x0000400000000000))
  57. #define VHA_CR_CLK_CTRL0_CNN_XBAR_AUTO (IMG_UINT64_C(0x0000800000000000))
  58. #define VHA_CR_CLK_CTRL0_CNN_NORM_SHIFT (44U)
  59. #define VHA_CR_CLK_CTRL0_CNN_NORM_CLRMSK (IMG_UINT64_C(0XFFFFCFFFFFFFFFFF))
  60. #define VHA_CR_CLK_CTRL0_CNN_NORM_OFF (IMG_UINT64_C(0000000000000000))
  61. #define VHA_CR_CLK_CTRL0_CNN_NORM_ON (IMG_UINT64_C(0x0000100000000000))
  62. #define VHA_CR_CLK_CTRL0_CNN_NORM_AUTO (IMG_UINT64_C(0x0000200000000000))
  63. #define VHA_CR_CLK_CTRL0_CNN_ACT_SHIFT (42U)
  64. #define VHA_CR_CLK_CTRL0_CNN_ACT_CLRMSK (IMG_UINT64_C(0XFFFFF3FFFFFFFFFF))
  65. #define VHA_CR_CLK_CTRL0_CNN_ACT_OFF (IMG_UINT64_C(0000000000000000))
  66. #define VHA_CR_CLK_CTRL0_CNN_ACT_ON (IMG_UINT64_C(0x0000040000000000))
  67. #define VHA_CR_CLK_CTRL0_CNN_ACT_AUTO (IMG_UINT64_C(0x0000080000000000))
  68. #define VHA_CR_CLK_CTRL0_CNN_ACCUM_SHIFT (40U)
  69. #define VHA_CR_CLK_CTRL0_CNN_ACCUM_CLRMSK (IMG_UINT64_C(0XFFFFFCFFFFFFFFFF))
  70. #define VHA_CR_CLK_CTRL0_CNN_ACCUM_OFF (IMG_UINT64_C(0000000000000000))
  71. #define VHA_CR_CLK_CTRL0_CNN_ACCUM_ON (IMG_UINT64_C(0x0000010000000000))
  72. #define VHA_CR_CLK_CTRL0_CNN_ACCUM_AUTO (IMG_UINT64_C(0x0000020000000000))
  73. #define VHA_CR_CLK_CTRL0_CNN_CNV_SHIFT (38U)
  74. #define VHA_CR_CLK_CTRL0_CNN_CNV_CLRMSK (IMG_UINT64_C(0XFFFFFF3FFFFFFFFF))
  75. #define VHA_CR_CLK_CTRL0_CNN_CNV_OFF (IMG_UINT64_C(0000000000000000))
  76. #define VHA_CR_CLK_CTRL0_CNN_CNV_ON (IMG_UINT64_C(0x0000004000000000))
  77. #define VHA_CR_CLK_CTRL0_CNN_CNV_AUTO (IMG_UINT64_C(0x0000008000000000))
  78. #define VHA_CR_CLK_CTRL0_CNN_CBUF_SHIFT (36U)
  79. #define VHA_CR_CLK_CTRL0_CNN_CBUF_CLRMSK (IMG_UINT64_C(0XFFFFFFCFFFFFFFFF))
  80. #define VHA_CR_CLK_CTRL0_CNN_CBUF_OFF (IMG_UINT64_C(0000000000000000))
  81. #define VHA_CR_CLK_CTRL0_CNN_CBUF_ON (IMG_UINT64_C(0x0000001000000000))
  82. #define VHA_CR_CLK_CTRL0_CNN_CBUF_AUTO (IMG_UINT64_C(0x0000002000000000))
  83. #define VHA_CR_CLK_CTRL0_CNN_IBUF_SHIFT (34U)
  84. #define VHA_CR_CLK_CTRL0_CNN_IBUF_CLRMSK (IMG_UINT64_C(0XFFFFFFF3FFFFFFFF))
  85. #define VHA_CR_CLK_CTRL0_CNN_IBUF_OFF (IMG_UINT64_C(0000000000000000))
  86. #define VHA_CR_CLK_CTRL0_CNN_IBUF_ON (IMG_UINT64_C(0x0000000400000000))
  87. #define VHA_CR_CLK_CTRL0_CNN_IBUF_AUTO (IMG_UINT64_C(0x0000000800000000))
  88. #define VHA_CR_CLK_CTRL0_CNN_CMD_SHIFT (32U)
  89. #define VHA_CR_CLK_CTRL0_CNN_CMD_CLRMSK (IMG_UINT64_C(0XFFFFFFFCFFFFFFFF))
  90. #define VHA_CR_CLK_CTRL0_CNN_CMD_OFF (IMG_UINT64_C(0000000000000000))
  91. #define VHA_CR_CLK_CTRL0_CNN_CMD_ON (IMG_UINT64_C(0x0000000100000000))
  92. #define VHA_CR_CLK_CTRL0_CNN_CMD_AUTO (IMG_UINT64_C(0x0000000200000000))
  93. #define VHA_CR_CLK_CTRL0_CNN_SHIFT (28U)
  94. #define VHA_CR_CLK_CTRL0_CNN_CLRMSK (IMG_UINT64_C(0XFFFFFFFFCFFFFFFF))
  95. #define VHA_CR_CLK_CTRL0_CNN_OFF (IMG_UINT64_C(0000000000000000))
  96. #define VHA_CR_CLK_CTRL0_CNN_ON (IMG_UINT64_C(0x0000000010000000))
  97. #define VHA_CR_CLK_CTRL0_CNN_AUTO (IMG_UINT64_C(0x0000000020000000))
  98. #define VHA_CR_CLK_CTRL0_SLC_SHIFT (8U)
  99. #define VHA_CR_CLK_CTRL0_SLC_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFCFF))
  100. #define VHA_CR_CLK_CTRL0_SLC_OFF (IMG_UINT64_C(0000000000000000))
  101. #define VHA_CR_CLK_CTRL0_SLC_ON (IMG_UINT64_C(0x0000000000000100))
  102. #define VHA_CR_CLK_CTRL0_SLC_AUTO (IMG_UINT64_C(0x0000000000000200))
  103. #define VHA_CR_CLK_CTRL0_BIF_SHIFT (4U)
  104. #define VHA_CR_CLK_CTRL0_BIF_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFCF))
  105. #define VHA_CR_CLK_CTRL0_BIF_OFF (IMG_UINT64_C(0000000000000000))
  106. #define VHA_CR_CLK_CTRL0_BIF_ON (IMG_UINT64_C(0x0000000000000010))
  107. #define VHA_CR_CLK_CTRL0_BIF_AUTO (IMG_UINT64_C(0x0000000000000020))
  108. /*
  109. Clock is gated and the module is inactive */
  110. #define VHA_CR_CLK_STATUS0_MODE_GATED (0x00000000U)
  111. /*
  112. Clock is running */
  113. #define VHA_CR_CLK_STATUS0_MODE_RUNNING (0x00000001U)
  114. /*
  115. Register VHA_CR_CLK_STATUS0
  116. */
  117. #define VHA_CR_CLK_STATUS0 (0x0008U)
  118. #define VHA_CR_CLK_STATUS0_MASKFULL (IMG_UINT64_C(0x00000007FFD00104))
  119. #define VHA_CR_CLK_STATUS0_CNN_EWO_SHIFT (34U)
  120. #define VHA_CR_CLK_STATUS0_CNN_EWO_CLRMSK (IMG_UINT64_C(0XFFFFFFFBFFFFFFFF))
  121. #define VHA_CR_CLK_STATUS0_CNN_EWO_GATED (IMG_UINT64_C(0000000000000000))
  122. #define VHA_CR_CLK_STATUS0_CNN_EWO_RUNNING (IMG_UINT64_C(0x0000000400000000))
  123. #define VHA_CR_CLK_STATUS0_CNN_PACK_SHIFT (33U)
  124. #define VHA_CR_CLK_STATUS0_CNN_PACK_CLRMSK (IMG_UINT64_C(0XFFFFFFFDFFFFFFFF))
  125. #define VHA_CR_CLK_STATUS0_CNN_PACK_GATED (IMG_UINT64_C(0000000000000000))
  126. #define VHA_CR_CLK_STATUS0_CNN_PACK_RUNNING (IMG_UINT64_C(0x0000000200000000))
  127. #define VHA_CR_CLK_STATUS0_CNN_OIN_SHIFT (32U)
  128. #define VHA_CR_CLK_STATUS0_CNN_OIN_CLRMSK (IMG_UINT64_C(0XFFFFFFFEFFFFFFFF))
  129. #define VHA_CR_CLK_STATUS0_CNN_OIN_GATED (IMG_UINT64_C(0000000000000000))
  130. #define VHA_CR_CLK_STATUS0_CNN_OIN_RUNNING (IMG_UINT64_C(0x0000000100000000))
  131. #define VHA_CR_CLK_STATUS0_CNN_POOL_SHIFT (31U)
  132. #define VHA_CR_CLK_STATUS0_CNN_POOL_CLRMSK (IMG_UINT64_C(0XFFFFFFFF7FFFFFFF))
  133. #define VHA_CR_CLK_STATUS0_CNN_POOL_GATED (IMG_UINT64_C(0000000000000000))
  134. #define VHA_CR_CLK_STATUS0_CNN_POOL_RUNNING (IMG_UINT64_C(0x0000000080000000))
  135. #define VHA_CR_CLK_STATUS0_CNN_SB_SHIFT (30U)
  136. #define VHA_CR_CLK_STATUS0_CNN_SB_CLRMSK (IMG_UINT64_C(0XFFFFFFFFBFFFFFFF))
  137. #define VHA_CR_CLK_STATUS0_CNN_SB_GATED (IMG_UINT64_C(0000000000000000))
  138. #define VHA_CR_CLK_STATUS0_CNN_SB_RUNNING (IMG_UINT64_C(0x0000000040000000))
  139. #define VHA_CR_CLK_STATUS0_CNN_XBAR_SHIFT (29U)
  140. #define VHA_CR_CLK_STATUS0_CNN_XBAR_CLRMSK (IMG_UINT64_C(0XFFFFFFFFDFFFFFFF))
  141. #define VHA_CR_CLK_STATUS0_CNN_XBAR_GATED (IMG_UINT64_C(0000000000000000))
  142. #define VHA_CR_CLK_STATUS0_CNN_XBAR_RUNNING (IMG_UINT64_C(0x0000000020000000))
  143. #define VHA_CR_CLK_STATUS0_CNN_NORM_SHIFT (28U)
  144. #define VHA_CR_CLK_STATUS0_CNN_NORM_CLRMSK (IMG_UINT64_C(0XFFFFFFFFEFFFFFFF))
  145. #define VHA_CR_CLK_STATUS0_CNN_NORM_GATED (IMG_UINT64_C(0000000000000000))
  146. #define VHA_CR_CLK_STATUS0_CNN_NORM_RUNNING (IMG_UINT64_C(0x0000000010000000))
  147. #define VHA_CR_CLK_STATUS0_CNN_ACT_SHIFT (27U)
  148. #define VHA_CR_CLK_STATUS0_CNN_ACT_CLRMSK (IMG_UINT64_C(0XFFFFFFFFF7FFFFFF))
  149. #define VHA_CR_CLK_STATUS0_CNN_ACT_GATED (IMG_UINT64_C(0000000000000000))
  150. #define VHA_CR_CLK_STATUS0_CNN_ACT_RUNNING (IMG_UINT64_C(0x0000000008000000))
  151. #define VHA_CR_CLK_STATUS0_CNN_ACCUM_SHIFT (26U)
  152. #define VHA_CR_CLK_STATUS0_CNN_ACCUM_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFBFFFFFF))
  153. #define VHA_CR_CLK_STATUS0_CNN_ACCUM_GATED (IMG_UINT64_C(0000000000000000))
  154. #define VHA_CR_CLK_STATUS0_CNN_ACCUM_RUNNING (IMG_UINT64_C(0x0000000004000000))
  155. #define VHA_CR_CLK_STATUS0_CNN_CNV_SHIFT (25U)
  156. #define VHA_CR_CLK_STATUS0_CNN_CNV_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFDFFFFFF))
  157. #define VHA_CR_CLK_STATUS0_CNN_CNV_GATED (IMG_UINT64_C(0000000000000000))
  158. #define VHA_CR_CLK_STATUS0_CNN_CNV_RUNNING (IMG_UINT64_C(0x0000000002000000))
  159. #define VHA_CR_CLK_STATUS0_CNN_CBUF_SHIFT (24U)
  160. #define VHA_CR_CLK_STATUS0_CNN_CBUF_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFEFFFFFF))
  161. #define VHA_CR_CLK_STATUS0_CNN_CBUF_GATED (IMG_UINT64_C(0000000000000000))
  162. #define VHA_CR_CLK_STATUS0_CNN_CBUF_RUNNING (IMG_UINT64_C(0x0000000001000000))
  163. #define VHA_CR_CLK_STATUS0_CNN_IBUF_SHIFT (23U)
  164. #define VHA_CR_CLK_STATUS0_CNN_IBUF_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFF7FFFFF))
  165. #define VHA_CR_CLK_STATUS0_CNN_IBUF_GATED (IMG_UINT64_C(0000000000000000))
  166. #define VHA_CR_CLK_STATUS0_CNN_IBUF_RUNNING (IMG_UINT64_C(0x0000000000800000))
  167. #define VHA_CR_CLK_STATUS0_CNN_CMD_SHIFT (22U)
  168. #define VHA_CR_CLK_STATUS0_CNN_CMD_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFBFFFFF))
  169. #define VHA_CR_CLK_STATUS0_CNN_CMD_GATED (IMG_UINT64_C(0000000000000000))
  170. #define VHA_CR_CLK_STATUS0_CNN_CMD_RUNNING (IMG_UINT64_C(0x0000000000400000))
  171. #define VHA_CR_CLK_STATUS0_CNN_SHIFT (20U)
  172. #define VHA_CR_CLK_STATUS0_CNN_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFEFFFFF))
  173. #define VHA_CR_CLK_STATUS0_CNN_GATED (IMG_UINT64_C(0000000000000000))
  174. #define VHA_CR_CLK_STATUS0_CNN_RUNNING (IMG_UINT64_C(0x0000000000100000))
  175. #define VHA_CR_CLK_STATUS0_SLC_SHIFT (8U)
  176. #define VHA_CR_CLK_STATUS0_SLC_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFEFF))
  177. #define VHA_CR_CLK_STATUS0_SLC_GATED (IMG_UINT64_C(0000000000000000))
  178. #define VHA_CR_CLK_STATUS0_SLC_RUNNING (IMG_UINT64_C(0x0000000000000100))
  179. #define VHA_CR_CLK_STATUS0_BIF_SHIFT (2U)
  180. #define VHA_CR_CLK_STATUS0_BIF_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFB))
  181. #define VHA_CR_CLK_STATUS0_BIF_GATED (IMG_UINT64_C(0000000000000000))
  182. #define VHA_CR_CLK_STATUS0_BIF_RUNNING (IMG_UINT64_C(0x0000000000000004))
  183. /*
  184. Register VHA_CR_PRODUCT_ID
  185. */
  186. #define VHA_CR_PRODUCT_ID (0x0018U)
  187. #define VHA_CR_PRODUCT_ID_MASKFULL (IMG_UINT64_C(0x00000000FFFF0000))
  188. #define VHA_CR_PRODUCT_ID_IMG_PRODUCT_ID_SHIFT (16U)
  189. #define VHA_CR_PRODUCT_ID_IMG_PRODUCT_ID_CLRMSK (IMG_UINT64_C(0XFFFFFFFF0000FFFF))
  190. /*
  191. Register VHA_CR_CORE_ID
  192. */
  193. #define VHA_CR_CORE_ID (0x0020U)
  194. #define VHA_CR_CORE_ID_MASKFULL (IMG_UINT64_C(0xFFFFFFFFFFFFFFFF))
  195. #define VHA_CR_CORE_ID_BRANCH_ID_SHIFT (48U)
  196. #define VHA_CR_CORE_ID_BRANCH_ID_CLRMSK (IMG_UINT64_C(0X0000FFFFFFFFFFFF))
  197. #define VHA_CR_CORE_ID_VERSION_ID_SHIFT (32U)
  198. #define VHA_CR_CORE_ID_VERSION_ID_CLRMSK (IMG_UINT64_C(0XFFFF0000FFFFFFFF))
  199. #define VHA_CR_CORE_ID_NUMBER_OF_SCALABLE_UNITS_SHIFT (16U)
  200. #define VHA_CR_CORE_ID_NUMBER_OF_SCALABLE_UNITS_CLRMSK (IMG_UINT64_C(0XFFFFFFFF0000FFFF))
  201. #define VHA_CR_CORE_ID_CONFIG_ID_SHIFT (0U)
  202. #define VHA_CR_CORE_ID_CONFIG_ID_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFF0000))
  203. /*
  204. Register VHA_CR_CORE_IP_INTEGRATOR_ID
  205. */
  206. #define VHA_CR_CORE_IP_INTEGRATOR_ID (0x0028U)
  207. #define VHA_CR_CORE_IP_INTEGRATOR_ID_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  208. #define VHA_CR_CORE_IP_INTEGRATOR_ID_VALUE_SHIFT (0U)
  209. #define VHA_CR_CORE_IP_INTEGRATOR_ID_VALUE_CLRMSK (IMG_UINT64_C(0XFFFFFFFF00000000))
  210. /*
  211. Register VHA_CR_CORE_IP_CHANGELIST
  212. */
  213. #define VHA_CR_CORE_IP_CHANGELIST (0x0030U)
  214. #define VHA_CR_CORE_IP_CHANGELIST_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  215. #define VHA_CR_CORE_IP_CHANGELIST_VALUE_SHIFT (0U)
  216. #define VHA_CR_CORE_IP_CHANGELIST_VALUE_CLRMSK (IMG_UINT64_C(0XFFFFFFFF00000000))
  217. /*
  218. Register VHA_CR_CORE_IP_CONFIG
  219. */
  220. #define VHA_CR_CORE_IP_CONFIG (0x0038U)
  221. #define VHA_CR_CORE_IP_CONFIG_MASKFULL (IMG_UINT64_C(0x0000000000000F03))
  222. #define VHA_CR_CORE_IP_CONFIG_SIGNATURES_SUPPORTED_SUBSET_SHIFT (11U)
  223. #define VHA_CR_CORE_IP_CONFIG_SIGNATURES_SUPPORTED_SUBSET_CLRMSK (0XFFFFF7FFU)
  224. #define VHA_CR_CORE_IP_CONFIG_SIGNATURES_SUPPORTED_SUBSET_EN (0X00000800U)
  225. #define VHA_CR_CORE_IP_CONFIG_SIGNATURES_SUPPORTED_ALL_SHIFT (10U)
  226. #define VHA_CR_CORE_IP_CONFIG_SIGNATURES_SUPPORTED_ALL_CLRMSK (0XFFFFFBFFU)
  227. #define VHA_CR_CORE_IP_CONFIG_SIGNATURES_SUPPORTED_ALL_EN (0X00000400U)
  228. #define VHA_CR_CORE_IP_CONFIG_RANDOM_STALLERS_SUPPORTED_SHIFT (9U)
  229. #define VHA_CR_CORE_IP_CONFIG_RANDOM_STALLERS_SUPPORTED_CLRMSK (0XFFFFFDFFU)
  230. #define VHA_CR_CORE_IP_CONFIG_RANDOM_STALLERS_SUPPORTED_EN (0X00000200U)
  231. #define VHA_CR_CORE_IP_CONFIG_RTM_SUPPORTED_SHIFT (8U)
  232. #define VHA_CR_CORE_IP_CONFIG_RTM_SUPPORTED_CLRMSK (0XFFFFFEFFU)
  233. #define VHA_CR_CORE_IP_CONFIG_RTM_SUPPORTED_EN (0X00000100U)
  234. #define VHA_CR_CORE_IP_CONFIG_SCL_SUPPORTED_SHIFT (1U)
  235. #define VHA_CR_CORE_IP_CONFIG_SCL_SUPPORTED_CLRMSK (0XFFFFFFFDU)
  236. #define VHA_CR_CORE_IP_CONFIG_SCL_SUPPORTED_EN (0X00000002U)
  237. #define VHA_CR_CORE_IP_CONFIG_CNN_SUPPORTED_SHIFT (0U)
  238. #define VHA_CR_CORE_IP_CONFIG_CNN_SUPPORTED_CLRMSK (0XFFFFFFFEU)
  239. #define VHA_CR_CORE_IP_CONFIG_CNN_SUPPORTED_EN (0X00000001U)
  240. /*
  241. Register VHA_CR_VHA_AXI_RESET_CTRL
  242. */
  243. #define VHA_CR_VHA_AXI_RESET_CTRL (0x0078U)
  244. #define VHA_CR_VHA_AXI_RESET_CTRL_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  245. #define VHA_CR_VHA_AXI_RESET_CTRL_SOFT_RESET_CYCLES_SHIFT (0U)
  246. #define VHA_CR_VHA_AXI_RESET_CTRL_SOFT_RESET_CYCLES_CLRMSK (00000000U)
  247. /*
  248. Register VHA_CR_RESET_CTRL
  249. */
  250. #define VHA_CR_RESET_CTRL (0x0080U)
  251. #define VHA_CR_RESET_CTRL_MASKFULL (IMG_UINT64_C(0x00000000C0000107))
  252. #define VHA_CR_RESET_CTRL_VHA_SYS_SOFT_RESET_SHIFT (31U)
  253. #define VHA_CR_RESET_CTRL_VHA_SYS_SOFT_RESET_CLRMSK (0X7FFFFFFFU)
  254. #define VHA_CR_RESET_CTRL_VHA_SYS_SOFT_RESET_EN (0X80000000U)
  255. #define VHA_CR_RESET_CTRL_VHA_AXI_SOFT_RESET_SHIFT (30U)
  256. #define VHA_CR_RESET_CTRL_VHA_AXI_SOFT_RESET_CLRMSK (0XBFFFFFFFU)
  257. #define VHA_CR_RESET_CTRL_VHA_AXI_SOFT_RESET_EN (0X40000000U)
  258. #define VHA_CR_RESET_CTRL_VHA_CNN0_SOFT_RESET_SHIFT (8U)
  259. #define VHA_CR_RESET_CTRL_VHA_CNN0_SOFT_RESET_CLRMSK (0XFFFFFEFFU)
  260. #define VHA_CR_RESET_CTRL_VHA_CNN0_SOFT_RESET_EN (0X00000100U)
  261. #define VHA_CR_RESET_CTRL_VHA_SLC_SOFT_RESET_SHIFT (2U)
  262. #define VHA_CR_RESET_CTRL_VHA_SLC_SOFT_RESET_CLRMSK (0XFFFFFFFBU)
  263. #define VHA_CR_RESET_CTRL_VHA_SLC_SOFT_RESET_EN (0X00000004U)
  264. #define VHA_CR_RESET_CTRL_VHA_BIF_SOFT_RESET_SHIFT (1U)
  265. #define VHA_CR_RESET_CTRL_VHA_BIF_SOFT_RESET_CLRMSK (0XFFFFFFFDU)
  266. #define VHA_CR_RESET_CTRL_VHA_BIF_SOFT_RESET_EN (0X00000002U)
  267. #define VHA_CR_RESET_CTRL_VHA_SOFT_RESET_SHIFT (0U)
  268. #define VHA_CR_RESET_CTRL_VHA_SOFT_RESET_CLRMSK (0XFFFFFFFEU)
  269. #define VHA_CR_RESET_CTRL_VHA_SOFT_RESET_EN (0X00000001U)
  270. #define VHA_CR_VHA_EVENT_TYPE_VHA_AXI_ERROR_SHIFT (18U)
  271. #define VHA_CR_VHA_EVENT_TYPE_VHA_AXI_ERROR_CLRMSK (0XFFFBFFFFU)
  272. #define VHA_CR_VHA_EVENT_TYPE_VHA_AXI_ERROR_EN (0X00040000U)
  273. #define VHA_CR_VHA_EVENT_TYPE_VHA_MMU_PAGE_FAULT_SHIFT (16U)
  274. #define VHA_CR_VHA_EVENT_TYPE_VHA_MMU_PAGE_FAULT_CLRMSK (0XFFFEFFFFU)
  275. #define VHA_CR_VHA_EVENT_TYPE_VHA_MMU_PAGE_FAULT_EN (0X00010000U)
  276. #define VHA_CR_VHA_EVENT_TYPE_VHA_CNN0_MEM_WDT_SHIFT (3U)
  277. #define VHA_CR_VHA_EVENT_TYPE_VHA_CNN0_MEM_WDT_CLRMSK (0XFFFFFFF7U)
  278. #define VHA_CR_VHA_EVENT_TYPE_VHA_CNN0_MEM_WDT_EN (0X00000008U)
  279. #define VHA_CR_VHA_EVENT_TYPE_VHA_CNN0_WDT_SHIFT (2U)
  280. #define VHA_CR_VHA_EVENT_TYPE_VHA_CNN0_WDT_CLRMSK (0XFFFFFFFBU)
  281. #define VHA_CR_VHA_EVENT_TYPE_VHA_CNN0_WDT_EN (0X00000004U)
  282. #define VHA_CR_VHA_EVENT_TYPE_VHA_CNN0_ERROR_SHIFT (1U)
  283. #define VHA_CR_VHA_EVENT_TYPE_VHA_CNN0_ERROR_CLRMSK (0XFFFFFFFDU)
  284. #define VHA_CR_VHA_EVENT_TYPE_VHA_CNN0_ERROR_EN (0X00000002U)
  285. #define VHA_CR_VHA_EVENT_TYPE_VHA_CNN0_COMPLETE_SHIFT (0U)
  286. #define VHA_CR_VHA_EVENT_TYPE_VHA_CNN0_COMPLETE_CLRMSK (0XFFFFFFFEU)
  287. #define VHA_CR_VHA_EVENT_TYPE_VHA_CNN0_COMPLETE_EN (0X00000001U)
  288. /*
  289. Register VHA_CR_OS0_VHA_EVENT_ENABLE
  290. */
  291. #define VHA_CR_OS0_VHA_EVENT_ENABLE (0x0088U)
  292. #define VHA_CR_OS0_VHA_EVENT_ENABLE_MASKFULL (IMG_UINT64_C(0x000000000005000F))
  293. #define VHA_CR_OS0_VHA_EVENT_ENABLE_VHA_AXI_ERROR_SHIFT (18U)
  294. #define VHA_CR_OS0_VHA_EVENT_ENABLE_VHA_AXI_ERROR_CLRMSK (0XFFFBFFFFU)
  295. #define VHA_CR_OS0_VHA_EVENT_ENABLE_VHA_AXI_ERROR_EN (0X00040000U)
  296. #define VHA_CR_OS0_VHA_EVENT_ENABLE_VHA_MMU_PAGE_FAULT_SHIFT (16U)
  297. #define VHA_CR_OS0_VHA_EVENT_ENABLE_VHA_MMU_PAGE_FAULT_CLRMSK (0XFFFEFFFFU)
  298. #define VHA_CR_OS0_VHA_EVENT_ENABLE_VHA_MMU_PAGE_FAULT_EN (0X00010000U)
  299. #define VHA_CR_OS0_VHA_EVENT_ENABLE_VHA_CNN0_MEM_WDT_SHIFT (3U)
  300. #define VHA_CR_OS0_VHA_EVENT_ENABLE_VHA_CNN0_MEM_WDT_CLRMSK (0XFFFFFFF7U)
  301. #define VHA_CR_OS0_VHA_EVENT_ENABLE_VHA_CNN0_MEM_WDT_EN (0X00000008U)
  302. #define VHA_CR_OS0_VHA_EVENT_ENABLE_VHA_CNN0_WDT_SHIFT (2U)
  303. #define VHA_CR_OS0_VHA_EVENT_ENABLE_VHA_CNN0_WDT_CLRMSK (0XFFFFFFFBU)
  304. #define VHA_CR_OS0_VHA_EVENT_ENABLE_VHA_CNN0_WDT_EN (0X00000004U)
  305. #define VHA_CR_OS0_VHA_EVENT_ENABLE_VHA_CNN0_ERROR_SHIFT (1U)
  306. #define VHA_CR_OS0_VHA_EVENT_ENABLE_VHA_CNN0_ERROR_CLRMSK (0XFFFFFFFDU)
  307. #define VHA_CR_OS0_VHA_EVENT_ENABLE_VHA_CNN0_ERROR_EN (0X00000002U)
  308. #define VHA_CR_OS0_VHA_EVENT_ENABLE_VHA_CNN0_COMPLETE_SHIFT (0U)
  309. #define VHA_CR_OS0_VHA_EVENT_ENABLE_VHA_CNN0_COMPLETE_CLRMSK (0XFFFFFFFEU)
  310. #define VHA_CR_OS0_VHA_EVENT_ENABLE_VHA_CNN0_COMPLETE_EN (0X00000001U)
  311. /*
  312. Register VHA_CR_OS0_VHA_EVENT_STATUS
  313. */
  314. #define VHA_CR_OS0_VHA_EVENT_STATUS (0x0090U)
  315. #define VHA_CR_OS0_VHA_EVENT_STATUS_MASKFULL (IMG_UINT64_C(0x000000000005000F))
  316. #define VHA_CR_OS0_VHA_EVENT_STATUS_VHA_AXI_ERROR_SHIFT (18U)
  317. #define VHA_CR_OS0_VHA_EVENT_STATUS_VHA_AXI_ERROR_CLRMSK (0XFFFBFFFFU)
  318. #define VHA_CR_OS0_VHA_EVENT_STATUS_VHA_AXI_ERROR_EN (0X00040000U)
  319. #define VHA_CR_OS0_VHA_EVENT_STATUS_VHA_MMU_PAGE_FAULT_SHIFT (16U)
  320. #define VHA_CR_OS0_VHA_EVENT_STATUS_VHA_MMU_PAGE_FAULT_CLRMSK (0XFFFEFFFFU)
  321. #define VHA_CR_OS0_VHA_EVENT_STATUS_VHA_MMU_PAGE_FAULT_EN (0X00010000U)
  322. #define VHA_CR_OS0_VHA_EVENT_STATUS_VHA_CNN0_MEM_WDT_SHIFT (3U)
  323. #define VHA_CR_OS0_VHA_EVENT_STATUS_VHA_CNN0_MEM_WDT_CLRMSK (0XFFFFFFF7U)
  324. #define VHA_CR_OS0_VHA_EVENT_STATUS_VHA_CNN0_MEM_WDT_EN (0X00000008U)
  325. #define VHA_CR_OS0_VHA_EVENT_STATUS_VHA_CNN0_WDT_SHIFT (2U)
  326. #define VHA_CR_OS0_VHA_EVENT_STATUS_VHA_CNN0_WDT_CLRMSK (0XFFFFFFFBU)
  327. #define VHA_CR_OS0_VHA_EVENT_STATUS_VHA_CNN0_WDT_EN (0X00000004U)
  328. #define VHA_CR_OS0_VHA_EVENT_STATUS_VHA_CNN0_ERROR_SHIFT (1U)
  329. #define VHA_CR_OS0_VHA_EVENT_STATUS_VHA_CNN0_ERROR_CLRMSK (0XFFFFFFFDU)
  330. #define VHA_CR_OS0_VHA_EVENT_STATUS_VHA_CNN0_ERROR_EN (0X00000002U)
  331. #define VHA_CR_OS0_VHA_EVENT_STATUS_VHA_CNN0_COMPLETE_SHIFT (0U)
  332. #define VHA_CR_OS0_VHA_EVENT_STATUS_VHA_CNN0_COMPLETE_CLRMSK (0XFFFFFFFEU)
  333. #define VHA_CR_OS0_VHA_EVENT_STATUS_VHA_CNN0_COMPLETE_EN (0X00000001U)
  334. /*
  335. Register VHA_CR_OS0_VHA_EVENT_CLEAR
  336. */
  337. #define VHA_CR_OS0_VHA_EVENT_CLEAR (0x0098U)
  338. #define VHA_CR_OS0_VHA_EVENT_CLEAR_MASKFULL (IMG_UINT64_C(0x000000000005000F))
  339. #define VHA_CR_OS0_VHA_EVENT_CLEAR_VHA_AXI_ERROR_SHIFT (18U)
  340. #define VHA_CR_OS0_VHA_EVENT_CLEAR_VHA_AXI_ERROR_CLRMSK (0XFFFBFFFFU)
  341. #define VHA_CR_OS0_VHA_EVENT_CLEAR_VHA_AXI_ERROR_EN (0X00040000U)
  342. #define VHA_CR_OS0_VHA_EVENT_CLEAR_VHA_MMU_PAGE_FAULT_SHIFT (16U)
  343. #define VHA_CR_OS0_VHA_EVENT_CLEAR_VHA_MMU_PAGE_FAULT_CLRMSK (0XFFFEFFFFU)
  344. #define VHA_CR_OS0_VHA_EVENT_CLEAR_VHA_MMU_PAGE_FAULT_EN (0X00010000U)
  345. #define VHA_CR_OS0_VHA_EVENT_CLEAR_VHA_CNN0_MEM_WDT_SHIFT (3U)
  346. #define VHA_CR_OS0_VHA_EVENT_CLEAR_VHA_CNN0_MEM_WDT_CLRMSK (0XFFFFFFF7U)
  347. #define VHA_CR_OS0_VHA_EVENT_CLEAR_VHA_CNN0_MEM_WDT_EN (0X00000008U)
  348. #define VHA_CR_OS0_VHA_EVENT_CLEAR_VHA_CNN0_WDT_SHIFT (2U)
  349. #define VHA_CR_OS0_VHA_EVENT_CLEAR_VHA_CNN0_WDT_CLRMSK (0XFFFFFFFBU)
  350. #define VHA_CR_OS0_VHA_EVENT_CLEAR_VHA_CNN0_WDT_EN (0X00000004U)
  351. #define VHA_CR_OS0_VHA_EVENT_CLEAR_VHA_CNN0_ERROR_SHIFT (1U)
  352. #define VHA_CR_OS0_VHA_EVENT_CLEAR_VHA_CNN0_ERROR_CLRMSK (0XFFFFFFFDU)
  353. #define VHA_CR_OS0_VHA_EVENT_CLEAR_VHA_CNN0_ERROR_EN (0X00000002U)
  354. #define VHA_CR_OS0_VHA_EVENT_CLEAR_VHA_CNN0_COMPLETE_SHIFT (0U)
  355. #define VHA_CR_OS0_VHA_EVENT_CLEAR_VHA_CNN0_COMPLETE_CLRMSK (0XFFFFFFFEU)
  356. #define VHA_CR_OS0_VHA_EVENT_CLEAR_VHA_CNN0_COMPLETE_EN (0X00000001U)
  357. #define VHA_CR_SYS_CLK_CTRL0_MODE_MASK (0x00000003U)
  358. /*
  359. The domain clock is forced off */
  360. #define VHA_CR_SYS_CLK_CTRL0_MODE_OFF (0x00000000U)
  361. /*
  362. The domain clock is forced on */
  363. #define VHA_CR_SYS_CLK_CTRL0_MODE_ON (0x00000001U)
  364. /*
  365. Automatic clock gating is active, the domain clock is only on whilst data is being processed */
  366. #define VHA_CR_SYS_CLK_CTRL0_MODE_AUTO (0x00000002U)
  367. /*
  368. Register VHA_CR_SYS_CLK_CTRL0
  369. */
  370. #define VHA_CR_SYS_CLK_CTRL0 (0x2000U)
  371. #define VHA_CR_SYS_CLK_CTRL0_MASKFULL (IMG_UINT64_C(0x0000000000000030))
  372. #define VHA_CR_SYS_CLK_CTRL0_SLC_SHIFT (4U)
  373. #define VHA_CR_SYS_CLK_CTRL0_SLC_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFCF))
  374. #define VHA_CR_SYS_CLK_CTRL0_SLC_OFF (IMG_UINT64_C(0000000000000000))
  375. #define VHA_CR_SYS_CLK_CTRL0_SLC_ON (IMG_UINT64_C(0x0000000000000010))
  376. #define VHA_CR_SYS_CLK_CTRL0_SLC_AUTO (IMG_UINT64_C(0x0000000000000020))
  377. /*
  378. Clock is gated and the module is inactive */
  379. #define VHA_CR_SYS_CLK_STATUS0_MODE_GATED (0x00000000U)
  380. /*
  381. Clock is running */
  382. #define VHA_CR_SYS_CLK_STATUS0_MODE_RUNNING (0x00000001U)
  383. /*
  384. Register VHA_CR_SYS_CLK_STATUS0
  385. */
  386. #define VHA_CR_SYS_CLK_STATUS0 (0x2008U)
  387. #define VHA_CR_SYS_CLK_STATUS0_MASKFULL (IMG_UINT64_C(0x0000000000000004))
  388. #define VHA_CR_SYS_CLK_STATUS0_SLC_SHIFT (2U)
  389. #define VHA_CR_SYS_CLK_STATUS0_SLC_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFB))
  390. #define VHA_CR_SYS_CLK_STATUS0_SLC_GATED (IMG_UINT64_C(0000000000000000))
  391. #define VHA_CR_SYS_CLK_STATUS0_SLC_RUNNING (IMG_UINT64_C(0x0000000000000004))
  392. /*
  393. Register VHA_CR_AXI_EXACCESS
  394. */
  395. #define VHA_CR_AXI_EXACCESS (0x2168U)
  396. #define VHA_CR_AXI_EXACCESS_MASKFULL (IMG_UINT64_C(0x0000000000000001))
  397. #define VHA_CR_AXI_EXACCESS_SOCIF_ENABLE_SHIFT (0U)
  398. #define VHA_CR_AXI_EXACCESS_SOCIF_ENABLE_CLRMSK (0XFFFFFFFEU)
  399. #define VHA_CR_AXI_EXACCESS_SOCIF_ENABLE_EN (0X00000001U)
  400. /*
  401. Register VHA_CR_MMU_HOST_IRQ_ENABLE
  402. */
  403. #define VHA_CR_MMU_HOST_IRQ_ENABLE (0xE1A0U)
  404. #define VHA_CR_MMU_HOST_IRQ_ENABLE_MASKFULL (IMG_UINT64_C(0x0000000000000001))
  405. #define VHA_CR_MMU_HOST_IRQ_ENABLE_FAULT_PM_SHIFT (0U)
  406. #define VHA_CR_MMU_HOST_IRQ_ENABLE_FAULT_PM_CLRMSK (0XFFFFFFFEU)
  407. #define VHA_CR_MMU_HOST_IRQ_ENABLE_FAULT_PM_EN (0X00000001U)
  408. /*
  409. Register VHA_CR_OS0_CNN_CONTROL
  410. */
  411. #define VHA_CR_OS0_CNN_CONTROL (0x0100U)
  412. #define VHA_CR_OS0_CNN_CONTROL_MASKFULL (IMG_UINT64_C(0x000000000000007F))
  413. #define VHA_CR_OS0_CNN_CONTROL_CMD_SIZE_MIN1_SHIFT (1U)
  414. #define VHA_CR_OS0_CNN_CONTROL_CMD_SIZE_MIN1_CLRMSK (0XFFFFFF81U)
  415. #define VHA_CR_OS0_CNN_CONTROL_START_SHIFT (0U)
  416. #define VHA_CR_OS0_CNN_CONTROL_START_CLRMSK (0XFFFFFFFEU)
  417. #define VHA_CR_OS0_CNN_CONTROL_START_EN (0X00000001U)
  418. /*
  419. Register VHA_CR_OS0_CNN_STATUS
  420. */
  421. #define VHA_CR_OS0_CNN_STATUS (0x0108U)
  422. #define VHA_CR_OS0_CNN_STATUS_MASKFULL (IMG_UINT64_C(0x0000000000FFFFFF))
  423. #define VHA_CR_OS0_CNN_STATUS_PASS_COUNT_SHIFT (16U)
  424. #define VHA_CR_OS0_CNN_STATUS_PASS_COUNT_CLRMSK (0XFF00FFFFU)
  425. #define VHA_CR_OS0_CNN_STATUS_LAYER_COUNT_SHIFT (8U)
  426. #define VHA_CR_OS0_CNN_STATUS_LAYER_COUNT_CLRMSK (0XFFFF00FFU)
  427. #define VHA_CR_OS0_CNN_STATUS_STREAM_COUNT_SHIFT (0U)
  428. #define VHA_CR_OS0_CNN_STATUS_STREAM_COUNT_CLRMSK (0XFFFFFF00U)
  429. /*
  430. Register VHA_CR_OS0_CNN_CMD_BASE_ADDRESS
  431. */
  432. #define VHA_CR_OS0_CNN_CMD_BASE_ADDRESS (0x0120U)
  433. #define VHA_CR_OS0_CNN_CMD_BASE_ADDRESS_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFF00))
  434. #define VHA_CR_OS0_CNN_CMD_BASE_ADDRESS_BASE_ADDR_SHIFT (8U)
  435. #define VHA_CR_OS0_CNN_CMD_BASE_ADDRESS_BASE_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF00000000FF))
  436. /*
  437. Register VHA_CR_OS0_CNN_ALT_ADDRESS_USED
  438. */
  439. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED (0x0138U)
  440. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_MASKFULL (IMG_UINT64_C(0x00000000000000FF))
  441. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR7_USED_SHIFT (7U)
  442. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR7_USED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFF7F))
  443. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR7_USED_EN (IMG_UINT64_C(0X0000000000000080))
  444. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR6_USED_SHIFT (6U)
  445. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR6_USED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFBF))
  446. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR6_USED_EN (IMG_UINT64_C(0X0000000000000040))
  447. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR5_USED_SHIFT (5U)
  448. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR5_USED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFDF))
  449. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR5_USED_EN (IMG_UINT64_C(0X0000000000000020))
  450. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR4_USED_SHIFT (4U)
  451. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR4_USED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFEF))
  452. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR4_USED_EN (IMG_UINT64_C(0X0000000000000010))
  453. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR3_USED_SHIFT (3U)
  454. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR3_USED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFF7))
  455. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR3_USED_EN (IMG_UINT64_C(0X0000000000000008))
  456. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR2_USED_SHIFT (2U)
  457. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR2_USED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFB))
  458. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR2_USED_EN (IMG_UINT64_C(0X0000000000000004))
  459. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR1_USED_SHIFT (1U)
  460. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR1_USED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFD))
  461. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR1_USED_EN (IMG_UINT64_C(0X0000000000000002))
  462. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR0_USED_SHIFT (0U)
  463. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR0_USED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFE))
  464. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR0_USED_EN (IMG_UINT64_C(0X0000000000000001))
  465. /*
  466. Register VHA_CR_OS0_CNN_ALT_ADDRESS0
  467. */
  468. #define VHA_CR_OS0_CNN_ALT_ADDRESS0 (0x0140U)
  469. #define VHA_CR_OS0_CNN_ALT_ADDRESS0_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFF00))
  470. #define VHA_CR_OS0_CNN_ALT_ADDRESS0_ALT_ADDR_SHIFT (8U)
  471. #define VHA_CR_OS0_CNN_ALT_ADDRESS0_ALT_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF00000000FF))
  472. /*
  473. Register VHA_CR_OS0_CNN_ALT_ADDRESS1
  474. */
  475. #define VHA_CR_OS0_CNN_ALT_ADDRESS1 (0x0148U)
  476. #define VHA_CR_OS0_CNN_ALT_ADDRESS1_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFF00))
  477. #define VHA_CR_OS0_CNN_ALT_ADDRESS1_ALT_ADDR_SHIFT (8U)
  478. #define VHA_CR_OS0_CNN_ALT_ADDRESS1_ALT_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF00000000FF))
  479. /*
  480. Register VHA_CR_OS0_CNN_ALT_ADDRESS2
  481. */
  482. #define VHA_CR_OS0_CNN_ALT_ADDRESS2 (0x0150U)
  483. #define VHA_CR_OS0_CNN_ALT_ADDRESS2_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFF00))
  484. #define VHA_CR_OS0_CNN_ALT_ADDRESS2_ALT_ADDR_SHIFT (8U)
  485. #define VHA_CR_OS0_CNN_ALT_ADDRESS2_ALT_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF00000000FF))
  486. /*
  487. Register VHA_CR_OS0_CNN_ALT_ADDRESS3
  488. */
  489. #define VHA_CR_OS0_CNN_ALT_ADDRESS3 (0x0158U)
  490. #define VHA_CR_OS0_CNN_ALT_ADDRESS3_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFF00))
  491. #define VHA_CR_OS0_CNN_ALT_ADDRESS3_ALT_ADDR_SHIFT (8U)
  492. #define VHA_CR_OS0_CNN_ALT_ADDRESS3_ALT_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF00000000FF))
  493. /*
  494. Register VHA_CR_OS0_CNN_ALT_ADDRESS4
  495. */
  496. #define VHA_CR_OS0_CNN_ALT_ADDRESS4 (0x0160U)
  497. #define VHA_CR_OS0_CNN_ALT_ADDRESS4_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFF00))
  498. #define VHA_CR_OS0_CNN_ALT_ADDRESS4_ALT_ADDR_SHIFT (8U)
  499. #define VHA_CR_OS0_CNN_ALT_ADDRESS4_ALT_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF00000000FF))
  500. /*
  501. Register VHA_CR_OS0_CNN_ALT_ADDRESS5
  502. */
  503. #define VHA_CR_OS0_CNN_ALT_ADDRESS5 (0x0168U)
  504. #define VHA_CR_OS0_CNN_ALT_ADDRESS5_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFF00))
  505. #define VHA_CR_OS0_CNN_ALT_ADDRESS5_ALT_ADDR_SHIFT (8U)
  506. #define VHA_CR_OS0_CNN_ALT_ADDRESS5_ALT_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF00000000FF))
  507. /*
  508. Register VHA_CR_OS0_CNN_ALT_ADDRESS6
  509. */
  510. #define VHA_CR_OS0_CNN_ALT_ADDRESS6 (0x0170U)
  511. #define VHA_CR_OS0_CNN_ALT_ADDRESS6_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFF00))
  512. #define VHA_CR_OS0_CNN_ALT_ADDRESS6_ALT_ADDR_SHIFT (8U)
  513. #define VHA_CR_OS0_CNN_ALT_ADDRESS6_ALT_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF00000000FF))
  514. /*
  515. Register VHA_CR_OS0_CNN_ALT_ADDRESS7
  516. */
  517. #define VHA_CR_OS0_CNN_ALT_ADDRESS7 (0x0178U)
  518. #define VHA_CR_OS0_CNN_ALT_ADDRESS7_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFF00))
  519. #define VHA_CR_OS0_CNN_ALT_ADDRESS7_ALT_ADDR_SHIFT (8U)
  520. #define VHA_CR_OS0_CNN_ALT_ADDRESS7_ALT_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF00000000FF))
  521. /*
  522. Register VHA_CR_OS0_CNN_WRITEBACK_CONTROL
  523. */
  524. #define VHA_CR_OS0_CNN_WRITEBACK_CONTROL (0x0180U)
  525. #define VHA_CR_OS0_CNN_WRITEBACK_CONTROL_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  526. #define VHA_CR_OS0_CNN_WRITEBACK_CONTROL_WRITE_BACK_VALUE_SHIFT (0U)
  527. #define VHA_CR_OS0_CNN_WRITEBACK_CONTROL_WRITE_BACK_VALUE_CLRMSK (00000000U)
  528. /*
  529. Register VHA_CR_CNN_CMD_MH_CONTROL
  530. */
  531. #define VHA_CR_CNN_CMD_MH_CONTROL (0x0200U)
  532. #define VHA_CR_CNN_CMD_MH_CONTROL_MASKFULL (IMG_UINT64_C(0x0000000000001F3F))
  533. #define VHA_CR_CNN_CMD_MH_CONTROL_CTXT_PASID_SHIFT (8U)
  534. #define VHA_CR_CNN_CMD_MH_CONTROL_CTXT_PASID_CLRMSK (0XFFFFE0FFU)
  535. #define VHA_CR_CNN_CMD_MH_CONTROL_MAX_BURST_LENGTH_SHIFT (4U)
  536. #define VHA_CR_CNN_CMD_MH_CONTROL_MAX_BURST_LENGTH_CLRMSK (0XFFFFFFCFU)
  537. #define VHA_CR_CNN_CMD_MH_CONTROL_GPU_PIPE_COHERENT_SHIFT (3U)
  538. #define VHA_CR_CNN_CMD_MH_CONTROL_GPU_PIPE_COHERENT_CLRMSK (0XFFFFFFF7U)
  539. #define VHA_CR_CNN_CMD_MH_CONTROL_GPU_PIPE_COHERENT_EN (0X00000008U)
  540. #define VHA_CR_CNN_CMD_MH_CONTROL_SLC_CACHE_POLICY_SHIFT (2U)
  541. #define VHA_CR_CNN_CMD_MH_CONTROL_SLC_CACHE_POLICY_CLRMSK (0XFFFFFFFBU)
  542. #define VHA_CR_CNN_CMD_MH_CONTROL_SLC_CACHE_POLICY_EN (0X00000004U)
  543. #define VHA_CR_CNN_CMD_MH_CONTROL_PERSISTENCE_SHIFT (0U)
  544. #define VHA_CR_CNN_CMD_MH_CONTROL_PERSISTENCE_CLRMSK (0XFFFFFFFCU)
  545. /*
  546. Register VHA_CR_CNN_IBUF_MH_CONTROL
  547. */
  548. #define VHA_CR_CNN_IBUF_MH_CONTROL (0x0208U)
  549. #define VHA_CR_CNN_IBUF_MH_CONTROL_MASKFULL (IMG_UINT64_C(0x000000000000001F))
  550. #define VHA_CR_CNN_IBUF_MH_CONTROL_MAX_BURST_LENGTH_SHIFT (3U)
  551. #define VHA_CR_CNN_IBUF_MH_CONTROL_MAX_BURST_LENGTH_CLRMSK (0XFFFFFFE7U)
  552. #define VHA_CR_CNN_IBUF_MH_CONTROL_GPU_PIPE_COHERENT_SHIFT (2U)
  553. #define VHA_CR_CNN_IBUF_MH_CONTROL_GPU_PIPE_COHERENT_CLRMSK (0XFFFFFFFBU)
  554. #define VHA_CR_CNN_IBUF_MH_CONTROL_GPU_PIPE_COHERENT_EN (0X00000004U)
  555. #define VHA_CR_CNN_IBUF_MH_CONTROL_PERSISTENCE_SHIFT (0U)
  556. #define VHA_CR_CNN_IBUF_MH_CONTROL_PERSISTENCE_CLRMSK (0XFFFFFFFCU)
  557. /*
  558. Register VHA_CR_CNN_CBUF_MH_CONTROL
  559. */
  560. #define VHA_CR_CNN_CBUF_MH_CONTROL (0x0210U)
  561. #define VHA_CR_CNN_CBUF_MH_CONTROL_MASKFULL (IMG_UINT64_C(0x000000000000001F))
  562. #define VHA_CR_CNN_CBUF_MH_CONTROL_MAX_BURST_LENGTH_SHIFT (3U)
  563. #define VHA_CR_CNN_CBUF_MH_CONTROL_MAX_BURST_LENGTH_CLRMSK (0XFFFFFFE7U)
  564. #define VHA_CR_CNN_CBUF_MH_CONTROL_GPU_PIPE_COHERENT_SHIFT (2U)
  565. #define VHA_CR_CNN_CBUF_MH_CONTROL_GPU_PIPE_COHERENT_CLRMSK (0XFFFFFFFBU)
  566. #define VHA_CR_CNN_CBUF_MH_CONTROL_GPU_PIPE_COHERENT_EN (0X00000004U)
  567. #define VHA_CR_CNN_CBUF_MH_CONTROL_PERSISTENCE_SHIFT (0U)
  568. #define VHA_CR_CNN_CBUF_MH_CONTROL_PERSISTENCE_CLRMSK (0XFFFFFFFCU)
  569. /*
  570. Register VHA_CR_CNN_ABUF_MH_CONTROL
  571. */
  572. #define VHA_CR_CNN_ABUF_MH_CONTROL (0x0218U)
  573. #define VHA_CR_CNN_ABUF_MH_CONTROL_MASKFULL (IMG_UINT64_C(0x000000000000001F))
  574. #define VHA_CR_CNN_ABUF_MH_CONTROL_MAX_BURST_LENGTH_SHIFT (3U)
  575. #define VHA_CR_CNN_ABUF_MH_CONTROL_MAX_BURST_LENGTH_CLRMSK (0XFFFFFFE7U)
  576. #define VHA_CR_CNN_ABUF_MH_CONTROL_GPU_PIPE_COHERENT_SHIFT (2U)
  577. #define VHA_CR_CNN_ABUF_MH_CONTROL_GPU_PIPE_COHERENT_CLRMSK (0XFFFFFFFBU)
  578. #define VHA_CR_CNN_ABUF_MH_CONTROL_GPU_PIPE_COHERENT_EN (0X00000004U)
  579. #define VHA_CR_CNN_ABUF_MH_CONTROL_PERSISTENCE_SHIFT (0U)
  580. #define VHA_CR_CNN_ABUF_MH_CONTROL_PERSISTENCE_CLRMSK (0XFFFFFFFCU)
  581. /*
  582. Register VHA_CR_CNN_OUTPACK_MH_CONTROL
  583. */
  584. #define VHA_CR_CNN_OUTPACK_MH_CONTROL (0x0220U)
  585. #define VHA_CR_CNN_OUTPACK_MH_CONTROL_MASKFULL (IMG_UINT64_C(0x000000000000001F))
  586. #define VHA_CR_CNN_OUTPACK_MH_CONTROL_MAX_BURST_LENGTH_SHIFT (3U)
  587. #define VHA_CR_CNN_OUTPACK_MH_CONTROL_MAX_BURST_LENGTH_CLRMSK (0XFFFFFFE7U)
  588. #define VHA_CR_CNN_OUTPACK_MH_CONTROL_GPU_PIPE_COHERENT_SHIFT (2U)
  589. #define VHA_CR_CNN_OUTPACK_MH_CONTROL_GPU_PIPE_COHERENT_CLRMSK (0XFFFFFFFBU)
  590. #define VHA_CR_CNN_OUTPACK_MH_CONTROL_GPU_PIPE_COHERENT_EN (0X00000004U)
  591. #define VHA_CR_CNN_OUTPACK_MH_CONTROL_PERSISTENCE_SHIFT (0U)
  592. #define VHA_CR_CNN_OUTPACK_MH_CONTROL_PERSISTENCE_CLRMSK (0XFFFFFFFCU)
  593. /*
  594. Register VHA_CR_CNN_ELEMENTOPS_MH_CONTROL
  595. */
  596. #define VHA_CR_CNN_ELEMENTOPS_MH_CONTROL (0x0228U)
  597. #define VHA_CR_CNN_ELEMENTOPS_MH_CONTROL_MASKFULL (IMG_UINT64_C(0x000000000000001F))
  598. #define VHA_CR_CNN_ELEMENTOPS_MH_CONTROL_MAX_BURST_LENGTH_SHIFT (3U)
  599. #define VHA_CR_CNN_ELEMENTOPS_MH_CONTROL_MAX_BURST_LENGTH_CLRMSK (0XFFFFFFE7U)
  600. #define VHA_CR_CNN_ELEMENTOPS_MH_CONTROL_GPU_PIPE_COHERENT_SHIFT (2U)
  601. #define VHA_CR_CNN_ELEMENTOPS_MH_CONTROL_GPU_PIPE_COHERENT_CLRMSK (0XFFFFFFFBU)
  602. #define VHA_CR_CNN_ELEMENTOPS_MH_CONTROL_GPU_PIPE_COHERENT_EN (0X00000004U)
  603. #define VHA_CR_CNN_ELEMENTOPS_MH_CONTROL_PERSISTENCE_SHIFT (0U)
  604. #define VHA_CR_CNN_ELEMENTOPS_MH_CONTROL_PERSISTENCE_CLRMSK (0XFFFFFFFCU)
  605. #define VHA_CR_CNN_DEBUG_CTRL_MASK (0x00000003U)
  606. /*
  607. Debug is switched off */
  608. #define VHA_CR_CNN_DEBUG_CTRL_DISABLE (0x00000000U)
  609. /*
  610. Debug is output at the end of each stream */
  611. #define VHA_CR_CNN_DEBUG_CTRL_STREAM (0x00000001U)
  612. /*
  613. Debug is output at the end of each layer */
  614. #define VHA_CR_CNN_DEBUG_CTRL_LAYER (0x00000002U)
  615. /*
  616. Debug is output at the end of each pass */
  617. #define VHA_CR_CNN_DEBUG_CTRL_PASS (0x00000003U)
  618. /*
  619. Register VHA_CR_OS0_CNN_CRC_CONTROL
  620. */
  621. #define VHA_CR_OS0_CNN_CRC_CONTROL (0x0300U)
  622. #define VHA_CR_OS0_CNN_CRC_CONTROL_MASKFULL (IMG_UINT64_C(0x0000000000000003))
  623. #define VHA_CR_OS0_CNN_CRC_CONTROL_CNN_CRC_ENABLE_SHIFT (0U)
  624. #define VHA_CR_OS0_CNN_CRC_CONTROL_CNN_CRC_ENABLE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFC))
  625. #define VHA_CR_OS0_CNN_CRC_CONTROL_CNN_CRC_ENABLE_DISABLE (IMG_UINT64_C(0000000000000000))
  626. #define VHA_CR_OS0_CNN_CRC_CONTROL_CNN_CRC_ENABLE_STREAM (IMG_UINT64_C(0x0000000000000001))
  627. #define VHA_CR_OS0_CNN_CRC_CONTROL_CNN_CRC_ENABLE_LAYER (IMG_UINT64_C(0x0000000000000002))
  628. #define VHA_CR_OS0_CNN_CRC_CONTROL_CNN_CRC_ENABLE_PASS (IMG_UINT64_C(0x0000000000000003))
  629. /*
  630. Register VHA_CR_OS0_CNN_CRC_ADDRESS
  631. */
  632. #define VHA_CR_OS0_CNN_CRC_ADDRESS (0x0308U)
  633. #define VHA_CR_OS0_CNN_CRC_ADDRESS_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFF00))
  634. #define VHA_CR_OS0_CNN_CRC_ADDRESS_CNN_CRC_ADDR_SHIFT (8U)
  635. #define VHA_CR_OS0_CNN_CRC_ADDRESS_CNN_CRC_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF00000000FF))
  636. #define VHA_CR_OS0_CNN_CRC_ADDRESS_CNN_CRC_ADDR_ALIGNSHIFT (8U)
  637. #define VHA_CR_OS0_CNN_CRC_ADDRESS_CNN_CRC_ADDR_ALIGNSIZE (256U)
  638. /*
  639. Register VHA_CR_OS0_CNN_DEBUG_ADDRESS
  640. */
  641. #define VHA_CR_OS0_CNN_DEBUG_ADDRESS (0x0310U)
  642. #define VHA_CR_OS0_CNN_DEBUG_ADDRESS_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFF00))
  643. #define VHA_CR_OS0_CNN_DEBUG_ADDRESS_CNN_DEBUG_ADDR_SHIFT (8U)
  644. #define VHA_CR_OS0_CNN_DEBUG_ADDRESS_CNN_DEBUG_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF00000000FF))
  645. #define VHA_CR_OS0_CNN_DEBUG_ADDRESS_CNN_DEBUG_ADDR_ALIGNSHIFT (8U)
  646. #define VHA_CR_OS0_CNN_DEBUG_ADDRESS_CNN_DEBUG_ADDR_ALIGNSIZE (256U)
  647. /*
  648. Register VHA_CR_OS0_CNN_DEBUG_SIZE
  649. */
  650. #define VHA_CR_OS0_CNN_DEBUG_SIZE (0x0318U)
  651. #define VHA_CR_OS0_CNN_DEBUG_SIZE_MASKFULL (IMG_UINT64_C(0x0000000000FFFF00))
  652. #define VHA_CR_OS0_CNN_DEBUG_SIZE_CNN_DEBUG_SIZE_SHIFT (8U)
  653. #define VHA_CR_OS0_CNN_DEBUG_SIZE_CNN_DEBUG_SIZE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFF0000FF))
  654. #define VHA_CR_OS0_CNN_DEBUG_SIZE_CNN_DEBUG_SIZE_ALIGNSHIFT (8U)
  655. #define VHA_CR_OS0_CNN_DEBUG_SIZE_CNN_DEBUG_SIZE_ALIGNSIZE (256U)
  656. /*
  657. Register VHA_CR_OS0_CNN_DEBUG_CONTROL
  658. */
  659. #define VHA_CR_OS0_CNN_DEBUG_CONTROL (0x0320U)
  660. #define VHA_CR_OS0_CNN_DEBUG_CONTROL_MASKFULL (IMG_UINT64_C(0x000000000000000F))
  661. #define VHA_CR_OS0_CNN_DEBUG_CONTROL_CNN_PERF_ENABLE_SHIFT (2U)
  662. #define VHA_CR_OS0_CNN_DEBUG_CONTROL_CNN_PERF_ENABLE_CLRMSK (0XFFFFFFF3U)
  663. #define VHA_CR_OS0_CNN_DEBUG_CONTROL_CNN_PERF_ENABLE_DISABLE (00000000U)
  664. #define VHA_CR_OS0_CNN_DEBUG_CONTROL_CNN_PERF_ENABLE_STREAM (0X00000004U)
  665. #define VHA_CR_OS0_CNN_DEBUG_CONTROL_CNN_PERF_ENABLE_LAYER (0X00000008U)
  666. #define VHA_CR_OS0_CNN_DEBUG_CONTROL_CNN_PERF_ENABLE_PASS (0X0000000CU)
  667. #define VHA_CR_OS0_CNN_DEBUG_CONTROL_CNN_BAND_ENABLE_SHIFT (0U)
  668. #define VHA_CR_OS0_CNN_DEBUG_CONTROL_CNN_BAND_ENABLE_CLRMSK (0XFFFFFFFCU)
  669. #define VHA_CR_OS0_CNN_DEBUG_CONTROL_CNN_BAND_ENABLE_DISABLE (00000000U)
  670. #define VHA_CR_OS0_CNN_DEBUG_CONTROL_CNN_BAND_ENABLE_STREAM (0X00000001U)
  671. #define VHA_CR_OS0_CNN_DEBUG_CONTROL_CNN_BAND_ENABLE_LAYER (0X00000002U)
  672. #define VHA_CR_OS0_CNN_DEBUG_CONTROL_CNN_BAND_ENABLE_PASS (0X00000003U)
  673. /*
  674. Register VHA_CR_OS0_CNN_DEBUG_STATUS
  675. */
  676. #define VHA_CR_OS0_CNN_DEBUG_STATUS (0x0328U)
  677. #define VHA_CR_OS0_CNN_DEBUG_STATUS_MASKFULL (IMG_UINT64_C(0x000000000000FFFF))
  678. #define VHA_CR_OS0_CNN_DEBUG_STATUS_CNN_DEBUG_OFFSET_SHIFT (0U)
  679. #define VHA_CR_OS0_CNN_DEBUG_STATUS_CNN_DEBUG_OFFSET_CLRMSK (0XFFFF0000U)
  680. /*
  681. Register VHA_CR_CNN_WDT_COMPAREMATCH
  682. */
  683. #define VHA_CR_CNN_WDT_COMPAREMATCH (0x0330U)
  684. #define VHA_CR_CNN_WDT_COMPAREMATCH_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  685. #define VHA_CR_CNN_WDT_COMPAREMATCH_REG_SHIFT (0U)
  686. #define VHA_CR_CNN_WDT_COMPAREMATCH_REG_CLRMSK (00000000U)
  687. /*
  688. Register VHA_CR_CNN_WDT_TIMER
  689. */
  690. #define VHA_CR_CNN_WDT_TIMER (0x0338U)
  691. #define VHA_CR_CNN_WDT_TIMER_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  692. #define VHA_CR_CNN_WDT_TIMER_VALUE_SHIFT (0U)
  693. #define VHA_CR_CNN_WDT_TIMER_VALUE_CLRMSK (00000000U)
  694. #define VHA_CR_CNN_WDT_CTRL_CNN_WDT_CTRL_MASK (0x00000003U)
  695. /*
  696. WDT is Disabled */
  697. #define VHA_CR_CNN_WDT_CTRL_CNN_WDT_CTRL_NONE (0x00000000U)
  698. /*
  699. WDT is Cleared when CMD Parser starts a pass or CMD parser is kicked*/
  700. #define VHA_CR_CNN_WDT_CTRL_CNN_WDT_CTRL_KICK_PASS (0x00000001U)
  701. /*
  702. WDT is Cleared when CMD Parser is kicked */
  703. #define VHA_CR_CNN_WDT_CTRL_CNN_WDT_CTRL_KICK (0x00000002U)
  704. /*
  705. Register VHA_CR_CNN_WDT_CTRL
  706. */
  707. #define VHA_CR_CNN_WDT_CTRL (0x0340U)
  708. #define VHA_CR_CNN_WDT_CTRL_MASKFULL (IMG_UINT64_C(0x0000000000000003))
  709. #define VHA_CR_CNN_WDT_CTRL_MODE_SHIFT (0U)
  710. #define VHA_CR_CNN_WDT_CTRL_MODE_CLRMSK (0XFFFFFFFCU)
  711. #define VHA_CR_CNN_WDT_CTRL_MODE_NONE (00000000U)
  712. #define VHA_CR_CNN_WDT_CTRL_MODE_KICK_PASS (0X00000001U)
  713. #define VHA_CR_CNN_WDT_CTRL_MODE_KICK (0X00000002U)
  714. /*
  715. Register VHA_CR_CNN_MEM_WDT_COMPAREMATCH
  716. */
  717. #define VHA_CR_CNN_MEM_WDT_COMPAREMATCH (0x0348U)
  718. #define VHA_CR_CNN_MEM_WDT_COMPAREMATCH_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  719. #define VHA_CR_CNN_MEM_WDT_COMPAREMATCH_REG_SHIFT (0U)
  720. #define VHA_CR_CNN_MEM_WDT_COMPAREMATCH_REG_CLRMSK (00000000U)
  721. /*
  722. Register VHA_CR_CNN_ARB_STALL_RATIO
  723. */
  724. #define VHA_CR_CNN_ARB_STALL_RATIO (0x0350U)
  725. #define VHA_CR_CNN_ARB_STALL_RATIO_MASKFULL (IMG_UINT64_C(0x000000000FFFFFFF))
  726. #define VHA_CR_CNN_ARB_STALL_RATIO_OUTPUT_SHIFT (24U)
  727. #define VHA_CR_CNN_ARB_STALL_RATIO_OUTPUT_CLRMSK (0XF0FFFFFFU)
  728. #define VHA_CR_CNN_ARB_STALL_RATIO_REQUESTER_6_SHIFT (20U)
  729. #define VHA_CR_CNN_ARB_STALL_RATIO_REQUESTER_6_CLRMSK (0XFF0FFFFFU)
  730. #define VHA_CR_CNN_ARB_STALL_RATIO_REQUESTER_5_SHIFT (16U)
  731. #define VHA_CR_CNN_ARB_STALL_RATIO_REQUESTER_5_CLRMSK (0XFFF0FFFFU)
  732. #define VHA_CR_CNN_ARB_STALL_RATIO_REQUESTER_4_SHIFT (12U)
  733. #define VHA_CR_CNN_ARB_STALL_RATIO_REQUESTER_4_CLRMSK (0XFFFF0FFFU)
  734. #define VHA_CR_CNN_ARB_STALL_RATIO_REQUESTER_3_SHIFT (8U)
  735. #define VHA_CR_CNN_ARB_STALL_RATIO_REQUESTER_3_CLRMSK (0XFFFFF0FFU)
  736. #define VHA_CR_CNN_ARB_STALL_RATIO_REQUESTER_2_SHIFT (4U)
  737. #define VHA_CR_CNN_ARB_STALL_RATIO_REQUESTER_2_CLRMSK (0XFFFFFF0FU)
  738. #define VHA_CR_CNN_ARB_STALL_RATIO_REQUESTER_1_SHIFT (0U)
  739. #define VHA_CR_CNN_ARB_STALL_RATIO_REQUESTER_1_CLRMSK (0XFFFFFFF0U)
  740. /*
  741. Register VHA_CR_CNN_MEM_WDT_TIMER
  742. */
  743. #define VHA_CR_CNN_MEM_WDT_TIMER (0x0358U)
  744. #define VHA_CR_CNN_MEM_WDT_TIMER_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  745. #define VHA_CR_CNN_MEM_WDT_TIMER_VALUE_SHIFT (0U)
  746. #define VHA_CR_CNN_MEM_WDT_TIMER_VALUE_CLRMSK (00000000U)
  747. #define VHA_CR_CNN_MEM_WDT_CTRL_CNN_MEM_WDT_CTRL_MASK (0x00000003U)
  748. /*
  749. WDT is Disabled */
  750. #define VHA_CR_CNN_MEM_WDT_CTRL_CNN_MEM_WDT_CTRL_NONE (0x00000000U)
  751. /*
  752. WDT is Cleared when CMD Parser starts a pass or CMD parser is kicked*/
  753. #define VHA_CR_CNN_MEM_WDT_CTRL_CNN_MEM_WDT_CTRL_KICK_PASS (0x00000001U)
  754. /*
  755. WDT is Cleared when CMD Parser is kicked */
  756. #define VHA_CR_CNN_MEM_WDT_CTRL_CNN_MEM_WDT_CTRL_KICK (0x00000002U)
  757. /*
  758. Register VHA_CR_CNN_MEM_WDT_CTRL
  759. */
  760. #define VHA_CR_CNN_MEM_WDT_CTRL (0x0360U)
  761. #define VHA_CR_CNN_MEM_WDT_CTRL_MASKFULL (IMG_UINT64_C(0x0000000000000003))
  762. #define VHA_CR_CNN_MEM_WDT_CTRL_MODE_SHIFT (0U)
  763. #define VHA_CR_CNN_MEM_WDT_CTRL_MODE_CLRMSK (0XFFFFFFFCU)
  764. #define VHA_CR_CNN_MEM_WDT_CTRL_MODE_NONE (00000000U)
  765. #define VHA_CR_CNN_MEM_WDT_CTRL_MODE_KICK_PASS (0X00000001U)
  766. #define VHA_CR_CNN_MEM_WDT_CTRL_MODE_KICK (0X00000002U)
  767. /*
  768. Register VHA_CR_CNN_DATAPATH_STALL_RATIO_FE
  769. */
  770. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_FE (0x0368U)
  771. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_FE_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  772. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_FE_CNV_ABUF_SHIFT (28U)
  773. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_FE_CNV_ABUF_CLRMSK (0X0FFFFFFFU)
  774. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_FE_IBUF_CNV_SHIFT (24U)
  775. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_FE_IBUF_CNV_CLRMSK (0XF0FFFFFFU)
  776. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_FE_ABUF_ACT_SHIFT (20U)
  777. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_FE_ABUF_ACT_CLRMSK (0XFF0FFFFFU)
  778. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_FE_ACT_NORM_SHIFT (16U)
  779. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_FE_ACT_NORM_CLRMSK (0XFFF0FFFFU)
  780. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_FE_IBUF_NORM_SHIFT (12U)
  781. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_FE_IBUF_NORM_CLRMSK (0XFFFF0FFFU)
  782. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_FE_CBUF_CNV_SHIFT (8U)
  783. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_FE_CBUF_CNV_CLRMSK (0XFFFFF0FFU)
  784. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_FE_ABUF_OUTPACK_SHIFT (4U)
  785. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_FE_ABUF_OUTPACK_CLRMSK (0XFFFFFF0FU)
  786. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_FE_CBUF_ABUF_SHIFT (0U)
  787. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_FE_CBUF_ABUF_CLRMSK (0XFFFFFFF0U)
  788. /*
  789. Register VHA_CR_CNN_DATAPATH_STALL_RATIO_BE
  790. */
  791. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_BE (0x0370U)
  792. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_BE_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  793. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_BE_NORM_XBAR_SHIFT (28U)
  794. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_BE_NORM_XBAR_CLRMSK (0X0FFFFFFFU)
  795. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_BE_XBAR_OIN_SHIFT (24U)
  796. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_BE_XBAR_OIN_CLRMSK (0XF0FFFFFFU)
  797. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_BE_OIN_OUTPACK_SHIFT (20U)
  798. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_BE_OIN_OUTPACK_CLRMSK (0XFF0FFFFFU)
  799. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_BE_POOL_XBAR_SHIFT (16U)
  800. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_BE_POOL_XBAR_CLRMSK (0XFFF0FFFFU)
  801. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_BE_XBAR_POOL_SHIFT (12U)
  802. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_BE_XBAR_POOL_CLRMSK (0XFFFF0FFFU)
  803. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_BE_NORM_SB_SHIFT (8U)
  804. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_BE_NORM_SB_CLRMSK (0XFFFFF0FFU)
  805. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_BE_POOL_SB_SHIFT (4U)
  806. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_BE_POOL_SB_CLRMSK (0XFFFFFF0FU)
  807. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_BE_OIN_SB_SHIFT (0U)
  808. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_BE_OIN_SB_CLRMSK (0XFFFFFFF0U)
  809. /*
  810. Register VHA_CR_RTM_CTRL
  811. */
  812. #define VHA_CR_RTM_CTRL (0x0380U)
  813. #define VHA_CR_RTM_CTRL_MASKFULL (IMG_UINT64_C(0x000000008FFFFFF8))
  814. #define VHA_CR_RTM_CTRL_RTM_ENABLE_SHIFT (31U)
  815. #define VHA_CR_RTM_CTRL_RTM_ENABLE_CLRMSK (0X7FFFFFFFU)
  816. #define VHA_CR_RTM_CTRL_RTM_ENABLE_EN (0X80000000U)
  817. #define VHA_CR_RTM_CTRL_RTM_SELECTOR_SHIFT (3U)
  818. #define VHA_CR_RTM_CTRL_RTM_SELECTOR_CLRMSK (0XF0000007U)
  819. /*
  820. Register VHA_CR_RTM_DATA
  821. */
  822. #define VHA_CR_RTM_DATA (0x0388U)
  823. #define VHA_CR_RTM_DATA_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  824. #define VHA_CR_RTM_DATA_RTM_DATA_SHIFT (0U)
  825. #define VHA_CR_RTM_DATA_RTM_DATA_CLRMSK (00000000U)
  826. /*
  827. Register VHA_CR_CNN_IP_CONFIG0
  828. */
  829. #define VHA_CR_CNN_IP_CONFIG0 (0x03A0U)
  830. #define VHA_CR_CNN_IP_CONFIG0_MASKFULL (IMG_UINT64_C(0x0000000000003FFF))
  831. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_OUTPUT_FIXTOFIX_SUPPORTED_SHIFT (13U)
  832. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_OUTPUT_FIXTOFIX_SUPPORTED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFDFFF))
  833. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_OUTPUT_FIXTOFIX_SUPPORTED_EN (IMG_UINT64_C(0X0000000000002000))
  834. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_DUAL_8BIT_CONV_SUPPORTED_SHIFT (12U)
  835. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_DUAL_8BIT_CONV_SUPPORTED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFEFFF))
  836. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_DUAL_8BIT_CONV_SUPPORTED_EN (IMG_UINT64_C(0X0000000000001000))
  837. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_DATA_DECOMPRESSION_SUPPORTED_SHIFT (11U)
  838. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_DATA_DECOMPRESSION_SUPPORTED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFF7FF))
  839. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_DATA_DECOMPRESSION_SUPPORTED_EN (IMG_UINT64_C(0X0000000000000800))
  840. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_DATA_COMPRESSION_SUPPORTED_SHIFT (10U)
  841. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_DATA_COMPRESSION_SUPPORTED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFBFF))
  842. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_DATA_COMPRESSION_SUPPORTED_EN (IMG_UINT64_C(0X0000000000000400))
  843. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_ELEMENT_OPS_CALC_SUPPORTED_SHIFT (9U)
  844. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_ELEMENT_OPS_CALC_SUPPORTED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFDFF))
  845. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_ELEMENT_OPS_CALC_SUPPORTED_EN (IMG_UINT64_C(0X0000000000000200))
  846. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_ELEMENT_OPS_FETCH_SUPPORTED_SHIFT (8U)
  847. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_ELEMENT_OPS_FETCH_SUPPORTED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFEFF))
  848. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_ELEMENT_OPS_FETCH_SUPPORTED_EN (IMG_UINT64_C(0X0000000000000100))
  849. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_ELEMENT_OPS_SUPPORTED_SHIFT (7U)
  850. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_ELEMENT_OPS_SUPPORTED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFF7F))
  851. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_ELEMENT_OPS_SUPPORTED_EN (IMG_UINT64_C(0X0000000000000080))
  852. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_POOL_AVG_SUPPORTED_SHIFT (6U)
  853. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_POOL_AVG_SUPPORTED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFBF))
  854. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_POOL_AVG_SUPPORTED_EN (IMG_UINT64_C(0X0000000000000040))
  855. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_POOL_MAX_SUPPORTED_SHIFT (5U)
  856. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_POOL_MAX_SUPPORTED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFDF))
  857. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_POOL_MAX_SUPPORTED_EN (IMG_UINT64_C(0X0000000000000020))
  858. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_NORM_ICN_SUPPORTED_SHIFT (4U)
  859. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_NORM_ICN_SUPPORTED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFEF))
  860. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_NORM_ICN_SUPPORTED_EN (IMG_UINT64_C(0X0000000000000010))
  861. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_NORM_ACN_SUPPORTED_SHIFT (3U)
  862. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_NORM_ACN_SUPPORTED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFF7))
  863. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_NORM_ACN_SUPPORTED_EN (IMG_UINT64_C(0X0000000000000008))
  864. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_ACT_LUT_SUPPORTED_SHIFT (2U)
  865. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_ACT_LUT_SUPPORTED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFB))
  866. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_ACT_LUT_SUPPORTED_EN (IMG_UINT64_C(0X0000000000000004))
  867. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_DECONV_SUPPORTED_SHIFT (1U)
  868. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_DECONV_SUPPORTED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFD))
  869. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_DECONV_SUPPORTED_EN (IMG_UINT64_C(0X0000000000000002))
  870. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_CONV_SUPPORTED_SHIFT (0U)
  871. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_CONV_SUPPORTED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFE))
  872. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_CONV_SUPPORTED_EN (IMG_UINT64_C(0X0000000000000001))
  873. /*
  874. Register VHA_CR_CNN_IP_CONFIG1
  875. */
  876. #define VHA_CR_CNN_IP_CONFIG1 (0x03A8U)
  877. #define VHA_CR_CNN_IP_CONFIG1_MASKFULL (IMG_UINT64_C(0x000000003F0FFFFF))
  878. #define VHA_CR_CNN_IP_CONFIG1_VHA_CNN_WEIGHT_DATA_WIDTH_MIN1_SHIFT (24U)
  879. #define VHA_CR_CNN_IP_CONFIG1_VHA_CNN_WEIGHT_DATA_WIDTH_MIN1_CLRMSK (IMG_UINT64_C(0XFFFFFFFFC0FFFFFF))
  880. #define VHA_CR_CNN_IP_CONFIG1_VHA_CNN_ACTIVATION_DATA_WIDTH_MIN1_SHIFT (16U)
  881. #define VHA_CR_CNN_IP_CONFIG1_VHA_CNN_ACTIVATION_DATA_WIDTH_MIN1_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFF0FFFF))
  882. #define VHA_CR_CNN_IP_CONFIG1_VHA_CNN_CONV_ENGINE_NUM_FILTERS_MIN1_SHIFT (12U)
  883. #define VHA_CR_CNN_IP_CONFIG1_VHA_CNN_CONV_ENGINE_NUM_FILTERS_MIN1_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFF0FFF))
  884. #define VHA_CR_CNN_IP_CONFIG1_VHA_CNN_CONV_ENGINE_NUM_COEFFS_MIN1_SHIFT (4U)
  885. #define VHA_CR_CNN_IP_CONFIG1_VHA_CNN_CONV_ENGINE_NUM_COEFFS_MIN1_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFF00F))
  886. #define VHA_CR_CNN_IP_CONFIG1_VHA_CNN_CONV_ENGINE_CALC_BLOCKS_MIN1_SHIFT (0U)
  887. #define VHA_CR_CNN_IP_CONFIG1_VHA_CNN_CONV_ENGINE_CALC_BLOCKS_MIN1_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFF0))
  888. /*
  889. Register VHA_CR_CNN_IP_CONFIG2
  890. */
  891. #define VHA_CR_CNN_IP_CONFIG2 (0x03B0U)
  892. #define VHA_CR_CNN_IP_CONFIG2_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  893. #define VHA_CR_CNN_IP_CONFIG2_VHA_CNN_NORM_UNITS_MIN1_SHIFT (28U)
  894. #define VHA_CR_CNN_IP_CONFIG2_VHA_CNN_NORM_UNITS_MIN1_CLRMSK (IMG_UINT64_C(0XFFFFFFFF0FFFFFFF))
  895. #define VHA_CR_CNN_IP_CONFIG2_VHA_CNN_SHARED_BUFFER_SIZE_MIN1_SHIFT (20U)
  896. #define VHA_CR_CNN_IP_CONFIG2_VHA_CNN_SHARED_BUFFER_SIZE_MIN1_CLRMSK (IMG_UINT64_C(0XFFFFFFFFF00FFFFF))
  897. #define VHA_CR_CNN_IP_CONFIG2_VHA_CNN_COEFF_BUFFER_SIZE_MIN1_SHIFT (4U)
  898. #define VHA_CR_CNN_IP_CONFIG2_VHA_CNN_COEFF_BUFFER_SIZE_MIN1_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFF0000F))
  899. #define VHA_CR_CNN_IP_CONFIG2_VHA_CNN_COEFF_BUFFER_BANKS_MIN1_SHIFT (0U)
  900. #define VHA_CR_CNN_IP_CONFIG2_VHA_CNN_COEFF_BUFFER_BANKS_MIN1_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFF0))
  901. /*
  902. Register VHA_CR_CNN_IP_CONFIG3
  903. */
  904. #define VHA_CR_CNN_IP_CONFIG3 (0x03B8U)
  905. #define VHA_CR_CNN_IP_CONFIG3_MASKFULL (IMG_UINT64_C(0x0000000000FFFFFF))
  906. #define VHA_CR_CNN_IP_CONFIG3_VHA_CNN_ACT_LUT_SIZE_MIN1_SHIFT (16U)
  907. #define VHA_CR_CNN_IP_CONFIG3_VHA_CNN_ACT_LUT_SIZE_MIN1_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFF00FFFF))
  908. #define VHA_CR_CNN_IP_CONFIG3_VHA_CNN_INPUT_BUFFER_SIZE_MIN1_SHIFT (8U)
  909. #define VHA_CR_CNN_IP_CONFIG3_VHA_CNN_INPUT_BUFFER_SIZE_MIN1_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFF00FF))
  910. #define VHA_CR_CNN_IP_CONFIG3_VHA_CNN_INPUT_BUFFER_BANKS_MIN1_SHIFT (0U)
  911. #define VHA_CR_CNN_IP_CONFIG3_VHA_CNN_INPUT_BUFFER_BANKS_MIN1_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFF00))
  912. /*
  913. Register VHA_CR_BIF_OUTSTANDING_READ
  914. */
  915. #define VHA_CR_BIF_OUTSTANDING_READ (0xF098U)
  916. #define VHA_CR_BIF_OUTSTANDING_READ_MASKFULL (IMG_UINT64_C(0x000000000000FFFF))
  917. #define VHA_CR_BIF_OUTSTANDING_READ_COUNTER_SHIFT (0U)
  918. #define VHA_CR_BIF_OUTSTANDING_READ_COUNTER_CLRMSK (0XFFFF0000U)
  919. /*
  920. Register VHA_CR_BIF_PAGE_FAULT_STALL
  921. */
  922. #define VHA_CR_BIF_PAGE_FAULT_STALL (0xF0B0U)
  923. #define VHA_CR_BIF_PAGE_FAULT_STALL_MASKFULL (IMG_UINT64_C(0x0000000000000001))
  924. #define VHA_CR_BIF_PAGE_FAULT_STALL_STATUS_SHIFT (0U)
  925. #define VHA_CR_BIF_PAGE_FAULT_STALL_STATUS_CLRMSK (0XFFFFFFFEU)
  926. #define VHA_CR_BIF_PAGE_FAULT_STALL_STATUS_EN (0X00000001U)
  927. /*
  928. Register VHA_CR_BIF_RTN_FIFO_WORD_COUNT
  929. */
  930. #define VHA_CR_BIF_RTN_FIFO_WORD_COUNT (0xF230U)
  931. #define VHA_CR_BIF_RTN_FIFO_WORD_COUNT_MASKFULL (IMG_UINT64_C(0x00000000000001FF))
  932. #define VHA_CR_BIF_RTN_FIFO_WORD_COUNT_COUNTER_SHIFT (0U)
  933. #define VHA_CR_BIF_RTN_FIFO_WORD_COUNT_COUNTER_CLRMSK (0XFFFFFE00U)
  934. /*
  935. Register VHA_CR_IDLE_HYSTERESIS_COUNT
  936. */
  937. #define VHA_CR_IDLE_HYSTERESIS_COUNT (0x1000U)
  938. #define VHA_CR_IDLE_HYSTERESIS_COUNT_MASKFULL (IMG_UINT64_C(0x0000001F1F1F1F1F))
  939. #define VHA_CR_IDLE_HYSTERESIS_COUNT_VHA_SYS_SHIFT (32U)
  940. #define VHA_CR_IDLE_HYSTERESIS_COUNT_VHA_SYS_CLRMSK (IMG_UINT64_C(0XFFFFFFE0FFFFFFFF))
  941. #define VHA_CR_IDLE_HYSTERESIS_COUNT_CNN_FE_SHIFT (24U)
  942. #define VHA_CR_IDLE_HYSTERESIS_COUNT_CNN_FE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFE0FFFFFF))
  943. #define VHA_CR_IDLE_HYSTERESIS_COUNT_CNN_BE_SHIFT (16U)
  944. #define VHA_CR_IDLE_HYSTERESIS_COUNT_CNN_BE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFE0FFFF))
  945. #define VHA_CR_IDLE_HYSTERESIS_COUNT_CNN_TOP_SHIFT (8U)
  946. #define VHA_CR_IDLE_HYSTERESIS_COUNT_CNN_TOP_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFE0FF))
  947. #define VHA_CR_IDLE_HYSTERESIS_COUNT_VHA_CTRL_SHIFT (0U)
  948. #define VHA_CR_IDLE_HYSTERESIS_COUNT_VHA_CTRL_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFE0))
  949. /*
  950. Register VHA_CR_SOCIF_WAKEUP_ENABLE
  951. */
  952. #define VHA_CR_SOCIF_WAKEUP_ENABLE (0x1008U)
  953. #define VHA_CR_SOCIF_WAKEUP_ENABLE_MASKFULL (IMG_UINT64_C(0x0000000000000001))
  954. #define VHA_CR_SOCIF_WAKEUP_ENABLE_ALWAYS_SHIFT (0U)
  955. #define VHA_CR_SOCIF_WAKEUP_ENABLE_ALWAYS_CLRMSK (0XFFFFFFFEU)
  956. #define VHA_CR_SOCIF_WAKEUP_ENABLE_ALWAYS_EN (0X00000001U)
  957. /*
  958. Register VHA_CR_REGBANK_REQUEST_INVALID
  959. */
  960. #define VHA_CR_REGBANK_REQUEST_INVALID (0x1018U)
  961. #define VHA_CR_REGBANK_REQUEST_INVALID_MASKFULL (IMG_UINT64_C(0x0000000000000001))
  962. #define VHA_CR_REGBANK_REQUEST_INVALID_FLAG_SHIFT (0U)
  963. #define VHA_CR_REGBANK_REQUEST_INVALID_FLAG_CLRMSK (0XFFFFFFFEU)
  964. #define VHA_CR_REGBANK_REQUEST_INVALID_FLAG_EN (0X00000001U)
  965. /*
  966. Register VHA_CR_RESET_CLK_CTRL
  967. */
  968. #define VHA_CR_RESET_CLK_CTRL (0x1020U)
  969. #define VHA_CR_RESET_CLK_CTRL_MASKFULL (IMG_UINT64_C(0x00000000000003FF))
  970. #define VHA_CR_RESET_CLK_CTRL_VHA_SYS_SHIFT (8U)
  971. #define VHA_CR_RESET_CLK_CTRL_VHA_SYS_CLRMSK (0XFFFFFCFFU)
  972. #define VHA_CR_RESET_CLK_CTRL_CNN_FE_SHIFT (6U)
  973. #define VHA_CR_RESET_CLK_CTRL_CNN_FE_CLRMSK (0XFFFFFF3FU)
  974. #define VHA_CR_RESET_CLK_CTRL_CNN_BE_SHIFT (4U)
  975. #define VHA_CR_RESET_CLK_CTRL_CNN_BE_CLRMSK (0XFFFFFFCFU)
  976. #define VHA_CR_RESET_CLK_CTRL_CNN_TOP_SHIFT (2U)
  977. #define VHA_CR_RESET_CLK_CTRL_CNN_TOP_CLRMSK (0XFFFFFFF3U)
  978. #define VHA_CR_RESET_CLK_CTRL_VHA_CTRL_SHIFT (0U)
  979. #define VHA_CR_RESET_CLK_CTRL_VHA_CTRL_CLRMSK (0XFFFFFFFCU)
  980. /*
  981. Register VHA_CR_PM_VFP_TRAN_EN
  982. */
  983. #define VHA_CR_PM_VFP_TRAN_EN (0x2100U)
  984. #define VHA_CR_PM_VFP_TRAN_EN_MASKFULL (IMG_UINT64_C(0x0000000000000001))
  985. #define VHA_CR_PM_VFP_TRAN_EN_OP_SHIFT (0U)
  986. #define VHA_CR_PM_VFP_TRAN_EN_OP_CLRMSK (0XFFFFFFFEU)
  987. #define VHA_CR_PM_VFP_TRAN_EN_OP_EN (0X00000001U)
  988. /*
  989. Register VHA_CR_PERF_SLC0_READ
  990. */
  991. #define VHA_CR_PERF_SLC0_READ (0x60A0U)
  992. #define VHA_CR_PERF_SLC0_READ_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  993. #define VHA_CR_PERF_SLC0_READ_COUNT_SHIFT (0U)
  994. #define VHA_CR_PERF_SLC0_READ_COUNT_CLRMSK (00000000U)
  995. /*
  996. Register VHA_CR_PERF_SLC0_WRITE
  997. */
  998. #define VHA_CR_PERF_SLC0_WRITE (0x60A8U)
  999. #define VHA_CR_PERF_SLC0_WRITE_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  1000. #define VHA_CR_PERF_SLC0_WRITE_COUNT_SHIFT (0U)
  1001. #define VHA_CR_PERF_SLC0_WRITE_COUNT_CLRMSK (00000000U)
  1002. /*
  1003. Register VHA_CR_PERF_SLC0_WRITE_DATA_STALL
  1004. */
  1005. #define VHA_CR_PERF_SLC0_WRITE_DATA_STALL (0x60B0U)
  1006. #define VHA_CR_PERF_SLC0_WRITE_DATA_STALL_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  1007. #define VHA_CR_PERF_SLC0_WRITE_DATA_STALL_COUNT_SHIFT (0U)
  1008. #define VHA_CR_PERF_SLC0_WRITE_DATA_STALL_COUNT_CLRMSK (00000000U)
  1009. /*
  1010. Register VHA_CR_PERF_SLC0_READ_STALL
  1011. */
  1012. #define VHA_CR_PERF_SLC0_READ_STALL (0x60B8U)
  1013. #define VHA_CR_PERF_SLC0_READ_STALL_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  1014. #define VHA_CR_PERF_SLC0_READ_STALL_COUNT_SHIFT (0U)
  1015. #define VHA_CR_PERF_SLC0_READ_STALL_COUNT_CLRMSK (00000000U)
  1016. /*
  1017. Register VHA_CR_PERF_SLC0_WRITE_STALL
  1018. */
  1019. #define VHA_CR_PERF_SLC0_WRITE_STALL (0x60C0U)
  1020. #define VHA_CR_PERF_SLC0_WRITE_STALL_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  1021. #define VHA_CR_PERF_SLC0_WRITE_STALL_COUNT_SHIFT (0U)
  1022. #define VHA_CR_PERF_SLC0_WRITE_STALL_COUNT_CLRMSK (00000000U)
  1023. /*
  1024. Register VHA_CR_PERF_SLC0_READ_ID_STALL
  1025. */
  1026. #define VHA_CR_PERF_SLC0_READ_ID_STALL (0x60F0U)
  1027. #define VHA_CR_PERF_SLC0_READ_ID_STALL_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  1028. #define VHA_CR_PERF_SLC0_READ_ID_STALL_COUNT_SHIFT (0U)
  1029. #define VHA_CR_PERF_SLC0_READ_ID_STALL_COUNT_CLRMSK (00000000U)
  1030. /*
  1031. Register VHA_CR_PERF_SLC0_WRITE_ID_STALL
  1032. */
  1033. #define VHA_CR_PERF_SLC0_WRITE_ID_STALL (0x60F8U)
  1034. #define VHA_CR_PERF_SLC0_WRITE_ID_STALL_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  1035. #define VHA_CR_PERF_SLC0_WRITE_ID_STALL_COUNT_SHIFT (0U)
  1036. #define VHA_CR_PERF_SLC0_WRITE_ID_STALL_COUNT_CLRMSK (00000000U)
  1037. /*
  1038. Register VHA_CR_PERF_SLC0_RD_BURST_SIZE1
  1039. */
  1040. #define VHA_CR_PERF_SLC0_RD_BURST_SIZE1 (0x6130U)
  1041. #define VHA_CR_PERF_SLC0_RD_BURST_SIZE1_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  1042. #define VHA_CR_PERF_SLC0_RD_BURST_SIZE1_COUNT_SHIFT (0U)
  1043. #define VHA_CR_PERF_SLC0_RD_BURST_SIZE1_COUNT_CLRMSK (00000000U)
  1044. /*
  1045. Register VHA_CR_PERF_SLC0_WR_BURST_SIZE1
  1046. */
  1047. #define VHA_CR_PERF_SLC0_WR_BURST_SIZE1 (0x6138U)
  1048. #define VHA_CR_PERF_SLC0_WR_BURST_SIZE1_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  1049. #define VHA_CR_PERF_SLC0_WR_BURST_SIZE1_COUNT_SHIFT (0U)
  1050. #define VHA_CR_PERF_SLC0_WR_BURST_SIZE1_COUNT_CLRMSK (00000000U)
  1051. /*
  1052. Register VHA_CR_PERF_SLC0_RD_BURST_SIZE2
  1053. */
  1054. #define VHA_CR_PERF_SLC0_RD_BURST_SIZE2 (0x6190U)
  1055. #define VHA_CR_PERF_SLC0_RD_BURST_SIZE2_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  1056. #define VHA_CR_PERF_SLC0_RD_BURST_SIZE2_COUNT_SHIFT (0U)
  1057. #define VHA_CR_PERF_SLC0_RD_BURST_SIZE2_COUNT_CLRMSK (00000000U)
  1058. /*
  1059. Register VHA_CR_PERF_SLC0_WR_BURST_SIZE2
  1060. */
  1061. #define VHA_CR_PERF_SLC0_WR_BURST_SIZE2 (0x6198U)
  1062. #define VHA_CR_PERF_SLC0_WR_BURST_SIZE2_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  1063. #define VHA_CR_PERF_SLC0_WR_BURST_SIZE2_COUNT_SHIFT (0U)
  1064. #define VHA_CR_PERF_SLC0_WR_BURST_SIZE2_COUNT_CLRMSK (00000000U)
  1065. /*
  1066. Register VHA_CR_PERF_SLC0_RD_BURST_SIZE3
  1067. */
  1068. #define VHA_CR_PERF_SLC0_RD_BURST_SIZE3 (0x61B0U)
  1069. #define VHA_CR_PERF_SLC0_RD_BURST_SIZE3_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  1070. #define VHA_CR_PERF_SLC0_RD_BURST_SIZE3_COUNT_SHIFT (0U)
  1071. #define VHA_CR_PERF_SLC0_RD_BURST_SIZE3_COUNT_CLRMSK (00000000U)
  1072. /*
  1073. Register VHA_CR_PERF_SLC0_WR_BURST_SIZE3
  1074. */
  1075. #define VHA_CR_PERF_SLC0_WR_BURST_SIZE3 (0x61B8U)
  1076. #define VHA_CR_PERF_SLC0_WR_BURST_SIZE3_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  1077. #define VHA_CR_PERF_SLC0_WR_BURST_SIZE3_COUNT_SHIFT (0U)
  1078. #define VHA_CR_PERF_SLC0_WR_BURST_SIZE3_COUNT_CLRMSK (00000000U)
  1079. /*
  1080. Register VHA_CR_PERF_SLC0_RD_BURST_SIZE4
  1081. */
  1082. #define VHA_CR_PERF_SLC0_RD_BURST_SIZE4 (0x61C0U)
  1083. #define VHA_CR_PERF_SLC0_RD_BURST_SIZE4_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  1084. #define VHA_CR_PERF_SLC0_RD_BURST_SIZE4_COUNT_SHIFT (0U)
  1085. #define VHA_CR_PERF_SLC0_RD_BURST_SIZE4_COUNT_CLRMSK (00000000U)
  1086. /*
  1087. Register VHA_CR_PERF_SLC0_WR_BURST_SIZE4
  1088. */
  1089. #define VHA_CR_PERF_SLC0_WR_BURST_SIZE4 (0x61C8U)
  1090. #define VHA_CR_PERF_SLC0_WR_BURST_SIZE4_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  1091. #define VHA_CR_PERF_SLC0_WR_BURST_SIZE4_COUNT_SHIFT (0U)
  1092. #define VHA_CR_PERF_SLC0_WR_BURST_SIZE4_COUNT_CLRMSK (00000000U)
  1093. /*
  1094. Register VHA_CR_PERF_SLC_SNOOP_HITS
  1095. */
  1096. #define VHA_CR_PERF_SLC_SNOOP_HITS (0x61A0U)
  1097. #define VHA_CR_PERF_SLC_SNOOP_HITS_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  1098. #define VHA_CR_PERF_SLC_SNOOP_HITS_COUNT_SHIFT (0U)
  1099. #define VHA_CR_PERF_SLC_SNOOP_HITS_COUNT_CLRMSK (00000000U)
  1100. /*
  1101. Register VHA_CR_PERF_SLC_SNOOP_MISSES
  1102. */
  1103. #define VHA_CR_PERF_SLC_SNOOP_MISSES (0x61A8U)
  1104. #define VHA_CR_PERF_SLC_SNOOP_MISSES_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  1105. #define VHA_CR_PERF_SLC_SNOOP_MISSES_COUNT_SHIFT (0U)
  1106. #define VHA_CR_PERF_SLC_SNOOP_MISSES_COUNT_CLRMSK (00000000U)
  1107. /*
  1108. Register VHA_CR_PERF_RESET_FULL
  1109. */
  1110. #define VHA_CR_PERF_RESET_FULL (0x3990U)
  1111. #define VHA_CR_PERF_RESET_FULL_MASKFULL (IMG_UINT64_C(0x0000000000000001))
  1112. #define VHA_CR_PERF_RESET_FULL_RANGE_SHIFT (0U)
  1113. #define VHA_CR_PERF_RESET_FULL_RANGE_CLRMSK (0XFFFFFFFEU)
  1114. #define VHA_CR_PERF_RESET_FULL_RANGE_EN (0X00000001U)
  1115. /*
  1116. Register VHA_CR_PERF_ENABLE_FULL
  1117. */
  1118. #define VHA_CR_PERF_ENABLE_FULL (0x3998U)
  1119. #define VHA_CR_PERF_ENABLE_FULL_MASKFULL (IMG_UINT64_C(0x0000000000000001))
  1120. #define VHA_CR_PERF_ENABLE_FULL_RANGE_SHIFT (0U)
  1121. #define VHA_CR_PERF_ENABLE_FULL_RANGE_CLRMSK (0XFFFFFFFEU)
  1122. #define VHA_CR_PERF_ENABLE_FULL_RANGE_EN (0X00000001U)
  1123. /*
  1124. Register VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE0
  1125. */
  1126. #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE0 (0xE008U)
  1127. #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE0_MASKFULL (IMG_UINT64_C(0x0FFFFFFFFFFFF003))
  1128. #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE0_INIT_PAGE_SHIFT (40U)
  1129. #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE0_INIT_PAGE_CLRMSK (IMG_UINT64_C(0XF00000FFFFFFFFFF))
  1130. #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE0_ADDR_SHIFT (12U)
  1131. #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE0_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF0000000FFF))
  1132. #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE0_WRAP_SHIFT (1U)
  1133. #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE0_WRAP_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFD))
  1134. #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE0_WRAP_EN (IMG_UINT64_C(0X0000000000000002))
  1135. #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE0_VALID_SHIFT (0U)
  1136. #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE0_VALID_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFE))
  1137. #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE0_VALID_EN (IMG_UINT64_C(0X0000000000000001))
  1138. /*
  1139. Register VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE1
  1140. */
  1141. #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE1 (0xE010U)
  1142. #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE1_MASKFULL (IMG_UINT64_C(0x00000003FFFFC003))
  1143. #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE1_INIT_PAGE_SHIFT (14U)
  1144. #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE1_INIT_PAGE_CLRMSK (IMG_UINT64_C(0XFFFFFFFC00003FFF))
  1145. #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE1_WRAP_SHIFT (1U)
  1146. #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE1_WRAP_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFD))
  1147. #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE1_WRAP_EN (IMG_UINT64_C(0X0000000000000002))
  1148. #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE1_VALID_SHIFT (0U)
  1149. #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE1_VALID_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFE))
  1150. #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE1_VALID_EN (IMG_UINT64_C(0X0000000000000001))
  1151. /*
  1152. Register VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE2
  1153. */
  1154. #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE2 (0xE018U)
  1155. #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE2_MASKFULL (IMG_UINT64_C(0x00000003FFFFC003))
  1156. #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE2_INIT_PAGE_SHIFT (14U)
  1157. #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE2_INIT_PAGE_CLRMSK (IMG_UINT64_C(0XFFFFFFFC00003FFF))
  1158. #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE2_WRAP_SHIFT (1U)
  1159. #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE2_WRAP_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFD))
  1160. #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE2_WRAP_EN (IMG_UINT64_C(0X0000000000000002))
  1161. #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE2_VALID_SHIFT (0U)
  1162. #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE2_VALID_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFE))
  1163. #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE2_VALID_EN (IMG_UINT64_C(0X0000000000000001))
  1164. /*
  1165. Register VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE3
  1166. */
  1167. #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE3 (0xE020U)
  1168. #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE3_MASKFULL (IMG_UINT64_C(0x00000003FFFFC003))
  1169. #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE3_INIT_PAGE_SHIFT (14U)
  1170. #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE3_INIT_PAGE_CLRMSK (IMG_UINT64_C(0XFFFFFFFC00003FFF))
  1171. #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE3_WRAP_SHIFT (1U)
  1172. #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE3_WRAP_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFD))
  1173. #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE3_WRAP_EN (IMG_UINT64_C(0X0000000000000002))
  1174. #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE3_VALID_SHIFT (0U)
  1175. #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE3_VALID_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFE))
  1176. #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE3_VALID_EN (IMG_UINT64_C(0X0000000000000001))
  1177. /*
  1178. Register VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE0
  1179. */
  1180. #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE0 (0xE028U)
  1181. #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE0_MASKFULL (IMG_UINT64_C(0x0FFFFFFFFFFFF003))
  1182. #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE0_INIT_PAGE_SHIFT (40U)
  1183. #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE0_INIT_PAGE_CLRMSK (IMG_UINT64_C(0XF00000FFFFFFFFFF))
  1184. #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE0_ADDR_SHIFT (12U)
  1185. #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE0_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF0000000FFF))
  1186. #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE0_WRAP_SHIFT (1U)
  1187. #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE0_WRAP_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFD))
  1188. #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE0_WRAP_EN (IMG_UINT64_C(0X0000000000000002))
  1189. #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE0_VALID_SHIFT (0U)
  1190. #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE0_VALID_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFE))
  1191. #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE0_VALID_EN (IMG_UINT64_C(0X0000000000000001))
  1192. /*
  1193. Register VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE1
  1194. */
  1195. #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE1 (0xE030U)
  1196. #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE1_MASKFULL (IMG_UINT64_C(0x00000003FFFFC003))
  1197. #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE1_INIT_PAGE_SHIFT (14U)
  1198. #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE1_INIT_PAGE_CLRMSK (IMG_UINT64_C(0XFFFFFFFC00003FFF))
  1199. #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE1_WRAP_SHIFT (1U)
  1200. #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE1_WRAP_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFD))
  1201. #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE1_WRAP_EN (IMG_UINT64_C(0X0000000000000002))
  1202. #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE1_VALID_SHIFT (0U)
  1203. #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE1_VALID_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFE))
  1204. #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE1_VALID_EN (IMG_UINT64_C(0X0000000000000001))
  1205. /*
  1206. Register VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE2
  1207. */
  1208. #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE2 (0xE038U)
  1209. #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE2_MASKFULL (IMG_UINT64_C(0x00000003FFFFC003))
  1210. #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE2_INIT_PAGE_SHIFT (14U)
  1211. #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE2_INIT_PAGE_CLRMSK (IMG_UINT64_C(0XFFFFFFFC00003FFF))
  1212. #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE2_WRAP_SHIFT (1U)
  1213. #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE2_WRAP_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFD))
  1214. #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE2_WRAP_EN (IMG_UINT64_C(0X0000000000000002))
  1215. #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE2_VALID_SHIFT (0U)
  1216. #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE2_VALID_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFE))
  1217. #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE2_VALID_EN (IMG_UINT64_C(0X0000000000000001))
  1218. /*
  1219. Register VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE3
  1220. */
  1221. #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE3 (0xE040U)
  1222. #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE3_MASKFULL (IMG_UINT64_C(0x00000003FFFFC003))
  1223. #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE3_INIT_PAGE_SHIFT (14U)
  1224. #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE3_INIT_PAGE_CLRMSK (IMG_UINT64_C(0XFFFFFFFC00003FFF))
  1225. #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE3_WRAP_SHIFT (1U)
  1226. #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE3_WRAP_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFD))
  1227. #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE3_WRAP_EN (IMG_UINT64_C(0X0000000000000002))
  1228. #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE3_VALID_SHIFT (0U)
  1229. #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE3_VALID_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFE))
  1230. #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE3_VALID_EN (IMG_UINT64_C(0X0000000000000001))
  1231. /*
  1232. Register VHA_CR_MMU_PM_CAT_BASE_ALIST0
  1233. */
  1234. #define VHA_CR_MMU_PM_CAT_BASE_ALIST0 (0xE048U)
  1235. #define VHA_CR_MMU_PM_CAT_BASE_ALIST0_MASKFULL (IMG_UINT64_C(0x0FFFFFFFFFFFF003))
  1236. #define VHA_CR_MMU_PM_CAT_BASE_ALIST0_INIT_PAGE_SHIFT (40U)
  1237. #define VHA_CR_MMU_PM_CAT_BASE_ALIST0_INIT_PAGE_CLRMSK (IMG_UINT64_C(0XF00000FFFFFFFFFF))
  1238. #define VHA_CR_MMU_PM_CAT_BASE_ALIST0_ADDR_SHIFT (12U)
  1239. #define VHA_CR_MMU_PM_CAT_BASE_ALIST0_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF0000000FFF))
  1240. #define VHA_CR_MMU_PM_CAT_BASE_ALIST0_WRAP_SHIFT (1U)
  1241. #define VHA_CR_MMU_PM_CAT_BASE_ALIST0_WRAP_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFD))
  1242. #define VHA_CR_MMU_PM_CAT_BASE_ALIST0_WRAP_EN (IMG_UINT64_C(0X0000000000000002))
  1243. #define VHA_CR_MMU_PM_CAT_BASE_ALIST0_VALID_SHIFT (0U)
  1244. #define VHA_CR_MMU_PM_CAT_BASE_ALIST0_VALID_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFE))
  1245. #define VHA_CR_MMU_PM_CAT_BASE_ALIST0_VALID_EN (IMG_UINT64_C(0X0000000000000001))
  1246. /*
  1247. Register VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE0
  1248. */
  1249. #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE0 (0xE050U)
  1250. #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE0_MASKFULL (IMG_UINT64_C(0x0FFFFFFFFFFFF003))
  1251. #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE0_INIT_PAGE_SHIFT (40U)
  1252. #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE0_INIT_PAGE_CLRMSK (IMG_UINT64_C(0XF00000FFFFFFFFFF))
  1253. #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE0_ADDR_SHIFT (12U)
  1254. #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE0_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF0000000FFF))
  1255. #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE0_WRAP_SHIFT (1U)
  1256. #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE0_WRAP_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFD))
  1257. #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE0_WRAP_EN (IMG_UINT64_C(0X0000000000000002))
  1258. #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE0_VALID_SHIFT (0U)
  1259. #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE0_VALID_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFE))
  1260. #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE0_VALID_EN (IMG_UINT64_C(0X0000000000000001))
  1261. /*
  1262. Register VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE1
  1263. */
  1264. #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE1 (0xE058U)
  1265. #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE1_MASKFULL (IMG_UINT64_C(0x00000003FFFFC003))
  1266. #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE1_INIT_PAGE_SHIFT (14U)
  1267. #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE1_INIT_PAGE_CLRMSK (IMG_UINT64_C(0XFFFFFFFC00003FFF))
  1268. #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE1_WRAP_SHIFT (1U)
  1269. #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE1_WRAP_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFD))
  1270. #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE1_WRAP_EN (IMG_UINT64_C(0X0000000000000002))
  1271. #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE1_VALID_SHIFT (0U)
  1272. #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE1_VALID_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFE))
  1273. #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE1_VALID_EN (IMG_UINT64_C(0X0000000000000001))
  1274. /*
  1275. Register VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE2
  1276. */
  1277. #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE2 (0xE060U)
  1278. #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE2_MASKFULL (IMG_UINT64_C(0x00000003FFFFC003))
  1279. #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE2_INIT_PAGE_SHIFT (14U)
  1280. #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE2_INIT_PAGE_CLRMSK (IMG_UINT64_C(0XFFFFFFFC00003FFF))
  1281. #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE2_WRAP_SHIFT (1U)
  1282. #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE2_WRAP_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFD))
  1283. #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE2_WRAP_EN (IMG_UINT64_C(0X0000000000000002))
  1284. #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE2_VALID_SHIFT (0U)
  1285. #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE2_VALID_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFE))
  1286. #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE2_VALID_EN (IMG_UINT64_C(0X0000000000000001))
  1287. /*
  1288. Register VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE3
  1289. */
  1290. #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE3 (0xE068U)
  1291. #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE3_MASKFULL (IMG_UINT64_C(0x00000003FFFFC003))
  1292. #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE3_INIT_PAGE_SHIFT (14U)
  1293. #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE3_INIT_PAGE_CLRMSK (IMG_UINT64_C(0XFFFFFFFC00003FFF))
  1294. #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE3_WRAP_SHIFT (1U)
  1295. #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE3_WRAP_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFD))
  1296. #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE3_WRAP_EN (IMG_UINT64_C(0X0000000000000002))
  1297. #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE3_VALID_SHIFT (0U)
  1298. #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE3_VALID_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFE))
  1299. #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE3_VALID_EN (IMG_UINT64_C(0X0000000000000001))
  1300. /*
  1301. Register VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE0
  1302. */
  1303. #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE0 (0xE070U)
  1304. #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE0_MASKFULL (IMG_UINT64_C(0x0FFFFFFFFFFFF003))
  1305. #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE0_INIT_PAGE_SHIFT (40U)
  1306. #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE0_INIT_PAGE_CLRMSK (IMG_UINT64_C(0XF00000FFFFFFFFFF))
  1307. #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE0_ADDR_SHIFT (12U)
  1308. #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE0_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF0000000FFF))
  1309. #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE0_WRAP_SHIFT (1U)
  1310. #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE0_WRAP_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFD))
  1311. #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE0_WRAP_EN (IMG_UINT64_C(0X0000000000000002))
  1312. #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE0_VALID_SHIFT (0U)
  1313. #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE0_VALID_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFE))
  1314. #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE0_VALID_EN (IMG_UINT64_C(0X0000000000000001))
  1315. /*
  1316. Register VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE1
  1317. */
  1318. #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE1 (0xE078U)
  1319. #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE1_MASKFULL (IMG_UINT64_C(0x00000003FFFFC003))
  1320. #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE1_INIT_PAGE_SHIFT (14U)
  1321. #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE1_INIT_PAGE_CLRMSK (IMG_UINT64_C(0XFFFFFFFC00003FFF))
  1322. #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE1_WRAP_SHIFT (1U)
  1323. #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE1_WRAP_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFD))
  1324. #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE1_WRAP_EN (IMG_UINT64_C(0X0000000000000002))
  1325. #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE1_VALID_SHIFT (0U)
  1326. #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE1_VALID_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFE))
  1327. #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE1_VALID_EN (IMG_UINT64_C(0X0000000000000001))
  1328. /*
  1329. Register VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE2
  1330. */
  1331. #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE2 (0xE080U)
  1332. #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE2_MASKFULL (IMG_UINT64_C(0x00000003FFFFC003))
  1333. #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE2_INIT_PAGE_SHIFT (14U)
  1334. #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE2_INIT_PAGE_CLRMSK (IMG_UINT64_C(0XFFFFFFFC00003FFF))
  1335. #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE2_WRAP_SHIFT (1U)
  1336. #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE2_WRAP_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFD))
  1337. #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE2_WRAP_EN (IMG_UINT64_C(0X0000000000000002))
  1338. #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE2_VALID_SHIFT (0U)
  1339. #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE2_VALID_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFE))
  1340. #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE2_VALID_EN (IMG_UINT64_C(0X0000000000000001))
  1341. /*
  1342. Register VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE3
  1343. */
  1344. #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE3 (0xE088U)
  1345. #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE3_MASKFULL (IMG_UINT64_C(0x00000003FFFFC003))
  1346. #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE3_INIT_PAGE_SHIFT (14U)
  1347. #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE3_INIT_PAGE_CLRMSK (IMG_UINT64_C(0XFFFFFFFC00003FFF))
  1348. #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE3_WRAP_SHIFT (1U)
  1349. #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE3_WRAP_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFD))
  1350. #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE3_WRAP_EN (IMG_UINT64_C(0X0000000000000002))
  1351. #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE3_VALID_SHIFT (0U)
  1352. #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE3_VALID_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFE))
  1353. #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE3_VALID_EN (IMG_UINT64_C(0X0000000000000001))
  1354. /*
  1355. Register VHA_CR_MMU_PM_CAT_BASE_ALIST1
  1356. */
  1357. #define VHA_CR_MMU_PM_CAT_BASE_ALIST1 (0xE090U)
  1358. #define VHA_CR_MMU_PM_CAT_BASE_ALIST1_MASKFULL (IMG_UINT64_C(0x0FFFFFFFFFFFF003))
  1359. #define VHA_CR_MMU_PM_CAT_BASE_ALIST1_INIT_PAGE_SHIFT (40U)
  1360. #define VHA_CR_MMU_PM_CAT_BASE_ALIST1_INIT_PAGE_CLRMSK (IMG_UINT64_C(0XF00000FFFFFFFFFF))
  1361. #define VHA_CR_MMU_PM_CAT_BASE_ALIST1_ADDR_SHIFT (12U)
  1362. #define VHA_CR_MMU_PM_CAT_BASE_ALIST1_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF0000000FFF))
  1363. #define VHA_CR_MMU_PM_CAT_BASE_ALIST1_WRAP_SHIFT (1U)
  1364. #define VHA_CR_MMU_PM_CAT_BASE_ALIST1_WRAP_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFD))
  1365. #define VHA_CR_MMU_PM_CAT_BASE_ALIST1_WRAP_EN (IMG_UINT64_C(0X0000000000000002))
  1366. #define VHA_CR_MMU_PM_CAT_BASE_ALIST1_VALID_SHIFT (0U)
  1367. #define VHA_CR_MMU_PM_CAT_BASE_ALIST1_VALID_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFE))
  1368. #define VHA_CR_MMU_PM_CAT_BASE_ALIST1_VALID_EN (IMG_UINT64_C(0X0000000000000001))
  1369. /*
  1370. Register VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE0_LAST
  1371. */
  1372. #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE0_LAST (0xE098U)
  1373. #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE0_LAST_MASKFULL (IMG_UINT64_C(0x00000003FFFFC000))
  1374. #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE0_LAST_PAGE_SHIFT (14U)
  1375. #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE0_LAST_PAGE_CLRMSK (IMG_UINT64_C(0XFFFFFFFC00003FFF))
  1376. #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE0_LAST_PAGE_ALIGNSHIFT (14U)
  1377. #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE0_LAST_PAGE_ALIGNSIZE (16384U)
  1378. /*
  1379. Register VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE1_LAST
  1380. */
  1381. #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE1_LAST (0xE0A0U)
  1382. #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE1_LAST_MASKFULL (IMG_UINT64_C(0x00000003FFFFC000))
  1383. #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE1_LAST_PAGE_SHIFT (14U)
  1384. #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE1_LAST_PAGE_CLRMSK (IMG_UINT64_C(0XFFFFFFFC00003FFF))
  1385. #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE1_LAST_PAGE_ALIGNSHIFT (14U)
  1386. #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE1_LAST_PAGE_ALIGNSIZE (16384U)
  1387. /*
  1388. Register VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE2_LAST
  1389. */
  1390. #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE2_LAST (0xE0A8U)
  1391. #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE2_LAST_MASKFULL (IMG_UINT64_C(0x00000003FFFFC000))
  1392. #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE2_LAST_PAGE_SHIFT (14U)
  1393. #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE2_LAST_PAGE_CLRMSK (IMG_UINT64_C(0XFFFFFFFC00003FFF))
  1394. #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE2_LAST_PAGE_ALIGNSHIFT (14U)
  1395. #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE2_LAST_PAGE_ALIGNSIZE (16384U)
  1396. /*
  1397. Register VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE3_LAST
  1398. */
  1399. #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE3_LAST (0xE0B0U)
  1400. #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE3_LAST_MASKFULL (IMG_UINT64_C(0x00000003FFFFC000))
  1401. #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE3_LAST_PAGE_SHIFT (14U)
  1402. #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE3_LAST_PAGE_CLRMSK (IMG_UINT64_C(0XFFFFFFFC00003FFF))
  1403. #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE3_LAST_PAGE_ALIGNSHIFT (14U)
  1404. #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE3_LAST_PAGE_ALIGNSIZE (16384U)
  1405. /*
  1406. Register VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE0_LAST
  1407. */
  1408. #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE0_LAST (0xE0B8U)
  1409. #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE0_LAST_MASKFULL (IMG_UINT64_C(0x00000003FFFFC000))
  1410. #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE0_LAST_PAGE_SHIFT (14U)
  1411. #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE0_LAST_PAGE_CLRMSK (IMG_UINT64_C(0XFFFFFFFC00003FFF))
  1412. #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE0_LAST_PAGE_ALIGNSHIFT (14U)
  1413. #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE0_LAST_PAGE_ALIGNSIZE (16384U)
  1414. /*
  1415. Register VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE1_LAST
  1416. */
  1417. #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE1_LAST (0xE0C0U)
  1418. #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE1_LAST_MASKFULL (IMG_UINT64_C(0x00000003FFFFC000))
  1419. #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE1_LAST_PAGE_SHIFT (14U)
  1420. #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE1_LAST_PAGE_CLRMSK (IMG_UINT64_C(0XFFFFFFFC00003FFF))
  1421. #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE1_LAST_PAGE_ALIGNSHIFT (14U)
  1422. #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE1_LAST_PAGE_ALIGNSIZE (16384U)
  1423. /*
  1424. Register VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE2_LAST
  1425. */
  1426. #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE2_LAST (0xE0C8U)
  1427. #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE2_LAST_MASKFULL (IMG_UINT64_C(0x00000003FFFFC000))
  1428. #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE2_LAST_PAGE_SHIFT (14U)
  1429. #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE2_LAST_PAGE_CLRMSK (IMG_UINT64_C(0XFFFFFFFC00003FFF))
  1430. #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE2_LAST_PAGE_ALIGNSHIFT (14U)
  1431. #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE2_LAST_PAGE_ALIGNSIZE (16384U)
  1432. /*
  1433. Register VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE3_LAST
  1434. */
  1435. #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE3_LAST (0xE0D0U)
  1436. #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE3_LAST_MASKFULL (IMG_UINT64_C(0x00000003FFFFC000))
  1437. #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE3_LAST_PAGE_SHIFT (14U)
  1438. #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE3_LAST_PAGE_CLRMSK (IMG_UINT64_C(0XFFFFFFFC00003FFF))
  1439. #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE3_LAST_PAGE_ALIGNSHIFT (14U)
  1440. #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE3_LAST_PAGE_ALIGNSIZE (16384U)
  1441. /*
  1442. Register VHA_CR_MMU_PM_CAT_BASE_ALIST0_LAST
  1443. */
  1444. #define VHA_CR_MMU_PM_CAT_BASE_ALIST0_LAST (0xE0D8U)
  1445. #define VHA_CR_MMU_PM_CAT_BASE_ALIST0_LAST_MASKFULL (IMG_UINT64_C(0x00000003FFFFC000))
  1446. #define VHA_CR_MMU_PM_CAT_BASE_ALIST0_LAST_PAGE_SHIFT (14U)
  1447. #define VHA_CR_MMU_PM_CAT_BASE_ALIST0_LAST_PAGE_CLRMSK (IMG_UINT64_C(0XFFFFFFFC00003FFF))
  1448. #define VHA_CR_MMU_PM_CAT_BASE_ALIST0_LAST_PAGE_ALIGNSHIFT (14U)
  1449. #define VHA_CR_MMU_PM_CAT_BASE_ALIST0_LAST_PAGE_ALIGNSIZE (16384U)
  1450. /*
  1451. Register VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE0_LAST
  1452. */
  1453. #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE0_LAST (0xE0E0U)
  1454. #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE0_LAST_MASKFULL (IMG_UINT64_C(0x00000003FFFFC000))
  1455. #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE0_LAST_PAGE_SHIFT (14U)
  1456. #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE0_LAST_PAGE_CLRMSK (IMG_UINT64_C(0XFFFFFFFC00003FFF))
  1457. #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE0_LAST_PAGE_ALIGNSHIFT (14U)
  1458. #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE0_LAST_PAGE_ALIGNSIZE (16384U)
  1459. /*
  1460. Register VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE1_LAST
  1461. */
  1462. #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE1_LAST (0xE0E8U)
  1463. #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE1_LAST_MASKFULL (IMG_UINT64_C(0x00000003FFFFC000))
  1464. #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE1_LAST_PAGE_SHIFT (14U)
  1465. #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE1_LAST_PAGE_CLRMSK (IMG_UINT64_C(0XFFFFFFFC00003FFF))
  1466. #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE1_LAST_PAGE_ALIGNSHIFT (14U)
  1467. #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE1_LAST_PAGE_ALIGNSIZE (16384U)
  1468. /*
  1469. Register VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE2_LAST
  1470. */
  1471. #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE2_LAST (0xE0F0U)
  1472. #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE2_LAST_MASKFULL (IMG_UINT64_C(0x00000003FFFFC000))
  1473. #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE2_LAST_PAGE_SHIFT (14U)
  1474. #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE2_LAST_PAGE_CLRMSK (IMG_UINT64_C(0XFFFFFFFC00003FFF))
  1475. #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE2_LAST_PAGE_ALIGNSHIFT (14U)
  1476. #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE2_LAST_PAGE_ALIGNSIZE (16384U)
  1477. /*
  1478. Register VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE3_LAST
  1479. */
  1480. #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE3_LAST (0xE0F8U)
  1481. #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE3_LAST_MASKFULL (IMG_UINT64_C(0x00000003FFFFC000))
  1482. #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE3_LAST_PAGE_SHIFT (14U)
  1483. #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE3_LAST_PAGE_CLRMSK (IMG_UINT64_C(0XFFFFFFFC00003FFF))
  1484. #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE3_LAST_PAGE_ALIGNSHIFT (14U)
  1485. #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE3_LAST_PAGE_ALIGNSIZE (16384U)
  1486. /*
  1487. Register VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE0_LAST
  1488. */
  1489. #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE0_LAST (0xE100U)
  1490. #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE0_LAST_MASKFULL (IMG_UINT64_C(0x00000003FFFFC000))
  1491. #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE0_LAST_PAGE_SHIFT (14U)
  1492. #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE0_LAST_PAGE_CLRMSK (IMG_UINT64_C(0XFFFFFFFC00003FFF))
  1493. #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE0_LAST_PAGE_ALIGNSHIFT (14U)
  1494. #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE0_LAST_PAGE_ALIGNSIZE (16384U)
  1495. /*
  1496. Register VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE1_LAST
  1497. */
  1498. #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE1_LAST (0xE108U)
  1499. #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE1_LAST_MASKFULL (IMG_UINT64_C(0x00000003FFFFC000))
  1500. #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE1_LAST_PAGE_SHIFT (14U)
  1501. #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE1_LAST_PAGE_CLRMSK (IMG_UINT64_C(0XFFFFFFFC00003FFF))
  1502. #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE1_LAST_PAGE_ALIGNSHIFT (14U)
  1503. #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE1_LAST_PAGE_ALIGNSIZE (16384U)
  1504. /*
  1505. Register VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE2_LAST
  1506. */
  1507. #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE2_LAST (0xE110U)
  1508. #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE2_LAST_MASKFULL (IMG_UINT64_C(0x00000003FFFFC000))
  1509. #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE2_LAST_PAGE_SHIFT (14U)
  1510. #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE2_LAST_PAGE_CLRMSK (IMG_UINT64_C(0XFFFFFFFC00003FFF))
  1511. #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE2_LAST_PAGE_ALIGNSHIFT (14U)
  1512. #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE2_LAST_PAGE_ALIGNSIZE (16384U)
  1513. /*
  1514. Register VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE3_LAST
  1515. */
  1516. #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE3_LAST (0xE118U)
  1517. #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE3_LAST_MASKFULL (IMG_UINT64_C(0x00000003FFFFC000))
  1518. #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE3_LAST_PAGE_SHIFT (14U)
  1519. #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE3_LAST_PAGE_CLRMSK (IMG_UINT64_C(0XFFFFFFFC00003FFF))
  1520. #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE3_LAST_PAGE_ALIGNSHIFT (14U)
  1521. #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE3_LAST_PAGE_ALIGNSIZE (16384U)
  1522. /*
  1523. Register VHA_CR_MMU_PM_CAT_BASE_ALIST1_LAST
  1524. */
  1525. #define VHA_CR_MMU_PM_CAT_BASE_ALIST1_LAST (0xE120U)
  1526. #define VHA_CR_MMU_PM_CAT_BASE_ALIST1_LAST_MASKFULL (IMG_UINT64_C(0x00000003FFFFC000))
  1527. #define VHA_CR_MMU_PM_CAT_BASE_ALIST1_LAST_PAGE_SHIFT (14U)
  1528. #define VHA_CR_MMU_PM_CAT_BASE_ALIST1_LAST_PAGE_CLRMSK (IMG_UINT64_C(0XFFFFFFFC00003FFF))
  1529. #define VHA_CR_MMU_PM_CAT_BASE_ALIST1_LAST_PAGE_ALIGNSHIFT (14U)
  1530. #define VHA_CR_MMU_PM_CAT_BASE_ALIST1_LAST_PAGE_ALIGNSIZE (16384U)
  1531. /*
  1532. Register VHA_CR_OS0_MMU_CTRL_INVAL
  1533. */
  1534. #define VHA_CR_OS0_MMU_CTRL_INVAL (0xE138U)
  1535. #define VHA_CR_OS0_MMU_CTRL_INVAL_MASKFULL (IMG_UINT64_C(0x0000000000000FFF))
  1536. #define VHA_CR_OS0_MMU_CTRL_INVAL_ALL_CONTEXTS_SHIFT (11U)
  1537. #define VHA_CR_OS0_MMU_CTRL_INVAL_ALL_CONTEXTS_CLRMSK (0XFFFFF7FFU)
  1538. #define VHA_CR_OS0_MMU_CTRL_INVAL_ALL_CONTEXTS_EN (0X00000800U)
  1539. #define VHA_CR_OS0_MMU_CTRL_INVAL_CONTEXT_SHIFT (3U)
  1540. #define VHA_CR_OS0_MMU_CTRL_INVAL_CONTEXT_CLRMSK (0XFFFFF807U)
  1541. #define VHA_CR_OS0_MMU_CTRL_INVAL_PC_SHIFT (2U)
  1542. #define VHA_CR_OS0_MMU_CTRL_INVAL_PC_CLRMSK (0XFFFFFFFBU)
  1543. #define VHA_CR_OS0_MMU_CTRL_INVAL_PC_EN (0X00000004U)
  1544. #define VHA_CR_OS0_MMU_CTRL_INVAL_PD_SHIFT (1U)
  1545. #define VHA_CR_OS0_MMU_CTRL_INVAL_PD_CLRMSK (0XFFFFFFFDU)
  1546. #define VHA_CR_OS0_MMU_CTRL_INVAL_PD_EN (0X00000002U)
  1547. #define VHA_CR_OS0_MMU_CTRL_INVAL_PT_SHIFT (0U)
  1548. #define VHA_CR_OS0_MMU_CTRL_INVAL_PT_CLRMSK (0XFFFFFFFEU)
  1549. #define VHA_CR_OS0_MMU_CTRL_INVAL_PT_EN (0X00000001U)
  1550. /*
  1551. Register VHA_CR_OS0_MMU_CBASE_MAPPING_CONTEXT
  1552. */
  1553. #define VHA_CR_OS0_MMU_CBASE_MAPPING_CONTEXT (0xE140U)
  1554. #define VHA_CR_OS0_MMU_CBASE_MAPPING_CONTEXT_MASKFULL (IMG_UINT64_C(0x00000000000000FF))
  1555. #define VHA_CR_OS0_MMU_CBASE_MAPPING_CONTEXT_ID_SHIFT (0U)
  1556. #define VHA_CR_OS0_MMU_CBASE_MAPPING_CONTEXT_ID_CLRMSK (0XFFFFFF00U)
  1557. /*
  1558. Register VHA_CR_OS0_MMU_CBASE_MAPPING
  1559. */
  1560. #define VHA_CR_OS0_MMU_CBASE_MAPPING (0xE148U)
  1561. #define VHA_CR_OS0_MMU_CBASE_MAPPING_MASKFULL (IMG_UINT64_C(0x000000001FFFFFFF))
  1562. #define VHA_CR_OS0_MMU_CBASE_MAPPING_INVALID_SHIFT (28U)
  1563. #define VHA_CR_OS0_MMU_CBASE_MAPPING_INVALID_CLRMSK (0XEFFFFFFFU)
  1564. #define VHA_CR_OS0_MMU_CBASE_MAPPING_INVALID_EN (0X10000000U)
  1565. #define VHA_CR_OS0_MMU_CBASE_MAPPING_BASE_ADDR_SHIFT (0U)
  1566. #define VHA_CR_OS0_MMU_CBASE_MAPPING_BASE_ADDR_CLRMSK (0XF0000000U)
  1567. #define VHA_CR_OS0_MMU_CBASE_MAPPING_BASE_ADDR_ALIGNSHIFT (12U)
  1568. #define VHA_CR_OS0_MMU_CBASE_MAPPING_BASE_ADDR_ALIGNSIZE (4096U)
  1569. /*
  1570. Register VHA_CR_OS0_MMU_FAULT_STATUS1
  1571. */
  1572. #define VHA_CR_OS0_MMU_FAULT_STATUS1 (0xE150U)
  1573. #define VHA_CR_OS0_MMU_FAULT_STATUS1_MASKFULL (IMG_UINT64_C(0xFFFFFFFFFFFFFFFF))
  1574. #define VHA_CR_OS0_MMU_FAULT_STATUS1_LEVEL_SHIFT (62U)
  1575. #define VHA_CR_OS0_MMU_FAULT_STATUS1_LEVEL_CLRMSK (IMG_UINT64_C(0X3FFFFFFFFFFFFFFF))
  1576. #define VHA_CR_OS0_MMU_FAULT_STATUS1_REQ_ID_SHIFT (56U)
  1577. #define VHA_CR_OS0_MMU_FAULT_STATUS1_REQ_ID_CLRMSK (IMG_UINT64_C(0XC0FFFFFFFFFFFFFF))
  1578. #define VHA_CR_OS0_MMU_FAULT_STATUS1_CONTEXT_SHIFT (48U)
  1579. #define VHA_CR_OS0_MMU_FAULT_STATUS1_CONTEXT_CLRMSK (IMG_UINT64_C(0XFF00FFFFFFFFFFFF))
  1580. #define VHA_CR_OS0_MMU_FAULT_STATUS1_ADDRESS_SHIFT (4U)
  1581. #define VHA_CR_OS0_MMU_FAULT_STATUS1_ADDRESS_CLRMSK (IMG_UINT64_C(0XFFFF00000000000F))
  1582. #define VHA_CR_OS0_MMU_FAULT_STATUS1_RNW_SHIFT (3U)
  1583. #define VHA_CR_OS0_MMU_FAULT_STATUS1_RNW_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFF7))
  1584. #define VHA_CR_OS0_MMU_FAULT_STATUS1_RNW_EN (IMG_UINT64_C(0X0000000000000008))
  1585. #define VHA_CR_OS0_MMU_FAULT_STATUS1_TYPE_SHIFT (1U)
  1586. #define VHA_CR_OS0_MMU_FAULT_STATUS1_TYPE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFF9))
  1587. #define VHA_CR_OS0_MMU_FAULT_STATUS1_FAULT_SHIFT (0U)
  1588. #define VHA_CR_OS0_MMU_FAULT_STATUS1_FAULT_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFE))
  1589. #define VHA_CR_OS0_MMU_FAULT_STATUS1_FAULT_EN (IMG_UINT64_C(0X0000000000000001))
  1590. /*
  1591. Register VHA_CR_OS0_MMU_FAULT_STATUS2
  1592. */
  1593. #define VHA_CR_OS0_MMU_FAULT_STATUS2 (0xE158U)
  1594. #define VHA_CR_OS0_MMU_FAULT_STATUS2_MASKFULL (IMG_UINT64_C(0x000000003FFF07FF))
  1595. #define VHA_CR_OS0_MMU_FAULT_STATUS2_WRITEBACK_SHIFT (29U)
  1596. #define VHA_CR_OS0_MMU_FAULT_STATUS2_WRITEBACK_CLRMSK (0XDFFFFFFFU)
  1597. #define VHA_CR_OS0_MMU_FAULT_STATUS2_WRITEBACK_EN (0X20000000U)
  1598. #define VHA_CR_OS0_MMU_FAULT_STATUS2_CLEANUNIQUE_SHIFT (28U)
  1599. #define VHA_CR_OS0_MMU_FAULT_STATUS2_CLEANUNIQUE_CLRMSK (0XEFFFFFFFU)
  1600. #define VHA_CR_OS0_MMU_FAULT_STATUS2_CLEANUNIQUE_EN (0X10000000U)
  1601. #define VHA_CR_OS0_MMU_FAULT_STATUS2_BANK_SHIFT (24U)
  1602. #define VHA_CR_OS0_MMU_FAULT_STATUS2_BANK_CLRMSK (0XF0FFFFFFU)
  1603. #define VHA_CR_OS0_MMU_FAULT_STATUS2_TLB_ENTRY_SHIFT (16U)
  1604. #define VHA_CR_OS0_MMU_FAULT_STATUS2_TLB_ENTRY_CLRMSK (0XFF00FFFFU)
  1605. #define VHA_CR_OS0_MMU_FAULT_STATUS2_FBM_FAULT_SHIFT (10U)
  1606. #define VHA_CR_OS0_MMU_FAULT_STATUS2_FBM_FAULT_CLRMSK (0XFFFFFBFFU)
  1607. #define VHA_CR_OS0_MMU_FAULT_STATUS2_FBM_FAULT_EN (0X00000400U)
  1608. #define VHA_CR_OS0_MMU_FAULT_STATUS2_BIF_ID_SHIFT (0U)
  1609. #define VHA_CR_OS0_MMU_FAULT_STATUS2_BIF_ID_CLRMSK (0XFFFFFC00U)
  1610. /*
  1611. Register VHA_CR_MMU_FAULT_STATUS_META
  1612. */
  1613. #define VHA_CR_MMU_FAULT_STATUS_META (0xE160U)
  1614. #define VHA_CR_MMU_FAULT_STATUS_META_MASKFULL (IMG_UINT64_C(0xFFFFFFFFFFFFFFFF))
  1615. #define VHA_CR_MMU_FAULT_STATUS_META_LEVEL_SHIFT (62U)
  1616. #define VHA_CR_MMU_FAULT_STATUS_META_LEVEL_CLRMSK (IMG_UINT64_C(0X3FFFFFFFFFFFFFFF))
  1617. #define VHA_CR_MMU_FAULT_STATUS_META_REQ_ID_SHIFT (56U)
  1618. #define VHA_CR_MMU_FAULT_STATUS_META_REQ_ID_CLRMSK (IMG_UINT64_C(0XC0FFFFFFFFFFFFFF))
  1619. #define VHA_CR_MMU_FAULT_STATUS_META_CONTEXT_SHIFT (48U)
  1620. #define VHA_CR_MMU_FAULT_STATUS_META_CONTEXT_CLRMSK (IMG_UINT64_C(0XFF00FFFFFFFFFFFF))
  1621. #define VHA_CR_MMU_FAULT_STATUS_META_ADDRESS_SHIFT (4U)
  1622. #define VHA_CR_MMU_FAULT_STATUS_META_ADDRESS_CLRMSK (IMG_UINT64_C(0XFFFF00000000000F))
  1623. #define VHA_CR_MMU_FAULT_STATUS_META_RNW_SHIFT (3U)
  1624. #define VHA_CR_MMU_FAULT_STATUS_META_RNW_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFF7))
  1625. #define VHA_CR_MMU_FAULT_STATUS_META_RNW_EN (IMG_UINT64_C(0X0000000000000008))
  1626. #define VHA_CR_MMU_FAULT_STATUS_META_TYPE_SHIFT (1U)
  1627. #define VHA_CR_MMU_FAULT_STATUS_META_TYPE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFF9))
  1628. #define VHA_CR_MMU_FAULT_STATUS_META_FAULT_SHIFT (0U)
  1629. #define VHA_CR_MMU_FAULT_STATUS_META_FAULT_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFE))
  1630. #define VHA_CR_MMU_FAULT_STATUS_META_FAULT_EN (IMG_UINT64_C(0X0000000000000001))
  1631. /*
  1632. Register VHA_CR_MMU_FAULT_STATUS2_META
  1633. */
  1634. #define VHA_CR_MMU_FAULT_STATUS2_META (0xE198U)
  1635. #define VHA_CR_MMU_FAULT_STATUS2_META_MASKFULL (IMG_UINT64_C(0x0000000000003FFF))
  1636. #define VHA_CR_MMU_FAULT_STATUS2_META_WRITEBACK_SHIFT (13U)
  1637. #define VHA_CR_MMU_FAULT_STATUS2_META_WRITEBACK_CLRMSK (0XFFFFDFFFU)
  1638. #define VHA_CR_MMU_FAULT_STATUS2_META_WRITEBACK_EN (0X00002000U)
  1639. #define VHA_CR_MMU_FAULT_STATUS2_META_CLEANUNIQUE_SHIFT (12U)
  1640. #define VHA_CR_MMU_FAULT_STATUS2_META_CLEANUNIQUE_CLRMSK (0XFFFFEFFFU)
  1641. #define VHA_CR_MMU_FAULT_STATUS2_META_CLEANUNIQUE_EN (0X00001000U)
  1642. #define VHA_CR_MMU_FAULT_STATUS2_META_BANK_SHIFT (8U)
  1643. #define VHA_CR_MMU_FAULT_STATUS2_META_BANK_CLRMSK (0XFFFFF0FFU)
  1644. #define VHA_CR_MMU_FAULT_STATUS2_META_TLB_ENTRY_SHIFT (0U)
  1645. #define VHA_CR_MMU_FAULT_STATUS2_META_TLB_ENTRY_CLRMSK (0XFFFFFF00U)
  1646. /*
  1647. Register VHA_CR_MMU_FAULT_STATUS_PM
  1648. */
  1649. #define VHA_CR_MMU_FAULT_STATUS_PM (0xE130U)
  1650. #define VHA_CR_MMU_FAULT_STATUS_PM_MASKFULL (IMG_UINT64_C(0x0000000007FFFFFF))
  1651. #define VHA_CR_MMU_FAULT_STATUS_PM_DM_SHIFT (24U)
  1652. #define VHA_CR_MMU_FAULT_STATUS_PM_DM_CLRMSK (IMG_UINT64_C(0XFFFFFFFFF8FFFFFF))
  1653. #define VHA_CR_MMU_FAULT_STATUS_PM_RNW_SHIFT (23U)
  1654. #define VHA_CR_MMU_FAULT_STATUS_PM_RNW_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFF7FFFFF))
  1655. #define VHA_CR_MMU_FAULT_STATUS_PM_RNW_EN (IMG_UINT64_C(0X0000000000800000))
  1656. #define VHA_CR_MMU_FAULT_STATUS_PM_ADDRESS_SHIFT (3U)
  1657. #define VHA_CR_MMU_FAULT_STATUS_PM_ADDRESS_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFF800007))
  1658. #define VHA_CR_MMU_FAULT_STATUS_PM_LEVEL_SHIFT (1U)
  1659. #define VHA_CR_MMU_FAULT_STATUS_PM_LEVEL_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFF9))
  1660. #define VHA_CR_MMU_FAULT_STATUS_PM_FAULT_SHIFT (0U)
  1661. #define VHA_CR_MMU_FAULT_STATUS_PM_FAULT_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFE))
  1662. #define VHA_CR_MMU_FAULT_STATUS_PM_FAULT_EN (IMG_UINT64_C(0X0000000000000001))
  1663. /*
  1664. Register VHA_CR_MMU_FAULT_ACCESS
  1665. */
  1666. #define VHA_CR_MMU_FAULT_ACCESS (0xE168U)
  1667. #define VHA_CR_MMU_FAULT_ACCESS_MASKFULL (IMG_UINT64_C(0x000000FFFFFFF000))
  1668. #define VHA_CR_MMU_FAULT_ACCESS_ADDRESS_SHIFT (12U)
  1669. #define VHA_CR_MMU_FAULT_ACCESS_ADDRESS_CLRMSK (IMG_UINT64_C(0XFFFFFF0000000FFF))
  1670. #define VHA_CR_MMU_FAULT_ACCESS_ADDRESS_ALIGNSHIFT (12U)
  1671. #define VHA_CR_MMU_FAULT_ACCESS_ADDRESS_ALIGNSIZE (4096U)
  1672. /*
  1673. Register VHA_CR_MMU_STATUS
  1674. */
  1675. #define VHA_CR_MMU_STATUS (0xE170U)
  1676. #define VHA_CR_MMU_STATUS_MASKFULL (IMG_UINT64_C(0x000001FFFFFFFFFF))
  1677. #define VHA_CR_MMU_STATUS_MMU_STALLED_SHIFT (40U)
  1678. #define VHA_CR_MMU_STATUS_MMU_STALLED_CLRMSK (IMG_UINT64_C(0XFFFFFEFFFFFFFFFF))
  1679. #define VHA_CR_MMU_STATUS_MMU_STALLED_EN (IMG_UINT64_C(0X0000010000000000))
  1680. #define VHA_CR_MMU_STATUS_PM_WRITES_SHIFT (38U)
  1681. #define VHA_CR_MMU_STATUS_PM_WRITES_CLRMSK (IMG_UINT64_C(0XFFFFFF3FFFFFFFFF))
  1682. #define VHA_CR_MMU_STATUS_PM_READS_SHIFT (36U)
  1683. #define VHA_CR_MMU_STATUS_PM_READS_CLRMSK (IMG_UINT64_C(0XFFFFFFCFFFFFFFFF))
  1684. #define VHA_CR_MMU_STATUS_PC_READS_SHIFT (24U)
  1685. #define VHA_CR_MMU_STATUS_PC_READS_CLRMSK (IMG_UINT64_C(0XFFFFFFF000FFFFFF))
  1686. #define VHA_CR_MMU_STATUS_PD_READS_SHIFT (12U)
  1687. #define VHA_CR_MMU_STATUS_PD_READS_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFF000FFF))
  1688. #define VHA_CR_MMU_STATUS_PT_READS_SHIFT (0U)
  1689. #define VHA_CR_MMU_STATUS_PT_READS_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFF000))
  1690. /*
  1691. Register VHA_CR_OS0_MMU_ENTRY_STATUS
  1692. */
  1693. #define VHA_CR_OS0_MMU_ENTRY_STATUS (0xE178U)
  1694. #define VHA_CR_OS0_MMU_ENTRY_STATUS_MASKFULL (IMG_UINT64_C(0x000000FFFFFF80FF))
  1695. #define VHA_CR_OS0_MMU_ENTRY_STATUS_ADDRESS_SHIFT (15U)
  1696. #define VHA_CR_OS0_MMU_ENTRY_STATUS_ADDRESS_CLRMSK (IMG_UINT64_C(0XFFFFFF0000007FFF))
  1697. #define VHA_CR_OS0_MMU_ENTRY_STATUS_CONTEXT_ID_SHIFT (0U)
  1698. #define VHA_CR_OS0_MMU_ENTRY_STATUS_CONTEXT_ID_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFF00))
  1699. /*
  1700. Register VHA_CR_OS0_MMU_ENTRY
  1701. */
  1702. #define VHA_CR_OS0_MMU_ENTRY (0xE180U)
  1703. #define VHA_CR_OS0_MMU_ENTRY_MASKFULL (IMG_UINT64_C(0x0000000000000003))
  1704. #define VHA_CR_OS0_MMU_ENTRY_ENABLE_SHIFT (1U)
  1705. #define VHA_CR_OS0_MMU_ENTRY_ENABLE_CLRMSK (0XFFFFFFFDU)
  1706. #define VHA_CR_OS0_MMU_ENTRY_ENABLE_EN (0X00000002U)
  1707. #define VHA_CR_OS0_MMU_ENTRY_PENDING_SHIFT (0U)
  1708. #define VHA_CR_OS0_MMU_ENTRY_PENDING_CLRMSK (0XFFFFFFFEU)
  1709. #define VHA_CR_OS0_MMU_ENTRY_PENDING_EN (0X00000001U)
  1710. /*
  1711. Register VHA_CR_MMU_ABORT_PM_CTRL
  1712. */
  1713. #define VHA_CR_MMU_ABORT_PM_CTRL (0xE188U)
  1714. #define VHA_CR_MMU_ABORT_PM_CTRL_MASKFULL (IMG_UINT64_C(0x0000000000000001))
  1715. #define VHA_CR_MMU_ABORT_PM_CTRL_ENABLE_SHIFT (0U)
  1716. #define VHA_CR_MMU_ABORT_PM_CTRL_ENABLE_CLRMSK (0XFFFFFFFEU)
  1717. #define VHA_CR_MMU_ABORT_PM_CTRL_ENABLE_EN (0X00000001U)
  1718. /*
  1719. Register VHA_CR_MMU_ABORT_PM_STATUS
  1720. */
  1721. #define VHA_CR_MMU_ABORT_PM_STATUS (0xE190U)
  1722. #define VHA_CR_MMU_ABORT_PM_STATUS_MASKFULL (IMG_UINT64_C(0x0000000000000001))
  1723. #define VHA_CR_MMU_ABORT_PM_STATUS_ABORT_SHIFT (0U)
  1724. #define VHA_CR_MMU_ABORT_PM_STATUS_ABORT_CLRMSK (0XFFFFFFFEU)
  1725. #define VHA_CR_MMU_ABORT_PM_STATUS_ABORT_EN (0X00000001U)
  1726. /*
  1727. Register VHA_CR_OS0_MMU_CTRL
  1728. */
  1729. #define VHA_CR_OS0_MMU_CTRL (0xE1A8U)
  1730. #define VHA_CR_OS0_MMU_CTRL_MASKFULL (IMG_UINT64_C(0x0000000000000001))
  1731. #define VHA_CR_OS0_MMU_CTRL_BYPASS_SHIFT (0U)
  1732. #define VHA_CR_OS0_MMU_CTRL_BYPASS_CLRMSK (0XFFFFFFFEU)
  1733. #define VHA_CR_OS0_MMU_CTRL_BYPASS_EN (0X00000001U)
  1734. #define VHA_CR_SLC_CTRL_ENUM_HASH_MODE_MASK (0x00000003U)
  1735. /*
  1736. Reserved value */
  1737. #define VHA_CR_SLC_CTRL_ENUM_HASH_MODE_RESERVED (0x00000000U)
  1738. /*
  1739. Addresses interleaved between Cache Bank using a combined Set & Bank hash of the upper address bits */
  1740. #define VHA_CR_SLC_CTRL_ENUM_HASH_MODE_PVR_V3_HASHING (0x00000001U)
  1741. /*
  1742. Addresses are interleaved between Cache Banks on a Cacheline boundary */
  1743. #define VHA_CR_SLC_CTRL_ENUM_HASH_MODE_LINEAR (0x00000002U)
  1744. /*
  1745. Addresses interleaved between Cache Banks using an XOR hash of the address bits below the 4KB page granularity */
  1746. #define VHA_CR_SLC_CTRL_ENUM_HASH_MODE_IN_PAGE_HASH (0x00000003U)
  1747. /*
  1748. Register VHA_CR_SLC_CTRL
  1749. */
  1750. #define VHA_CR_SLC_CTRL (0xE200U)
  1751. #define VHA_CR_SLC_CTRL_MASKFULL (IMG_UINT64_C(0x0000000000001FF3))
  1752. #define VHA_CR_SLC_CTRL_CFI_TIMEOUT_ENABLE_SHIFT (12U)
  1753. #define VHA_CR_SLC_CTRL_CFI_TIMEOUT_ENABLE_CLRMSK (0XFFFFEFFFU)
  1754. #define VHA_CR_SLC_CTRL_CFI_TIMEOUT_ENABLE_EN (0X00001000U)
  1755. #define VHA_CR_SLC_CTRL_CFI_TIMEOUT_CYCLES_SHIFT (8U)
  1756. #define VHA_CR_SLC_CTRL_CFI_TIMEOUT_CYCLES_CLRMSK (0XFFFFF0FFU)
  1757. #define VHA_CR_SLC_CTRL_PERSISTENCE_DECAY_ENABLE_SHIFT (7U)
  1758. #define VHA_CR_SLC_CTRL_PERSISTENCE_DECAY_ENABLE_CLRMSK (0XFFFFFF7FU)
  1759. #define VHA_CR_SLC_CTRL_PERSISTENCE_DECAY_ENABLE_EN (0X00000080U)
  1760. #define VHA_CR_SLC_CTRL_MAX_FENCES_SHIFT (4U)
  1761. #define VHA_CR_SLC_CTRL_MAX_FENCES_CLRMSK (0XFFFFFF8FU)
  1762. #define VHA_CR_SLC_CTRL_HASH_MODE_SHIFT (0U)
  1763. #define VHA_CR_SLC_CTRL_HASH_MODE_CLRMSK (0XFFFFFFFCU)
  1764. #define VHA_CR_SLC_CTRL_HASH_MODE_RESERVED (00000000U)
  1765. #define VHA_CR_SLC_CTRL_HASH_MODE_PVR_V3_HASHING (0X00000001U)
  1766. #define VHA_CR_SLC_CTRL_HASH_MODE_LINEAR (0X00000002U)
  1767. #define VHA_CR_SLC_CTRL_HASH_MODE_IN_PAGE_HASH (0X00000003U)
  1768. /*
  1769. Register VHA_CR_SLC_STATUS1
  1770. */
  1771. #define VHA_CR_SLC_STATUS1 (0xE210U)
  1772. #define VHA_CR_SLC_STATUS1_MASKFULL (IMG_UINT64_C(0xFFFFFFFFFFFFFFFF))
  1773. #define VHA_CR_SLC_STATUS1_XBAR_CFI_TIMEOUTS_SHIFT (48U)
  1774. #define VHA_CR_SLC_STATUS1_XBAR_CFI_TIMEOUTS_CLRMSK (IMG_UINT64_C(0X0000FFFFFFFFFFFF))
  1775. #define VHA_CR_SLC_STATUS1_BUS1_OUTSTANDING_WRITES_SHIFT (36U)
  1776. #define VHA_CR_SLC_STATUS1_BUS1_OUTSTANDING_WRITES_CLRMSK (IMG_UINT64_C(0XFFFF000FFFFFFFFF))
  1777. #define VHA_CR_SLC_STATUS1_BUS0_OUTSTANDING_WRITES_SHIFT (24U)
  1778. #define VHA_CR_SLC_STATUS1_BUS0_OUTSTANDING_WRITES_CLRMSK (IMG_UINT64_C(0XFFFFFFF000FFFFFF))
  1779. #define VHA_CR_SLC_STATUS1_BUS1_OUTSTANDING_READS_SHIFT (12U)
  1780. #define VHA_CR_SLC_STATUS1_BUS1_OUTSTANDING_READS_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFF000FFF))
  1781. #define VHA_CR_SLC_STATUS1_BUS0_OUTSTANDING_READS_SHIFT (0U)
  1782. #define VHA_CR_SLC_STATUS1_BUS0_OUTSTANDING_READS_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFF000))
  1783. /*
  1784. Register VHA_CR_SLC_STATUS2
  1785. */
  1786. #define VHA_CR_SLC_STATUS2 (0xE218U)
  1787. #define VHA_CR_SLC_STATUS2_MASKFULL (IMG_UINT64_C(0x0000FFFFFFFFFFFF))
  1788. #define VHA_CR_SLC_STATUS2_BUS3_OUTSTANDING_WRITES_SHIFT (36U)
  1789. #define VHA_CR_SLC_STATUS2_BUS3_OUTSTANDING_WRITES_CLRMSK (IMG_UINT64_C(0XFFFF000FFFFFFFFF))
  1790. #define VHA_CR_SLC_STATUS2_BUS2_OUTSTANDING_WRITES_SHIFT (24U)
  1791. #define VHA_CR_SLC_STATUS2_BUS2_OUTSTANDING_WRITES_CLRMSK (IMG_UINT64_C(0XFFFFFFF000FFFFFF))
  1792. #define VHA_CR_SLC_STATUS2_BUS3_OUTSTANDING_READS_SHIFT (12U)
  1793. #define VHA_CR_SLC_STATUS2_BUS3_OUTSTANDING_READS_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFF000FFF))
  1794. #define VHA_CR_SLC_STATUS2_BUS2_OUTSTANDING_READS_SHIFT (0U)
  1795. #define VHA_CR_SLC_STATUS2_BUS2_OUTSTANDING_READS_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFF000))
  1796. /*
  1797. Register VHA_CR_SLC_STATUS_BYP_COH_ERROR_READS
  1798. */
  1799. #define VHA_CR_SLC_STATUS_BYP_COH_ERROR_READS (0xE220U)
  1800. #define VHA_CR_SLC_STATUS_BYP_COH_ERROR_READS_MASKFULL (IMG_UINT64_C(0xFFFFFFFFFFFFFFFF))
  1801. #define VHA_CR_SLC_STATUS_BYP_COH_ERROR_READS_BANK3_SHIFT (48U)
  1802. #define VHA_CR_SLC_STATUS_BYP_COH_ERROR_READS_BANK3_CLRMSK (IMG_UINT64_C(0X0000FFFFFFFFFFFF))
  1803. #define VHA_CR_SLC_STATUS_BYP_COH_ERROR_READS_BANK2_SHIFT (32U)
  1804. #define VHA_CR_SLC_STATUS_BYP_COH_ERROR_READS_BANK2_CLRMSK (IMG_UINT64_C(0XFFFF0000FFFFFFFF))
  1805. #define VHA_CR_SLC_STATUS_BYP_COH_ERROR_READS_BANK1_SHIFT (16U)
  1806. #define VHA_CR_SLC_STATUS_BYP_COH_ERROR_READS_BANK1_CLRMSK (IMG_UINT64_C(0XFFFFFFFF0000FFFF))
  1807. #define VHA_CR_SLC_STATUS_BYP_COH_ERROR_READS_BANK0_SHIFT (0U)
  1808. #define VHA_CR_SLC_STATUS_BYP_COH_ERROR_READS_BANK0_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFF0000))
  1809. /*
  1810. Register VHA_CR_SLC_STATUS_BYP_COH_ERROR_WRITES
  1811. */
  1812. #define VHA_CR_SLC_STATUS_BYP_COH_ERROR_WRITES (0xE228U)
  1813. #define VHA_CR_SLC_STATUS_BYP_COH_ERROR_WRITES_MASKFULL (IMG_UINT64_C(0xFFFFFFFFFFFFFFFF))
  1814. #define VHA_CR_SLC_STATUS_BYP_COH_ERROR_WRITES_BANK3_SHIFT (48U)
  1815. #define VHA_CR_SLC_STATUS_BYP_COH_ERROR_WRITES_BANK3_CLRMSK (IMG_UINT64_C(0X0000FFFFFFFFFFFF))
  1816. #define VHA_CR_SLC_STATUS_BYP_COH_ERROR_WRITES_BANK2_SHIFT (32U)
  1817. #define VHA_CR_SLC_STATUS_BYP_COH_ERROR_WRITES_BANK2_CLRMSK (IMG_UINT64_C(0XFFFF0000FFFFFFFF))
  1818. #define VHA_CR_SLC_STATUS_BYP_COH_ERROR_WRITES_BANK1_SHIFT (16U)
  1819. #define VHA_CR_SLC_STATUS_BYP_COH_ERROR_WRITES_BANK1_CLRMSK (IMG_UINT64_C(0XFFFFFFFF0000FFFF))
  1820. #define VHA_CR_SLC_STATUS_BYP_COH_ERROR_WRITES_BANK0_SHIFT (0U)
  1821. #define VHA_CR_SLC_STATUS_BYP_COH_ERROR_WRITES_BANK0_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFF0000))
  1822. /*
  1823. Register VHA_CR_SLC_IDLE
  1824. */
  1825. #define VHA_CR_SLC_IDLE (0xE230U)
  1826. #define VHA_CR_SLC_IDLE_MASKFULL (IMG_UINT64_C(0x000000000000FFFF))
  1827. #define VHA_CR_SLC_IDLE_ACE_CONVERTERS_SHIFT (12U)
  1828. #define VHA_CR_SLC_IDLE_ACE_CONVERTERS_CLRMSK (0XFFFF0FFFU)
  1829. #define VHA_CR_SLC_IDLE_CACHE_BANKS_SHIFT (4U)
  1830. #define VHA_CR_SLC_IDLE_CACHE_BANKS_CLRMSK (0XFFFFF00FU)
  1831. #define VHA_CR_SLC_IDLE_MMU_SHIFT (3U)
  1832. #define VHA_CR_SLC_IDLE_MMU_CLRMSK (0XFFFFFFF7U)
  1833. #define VHA_CR_SLC_IDLE_MMU_EN (0X00000008U)
  1834. #define VHA_CR_SLC_IDLE_CCM_SHIFT (2U)
  1835. #define VHA_CR_SLC_IDLE_CCM_CLRMSK (0XFFFFFFFBU)
  1836. #define VHA_CR_SLC_IDLE_CCM_EN (0X00000004U)
  1837. #define VHA_CR_SLC_IDLE_RDI_SHIFT (1U)
  1838. #define VHA_CR_SLC_IDLE_RDI_CLRMSK (0XFFFFFFFDU)
  1839. #define VHA_CR_SLC_IDLE_RDI_EN (0X00000002U)
  1840. #define VHA_CR_SLC_IDLE_XBAR_SHIFT (0U)
  1841. #define VHA_CR_SLC_IDLE_XBAR_CLRMSK (0XFFFFFFFEU)
  1842. #define VHA_CR_SLC_IDLE_XBAR_EN (0X00000001U)
  1843. /*
  1844. Register VHA_CR_SLC_STATUS3
  1845. */
  1846. #define VHA_CR_SLC_STATUS3 (0xE238U)
  1847. #define VHA_CR_SLC_STATUS3_MASKFULL (IMG_UINT64_C(0x0FFFFFFFFFFFFFFF))
  1848. #define VHA_CR_SLC_STATUS3_MAX_CRITICAL_QOS_READ_LATENCY_SHIFT (50U)
  1849. #define VHA_CR_SLC_STATUS3_MAX_CRITICAL_QOS_READ_LATENCY_CLRMSK (IMG_UINT64_C(0XF003FFFFFFFFFFFF))
  1850. #define VHA_CR_SLC_STATUS3_MAX_LOW_QOS_READ_LATENCY_SHIFT (40U)
  1851. #define VHA_CR_SLC_STATUS3_MAX_LOW_QOS_READ_LATENCY_CLRMSK (IMG_UINT64_C(0XFFFC00FFFFFFFFFF))
  1852. #define VHA_CR_SLC_STATUS3_AVG_CRITICAL_QOS_READ_LATENCY_SHIFT (30U)
  1853. #define VHA_CR_SLC_STATUS3_AVG_CRITICAL_QOS_READ_LATENCY_CLRMSK (IMG_UINT64_C(0XFFFFFF003FFFFFFF))
  1854. #define VHA_CR_SLC_STATUS3_AVG_LOW_QOS_READ_LATENCY_SHIFT (20U)
  1855. #define VHA_CR_SLC_STATUS3_AVG_LOW_QOS_READ_LATENCY_CLRMSK (IMG_UINT64_C(0XFFFFFFFFC00FFFFF))
  1856. #define VHA_CR_SLC_STATUS3_MIN_CRITICAL_QOS_READ_LATENCY_SHIFT (10U)
  1857. #define VHA_CR_SLC_STATUS3_MIN_CRITICAL_QOS_READ_LATENCY_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFF003FF))
  1858. #define VHA_CR_SLC_STATUS3_MIN_LOW_QOS_READ_LATENCY_SHIFT (0U)
  1859. #define VHA_CR_SLC_STATUS3_MIN_LOW_QOS_READ_LATENCY_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFC00))
  1860. /*
  1861. Register VHA_CR_SLC_FAULT_STOP_STATUS
  1862. */
  1863. #define VHA_CR_SLC_FAULT_STOP_STATUS (0xE240U)
  1864. #define VHA_CR_SLC_FAULT_STOP_STATUS_MASKFULL (IMG_UINT64_C(0x000000000001FFFF))
  1865. #define VHA_CR_SLC_FAULT_STOP_STATUS_BIF_SHIFT (0U)
  1866. #define VHA_CR_SLC_FAULT_STOP_STATUS_BIF_CLRMSK (0XFFFE0000U)
  1867. /*
  1868. Register VHA_CR_SLC_FAULT_STOP_CTRL
  1869. */
  1870. #define VHA_CR_SLC_FAULT_STOP_CTRL (0xE248U)
  1871. #define VHA_CR_SLC_FAULT_STOP_CTRL_MASKFULL (IMG_UINT64_C(0x000000000003FFFF))
  1872. #define VHA_CR_SLC_FAULT_STOP_CTRL_ALL_SHIFT (17U)
  1873. #define VHA_CR_SLC_FAULT_STOP_CTRL_ALL_CLRMSK (0XFFFDFFFFU)
  1874. #define VHA_CR_SLC_FAULT_STOP_CTRL_ALL_EN (0X00020000U)
  1875. #define VHA_CR_SLC_FAULT_STOP_CTRL_ENABLE_SHIFT (0U)
  1876. #define VHA_CR_SLC_FAULT_STOP_CTRL_ENABLE_CLRMSK (0XFFFE0000U)
  1877. /*
  1878. Register VHA_CR_SLC_STATUS_DEBUG
  1879. */
  1880. #define VHA_CR_SLC_STATUS_DEBUG (0xE260U)
  1881. #define VHA_CR_SLC_STATUS_DEBUG_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  1882. #define VHA_CR_SLC_STATUS_DEBUG_ERR_COH_REQ_SHIFT (16U)
  1883. #define VHA_CR_SLC_STATUS_DEBUG_ERR_COH_REQ_CLRMSK (0X0000FFFFU)
  1884. #define VHA_CR_SLC_STATUS_DEBUG_ERR_ADDR_ALIAS_SHIFT (0U)
  1885. #define VHA_CR_SLC_STATUS_DEBUG_ERR_ADDR_ALIAS_CLRMSK (0XFFFF0000U)
  1886. /*
  1887. Register VHA_CR_SLC_CCM_CTRL
  1888. */
  1889. #define VHA_CR_SLC_CCM_CTRL (0xE300U)
  1890. #define VHA_CR_SLC_CCM_CTRL_MASKFULL (IMG_UINT64_C(0x0000000000FF00FF))
  1891. #define VHA_CR_SLC_CCM_CTRL_SPILL_AMOUNT_SHIFT (16U)
  1892. #define VHA_CR_SLC_CCM_CTRL_SPILL_AMOUNT_CLRMSK (0XFF00FFFFU)
  1893. #define VHA_CR_SLC_CCM_CTRL_SPILL_THRESHOLD_SHIFT (0U)
  1894. #define VHA_CR_SLC_CCM_CTRL_SPILL_THRESHOLD_CLRMSK (0XFFFFFF00U)
  1895. /*
  1896. Register VHA_CR_SLC_CCM_STATUS
  1897. */
  1898. #define VHA_CR_SLC_CCM_STATUS (0xE308U)
  1899. #define VHA_CR_SLC_CCM_STATUS_MASKFULL (IMG_UINT64_C(0x0FFFFFFFF10FF0FF))
  1900. #define VHA_CR_SLC_CCM_STATUS_SNOOP_COUNT3_SHIFT (52U)
  1901. #define VHA_CR_SLC_CCM_STATUS_SNOOP_COUNT3_CLRMSK (IMG_UINT64_C(0XF00FFFFFFFFFFFFF))
  1902. #define VHA_CR_SLC_CCM_STATUS_SNOOP_COUNT2_SHIFT (44U)
  1903. #define VHA_CR_SLC_CCM_STATUS_SNOOP_COUNT2_CLRMSK (IMG_UINT64_C(0XFFF00FFFFFFFFFFF))
  1904. #define VHA_CR_SLC_CCM_STATUS_SNOOP_COUNT1_SHIFT (36U)
  1905. #define VHA_CR_SLC_CCM_STATUS_SNOOP_COUNT1_CLRMSK (IMG_UINT64_C(0XFFFFF00FFFFFFFFF))
  1906. #define VHA_CR_SLC_CCM_STATUS_SNOOP_COUNT0_SHIFT (28U)
  1907. #define VHA_CR_SLC_CCM_STATUS_SNOOP_COUNT0_CLRMSK (IMG_UINT64_C(0XFFFFFFF00FFFFFFF))
  1908. #define VHA_CR_SLC_CCM_STATUS_SPILLING_SHIFT (24U)
  1909. #define VHA_CR_SLC_CCM_STATUS_SPILLING_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFEFFFFFF))
  1910. #define VHA_CR_SLC_CCM_STATUS_SPILLING_EN (IMG_UINT64_C(0X0000000001000000))
  1911. #define VHA_CR_SLC_CCM_STATUS_SPILL_ENTRIES_SHIFT (12U)
  1912. #define VHA_CR_SLC_CCM_STATUS_SPILL_ENTRIES_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFF00FFF))
  1913. #define VHA_CR_SLC_CCM_STATUS_ACTIVE_ENTRIES_SHIFT (0U)
  1914. #define VHA_CR_SLC_CCM_STATUS_ACTIVE_ENTRIES_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFF00))
  1915. /*
  1916. Register VHA_CR_ACE_QOS_CTRL
  1917. */
  1918. #define VHA_CR_ACE_QOS_CTRL (0xE310U)
  1919. #define VHA_CR_ACE_QOS_CTRL_MASKFULL (IMG_UINT64_C(0x000000000000FFFF))
  1920. #define VHA_CR_ACE_QOS_CTRL_CRITICAL_SHIFT (12U)
  1921. #define VHA_CR_ACE_QOS_CTRL_CRITICAL_CLRMSK (0XFFFF0FFFU)
  1922. #define VHA_CR_ACE_QOS_CTRL_HIGH_SHIFT (8U)
  1923. #define VHA_CR_ACE_QOS_CTRL_HIGH_CLRMSK (0XFFFFF0FFU)
  1924. #define VHA_CR_ACE_QOS_CTRL_MEDIUM_SHIFT (4U)
  1925. #define VHA_CR_ACE_QOS_CTRL_MEDIUM_CLRMSK (0XFFFFFF0FU)
  1926. #define VHA_CR_ACE_QOS_CTRL_LOW_SHIFT (0U)
  1927. #define VHA_CR_ACE_QOS_CTRL_LOW_CLRMSK (0XFFFFFFF0U)
  1928. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_ENUM_PRIORITIES_MASK (0x00000003U)
  1929. /*
  1930. Low */
  1931. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_ENUM_PRIORITIES_LOW (0x00000000U)
  1932. /*
  1933. Medium */
  1934. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_ENUM_PRIORITIES_MEDIUM (0x00000001U)
  1935. /*
  1936. High */
  1937. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_ENUM_PRIORITIES_HIGH (0x00000002U)
  1938. /*
  1939. Critical */
  1940. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_ENUM_PRIORITIES_CRITICAL (0x00000003U)
  1941. /*
  1942. Register VHA_CR_ACE_PRIORITY_MAPPING_CTRL
  1943. */
  1944. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL (0xE318U)
  1945. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_MASKFULL (IMG_UINT64_C(0xFFFFFFFFFFFFFFFF))
  1946. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_MMU_SHIFT (62U)
  1947. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_MMU_CLRMSK (IMG_UINT64_C(0X3FFFFFFFFFFFFFFF))
  1948. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_MMU_LOW (IMG_UINT64_C(0000000000000000))
  1949. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_MMU_MEDIUM (IMG_UINT64_C(0x4000000000000000))
  1950. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_MMU_HIGH (IMG_UINT64_C(0x8000000000000000))
  1951. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_MMU_CRITICAL (IMG_UINT64_C(0xc000000000000000))
  1952. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_UPS_SHIFT (60U)
  1953. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_UPS_CLRMSK (IMG_UINT64_C(0XCFFFFFFFFFFFFFFF))
  1954. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_UPS_LOW (IMG_UINT64_C(0000000000000000))
  1955. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_UPS_MEDIUM (IMG_UINT64_C(0x1000000000000000))
  1956. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_UPS_HIGH (IMG_UINT64_C(0x2000000000000000))
  1957. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_UPS_CRITICAL (IMG_UINT64_C(0x3000000000000000))
  1958. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_FBM_BSC_SHIFT (58U)
  1959. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_FBM_BSC_CLRMSK (IMG_UINT64_C(0XF3FFFFFFFFFFFFFF))
  1960. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_FBM_BSC_LOW (IMG_UINT64_C(0000000000000000))
  1961. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_FBM_BSC_MEDIUM (IMG_UINT64_C(0x0400000000000000))
  1962. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_FBM_BSC_HIGH (IMG_UINT64_C(0x0800000000000000))
  1963. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_FBM_BSC_CRITICAL (IMG_UINT64_C(0x0c00000000000000))
  1964. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_TUL_SHIFT (56U)
  1965. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_TUL_CLRMSK (IMG_UINT64_C(0XFCFFFFFFFFFFFFFF))
  1966. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_TUL_LOW (IMG_UINT64_C(0000000000000000))
  1967. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_TUL_MEDIUM (IMG_UINT64_C(0x0100000000000000))
  1968. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_TUL_HIGH (IMG_UINT64_C(0x0200000000000000))
  1969. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_TUL_CRITICAL (IMG_UINT64_C(0x0300000000000000))
  1970. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_SHR_SHIFT (54U)
  1971. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_SHR_CLRMSK (IMG_UINT64_C(0XFF3FFFFFFFFFFFFF))
  1972. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_SHR_LOW (IMG_UINT64_C(0000000000000000))
  1973. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_SHR_MEDIUM (IMG_UINT64_C(0x0040000000000000))
  1974. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_SHR_HIGH (IMG_UINT64_C(0x0080000000000000))
  1975. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_SHR_CRITICAL (IMG_UINT64_C(0x00c0000000000000))
  1976. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_FBA_SHIFT (52U)
  1977. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_FBA_CLRMSK (IMG_UINT64_C(0XFFCFFFFFFFFFFFFF))
  1978. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_FBA_LOW (IMG_UINT64_C(0000000000000000))
  1979. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_FBA_MEDIUM (IMG_UINT64_C(0x0010000000000000))
  1980. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_FBA_HIGH (IMG_UINT64_C(0x0020000000000000))
  1981. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_FBA_CRITICAL (IMG_UINT64_C(0x0030000000000000))
  1982. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_VDM_SHIFT (50U)
  1983. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_VDM_CLRMSK (IMG_UINT64_C(0XFFF3FFFFFFFFFFFF))
  1984. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_VDM_LOW (IMG_UINT64_C(0000000000000000))
  1985. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_VDM_MEDIUM (IMG_UINT64_C(0x0004000000000000))
  1986. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_VDM_HIGH (IMG_UINT64_C(0x0008000000000000))
  1987. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_VDM_CRITICAL (IMG_UINT64_C(0x000c000000000000))
  1988. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_USC_SHIFT (48U)
  1989. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_USC_CLRMSK (IMG_UINT64_C(0XFFFCFFFFFFFFFFFF))
  1990. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_USC_LOW (IMG_UINT64_C(0000000000000000))
  1991. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_USC_MEDIUM (IMG_UINT64_C(0x0001000000000000))
  1992. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_USC_HIGH (IMG_UINT64_C(0x0002000000000000))
  1993. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_USC_CRITICAL (IMG_UINT64_C(0x0003000000000000))
  1994. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_PDS_SHIFT (46U)
  1995. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_PDS_CLRMSK (IMG_UINT64_C(0XFFFF3FFFFFFFFFFF))
  1996. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_PDS_LOW (IMG_UINT64_C(0000000000000000))
  1997. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_PDS_MEDIUM (IMG_UINT64_C(0x0000400000000000))
  1998. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_PDS_HIGH (IMG_UINT64_C(0x0000800000000000))
  1999. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_PDS_CRITICAL (IMG_UINT64_C(0x0000c00000000000))
  2000. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_PDSRW_SHIFT (44U)
  2001. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_PDSRW_CLRMSK (IMG_UINT64_C(0XFFFFCFFFFFFFFFFF))
  2002. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_PDSRW_LOW (IMG_UINT64_C(0000000000000000))
  2003. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_PDSRW_MEDIUM (IMG_UINT64_C(0x0000100000000000))
  2004. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_PDSRW_HIGH (IMG_UINT64_C(0x0000200000000000))
  2005. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_PDSRW_CRITICAL (IMG_UINT64_C(0x0000300000000000))
  2006. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_TPF_SHIFT (42U)
  2007. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_TPF_CLRMSK (IMG_UINT64_C(0XFFFFF3FFFFFFFFFF))
  2008. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_TPF_LOW (IMG_UINT64_C(0000000000000000))
  2009. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_TPF_MEDIUM (IMG_UINT64_C(0x0000040000000000))
  2010. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_TPF_HIGH (IMG_UINT64_C(0x0000080000000000))
  2011. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_TPF_CRITICAL (IMG_UINT64_C(0x00000c0000000000))
  2012. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_SHF_SHG_SHIFT (40U)
  2013. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_SHF_SHG_CLRMSK (IMG_UINT64_C(0XFFFFFCFFFFFFFFFF))
  2014. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_SHF_SHG_LOW (IMG_UINT64_C(0000000000000000))
  2015. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_SHF_SHG_MEDIUM (IMG_UINT64_C(0x0000010000000000))
  2016. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_SHF_SHG_HIGH (IMG_UINT64_C(0x0000020000000000))
  2017. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_SHF_SHG_CRITICAL (IMG_UINT64_C(0x0000030000000000))
  2018. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_AMC_SHIFT (38U)
  2019. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_AMC_CLRMSK (IMG_UINT64_C(0XFFFFFF3FFFFFFFFF))
  2020. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_AMC_LOW (IMG_UINT64_C(0000000000000000))
  2021. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_AMC_MEDIUM (IMG_UINT64_C(0x0000004000000000))
  2022. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_AMC_HIGH (IMG_UINT64_C(0x0000008000000000))
  2023. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_AMC_CRITICAL (IMG_UINT64_C(0x000000c000000000))
  2024. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_RAC_SHIFT (36U)
  2025. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_RAC_CLRMSK (IMG_UINT64_C(0XFFFFFFCFFFFFFFFF))
  2026. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_RAC_LOW (IMG_UINT64_C(0000000000000000))
  2027. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_RAC_MEDIUM (IMG_UINT64_C(0x0000001000000000))
  2028. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_RAC_HIGH (IMG_UINT64_C(0x0000002000000000))
  2029. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_RAC_CRITICAL (IMG_UINT64_C(0x0000003000000000))
  2030. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_VCE_RTC_SHIFT (34U)
  2031. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_VCE_RTC_CLRMSK (IMG_UINT64_C(0XFFFFFFF3FFFFFFFF))
  2032. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_VCE_RTC_LOW (IMG_UINT64_C(0000000000000000))
  2033. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_VCE_RTC_MEDIUM (IMG_UINT64_C(0x0000000400000000))
  2034. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_VCE_RTC_HIGH (IMG_UINT64_C(0x0000000800000000))
  2035. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_VCE_RTC_CRITICAL (IMG_UINT64_C(0x0000000c00000000))
  2036. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_ISP_SHIFT (32U)
  2037. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_ISP_CLRMSK (IMG_UINT64_C(0XFFFFFFFCFFFFFFFF))
  2038. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_ISP_LOW (IMG_UINT64_C(0000000000000000))
  2039. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_ISP_MEDIUM (IMG_UINT64_C(0x0000000100000000))
  2040. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_ISP_HIGH (IMG_UINT64_C(0x0000000200000000))
  2041. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_ISP_CRITICAL (IMG_UINT64_C(0x0000000300000000))
  2042. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_PPP_SHIFT (30U)
  2043. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_PPP_CLRMSK (IMG_UINT64_C(0XFFFFFFFF3FFFFFFF))
  2044. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_PPP_LOW (IMG_UINT64_C(0000000000000000))
  2045. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_PPP_MEDIUM (IMG_UINT64_C(0x0000000040000000))
  2046. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_PPP_HIGH (IMG_UINT64_C(0x0000000080000000))
  2047. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_PPP_CRITICAL (IMG_UINT64_C(0x00000000c0000000))
  2048. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_IPF_SHIFT (28U)
  2049. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_IPF_CLRMSK (IMG_UINT64_C(0XFFFFFFFFCFFFFFFF))
  2050. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_IPF_LOW (IMG_UINT64_C(0000000000000000))
  2051. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_IPF_MEDIUM (IMG_UINT64_C(0x0000000010000000))
  2052. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_IPF_HIGH (IMG_UINT64_C(0x0000000020000000))
  2053. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_IPF_CRITICAL (IMG_UINT64_C(0x0000000030000000))
  2054. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_VCE_SHIFT (26U)
  2055. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_VCE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFF3FFFFFF))
  2056. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_VCE_LOW (IMG_UINT64_C(0000000000000000))
  2057. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_VCE_MEDIUM (IMG_UINT64_C(0x0000000004000000))
  2058. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_VCE_HIGH (IMG_UINT64_C(0x0000000008000000))
  2059. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_VCE_CRITICAL (IMG_UINT64_C(0x000000000c000000))
  2060. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_PBE_SHIFT (24U)
  2061. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_PBE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFCFFFFFF))
  2062. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_PBE_LOW (IMG_UINT64_C(0000000000000000))
  2063. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_PBE_MEDIUM (IMG_UINT64_C(0x0000000001000000))
  2064. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_PBE_HIGH (IMG_UINT64_C(0x0000000002000000))
  2065. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_PBE_CRITICAL (IMG_UINT64_C(0x0000000003000000))
  2066. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_TCU_SHIFT (22U)
  2067. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_TCU_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFF3FFFFF))
  2068. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_TCU_LOW (IMG_UINT64_C(0000000000000000))
  2069. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_TCU_MEDIUM (IMG_UINT64_C(0x0000000000400000))
  2070. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_TCU_HIGH (IMG_UINT64_C(0x0000000000800000))
  2071. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_TCU_CRITICAL (IMG_UINT64_C(0x0000000000c00000))
  2072. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_MCU_SHIFT (20U)
  2073. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_MCU_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFCFFFFF))
  2074. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_MCU_LOW (IMG_UINT64_C(0000000000000000))
  2075. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_MCU_MEDIUM (IMG_UINT64_C(0x0000000000100000))
  2076. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_MCU_HIGH (IMG_UINT64_C(0x0000000000200000))
  2077. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_MCU_CRITICAL (IMG_UINT64_C(0x0000000000300000))
  2078. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_RPM_SHIFT (18U)
  2079. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_RPM_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFF3FFFF))
  2080. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_RPM_LOW (IMG_UINT64_C(0000000000000000))
  2081. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_RPM_MEDIUM (IMG_UINT64_C(0x0000000000040000))
  2082. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_RPM_HIGH (IMG_UINT64_C(0x0000000000080000))
  2083. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_RPM_CRITICAL (IMG_UINT64_C(0x00000000000c0000))
  2084. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_RTU_SHIFT (16U)
  2085. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_RTU_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFCFFFF))
  2086. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_RTU_LOW (IMG_UINT64_C(0000000000000000))
  2087. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_RTU_MEDIUM (IMG_UINT64_C(0x0000000000010000))
  2088. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_RTU_HIGH (IMG_UINT64_C(0x0000000000020000))
  2089. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_RTU_CRITICAL (IMG_UINT64_C(0x0000000000030000))
  2090. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_TILING_SHIFT (14U)
  2091. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_TILING_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFF3FFF))
  2092. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_TILING_LOW (IMG_UINT64_C(0000000000000000))
  2093. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_TILING_MEDIUM (IMG_UINT64_C(0x0000000000004000))
  2094. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_TILING_HIGH (IMG_UINT64_C(0x0000000000008000))
  2095. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_TILING_CRITICAL (IMG_UINT64_C(0x000000000000c000))
  2096. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_META_DMA_SHIFT (12U)
  2097. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_META_DMA_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFCFFF))
  2098. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_META_DMA_LOW (IMG_UINT64_C(0000000000000000))
  2099. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_META_DMA_MEDIUM (IMG_UINT64_C(0x0000000000001000))
  2100. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_META_DMA_HIGH (IMG_UINT64_C(0x0000000000002000))
  2101. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_META_DMA_CRITICAL (IMG_UINT64_C(0x0000000000003000))
  2102. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_META_SHIFT (10U)
  2103. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_META_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFF3FF))
  2104. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_META_LOW (IMG_UINT64_C(0000000000000000))
  2105. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_META_MEDIUM (IMG_UINT64_C(0x0000000000000400))
  2106. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_META_HIGH (IMG_UINT64_C(0x0000000000000800))
  2107. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_META_CRITICAL (IMG_UINT64_C(0x0000000000000c00))
  2108. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_CDM_SHIFT (8U)
  2109. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_CDM_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFCFF))
  2110. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_CDM_LOW (IMG_UINT64_C(0000000000000000))
  2111. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_CDM_MEDIUM (IMG_UINT64_C(0x0000000000000100))
  2112. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_CDM_HIGH (IMG_UINT64_C(0x0000000000000200))
  2113. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_CDM_CRITICAL (IMG_UINT64_C(0x0000000000000300))
  2114. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_PM_SHIFT (6U)
  2115. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_PM_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFF3F))
  2116. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_PM_LOW (IMG_UINT64_C(0000000000000000))
  2117. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_PM_MEDIUM (IMG_UINT64_C(0x0000000000000040))
  2118. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_PM_HIGH (IMG_UINT64_C(0x0000000000000080))
  2119. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_PM_CRITICAL (IMG_UINT64_C(0x00000000000000c0))
  2120. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_TDM_SHIFT (4U)
  2121. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_TDM_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFCF))
  2122. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_TDM_LOW (IMG_UINT64_C(0000000000000000))
  2123. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_TDM_MEDIUM (IMG_UINT64_C(0x0000000000000010))
  2124. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_TDM_HIGH (IMG_UINT64_C(0x0000000000000020))
  2125. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_TDM_CRITICAL (IMG_UINT64_C(0x0000000000000030))
  2126. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_DCE_SHIFT (2U)
  2127. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_DCE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFF3))
  2128. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_DCE_LOW (IMG_UINT64_C(0000000000000000))
  2129. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_DCE_MEDIUM (IMG_UINT64_C(0x0000000000000004))
  2130. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_DCE_HIGH (IMG_UINT64_C(0x0000000000000008))
  2131. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_DCE_CRITICAL (IMG_UINT64_C(0x000000000000000c))
  2132. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_IPP_SHIFT (0U)
  2133. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_IPP_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFC))
  2134. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_IPP_LOW (IMG_UINT64_C(0000000000000000))
  2135. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_IPP_MEDIUM (IMG_UINT64_C(0x0000000000000001))
  2136. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_IPP_HIGH (IMG_UINT64_C(0x0000000000000002))
  2137. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_IPP_CRITICAL (IMG_UINT64_C(0x0000000000000003))
  2138. #define VHA_CR_ACE_CTRL_ENUM_WR_CACHEABLE_MASK (0x0000000FU)
  2139. /*
  2140. Device Non-bufferable */
  2141. #define VHA_CR_ACE_CTRL_ENUM_WR_CACHEABLE_DEVICE_NON_BUFFERABLE (0x00000000U)
  2142. /*
  2143. Device Bufferable */
  2144. #define VHA_CR_ACE_CTRL_ENUM_WR_CACHEABLE_DEVICE_BUFFERABLE (0x00000001U)
  2145. /*
  2146. Normal Non-cacheable Non-bufferable */
  2147. #define VHA_CR_ACE_CTRL_ENUM_WR_CACHEABLE_NORMAL_NC_NON_BUFFERABLE (0x00000002U)
  2148. /*
  2149. Normal Non-cacheable Bufferable */
  2150. #define VHA_CR_ACE_CTRL_ENUM_WR_CACHEABLE_NORMAL_NC_BUFFERABLE (0x00000003U)
  2151. /*
  2152. Write-through No-allocate */
  2153. #define VHA_CR_ACE_CTRL_ENUM_WR_CACHEABLE_WRITE_THROUGH_NO_ALLOCATE (0x00000006U)
  2154. /*
  2155. Write-through Write-allocate */
  2156. #define VHA_CR_ACE_CTRL_ENUM_WR_CACHEABLE_WRITE_THROUGH_WRITE_ALLOCATE (0x0000000eU)
  2157. /*
  2158. Write-back No-allocate */
  2159. #define VHA_CR_ACE_CTRL_ENUM_WR_CACHEABLE_WRITE_BACK_NO_ALLOCATE (0x00000007U)
  2160. /*
  2161. Write-back Write-allocate */
  2162. #define VHA_CR_ACE_CTRL_ENUM_WR_CACHEABLE_WRITE_BACK_WRITE_ALLOCATE (0x0000000fU)
  2163. #define VHA_CR_ACE_CTRL_ENUM_RD_CACHEABLE_MASK (0x0000000FU)
  2164. /*
  2165. Device Non-bufferable */
  2166. #define VHA_CR_ACE_CTRL_ENUM_RD_CACHEABLE_DEVICE_NON_BUFFERABLE (0x00000000U)
  2167. /*
  2168. Device Bufferable */
  2169. #define VHA_CR_ACE_CTRL_ENUM_RD_CACHEABLE_DEVICE_BUFFERABLE (0x00000001U)
  2170. /*
  2171. Normal Non-cacheable Non-bufferable */
  2172. #define VHA_CR_ACE_CTRL_ENUM_RD_CACHEABLE_NORMAL_NC_NON_BUFFERABLE (0x00000002U)
  2173. /*
  2174. Normal Non-cacheable Bufferable */
  2175. #define VHA_CR_ACE_CTRL_ENUM_RD_CACHEABLE_NORMAL_NC_BUFFERABLE (0x00000003U)
  2176. /*
  2177. Write-through No-allocate */
  2178. #define VHA_CR_ACE_CTRL_ENUM_RD_CACHEABLE_WRITE_THROUGH_NO_ALLOCATE (0x0000000aU)
  2179. /*
  2180. Write-through Read-allocate */
  2181. #define VHA_CR_ACE_CTRL_ENUM_RD_CACHEABLE_WRITE_THROUGH_READ_ALLOCATE (0x0000000eU)
  2182. /*
  2183. Write-back No-allocate */
  2184. #define VHA_CR_ACE_CTRL_ENUM_RD_CACHEABLE_WRITE_BACK_NO_ALLOCATE (0x0000000bU)
  2185. /*
  2186. Write-back Read-allocate */
  2187. #define VHA_CR_ACE_CTRL_ENUM_RD_CACHEABLE_WRITE_BACK_READ_ALLOCATE (0x0000000fU)
  2188. /*
  2189. Non-Shareable */
  2190. #define VHA_CR_ACE_CTRL_ENUM_NCOH_DOMAIN_NON_SHAREABLE (0x00000000U)
  2191. /*
  2192. System */
  2193. #define VHA_CR_ACE_CTRL_ENUM_NCOH_DOMAIN_SYSTEM (0x00000001U)
  2194. /*
  2195. Inner-Shareable */
  2196. #define VHA_CR_ACE_CTRL_ENUM_COH_DOMAIN_INNER_SHAREABLE (0x00000000U)
  2197. /*
  2198. Outer-Shareable */
  2199. #define VHA_CR_ACE_CTRL_ENUM_COH_DOMAIN_OUTER_SHAREABLE (0x00000001U)
  2200. /*
  2201. Register VHA_CR_ACE_CTRL
  2202. */
  2203. #define VHA_CR_ACE_CTRL (0xE320U)
  2204. #define VHA_CR_ACE_CTRL_MASKFULL (IMG_UINT64_C(0x00000000007FCFFF))
  2205. #define VHA_CR_ACE_CTRL_CLB_AXQOS_SHIFT (19U)
  2206. #define VHA_CR_ACE_CTRL_CLB_AXQOS_CLRMSK (0XFF87FFFFU)
  2207. #define VHA_CR_ACE_CTRL_PM_MMU_AXCACHE_SHIFT (15U)
  2208. #define VHA_CR_ACE_CTRL_PM_MMU_AXCACHE_CLRMSK (0XFFF87FFFU)
  2209. #define VHA_CR_ACE_CTRL_ENABLE_NONSECURE_PROT_MATCH_SHIFT (14U)
  2210. #define VHA_CR_ACE_CTRL_ENABLE_NONSECURE_PROT_MATCH_CLRMSK (0XFFFFBFFFU)
  2211. #define VHA_CR_ACE_CTRL_ENABLE_NONSECURE_PROT_MATCH_EN (0X00004000U)
  2212. #define VHA_CR_ACE_CTRL_MMU_AWCACHE_SHIFT (8U)
  2213. #define VHA_CR_ACE_CTRL_MMU_AWCACHE_CLRMSK (0XFFFFF0FFU)
  2214. #define VHA_CR_ACE_CTRL_MMU_AWCACHE_DEVICE_NON_BUFFERABLE (00000000U)
  2215. #define VHA_CR_ACE_CTRL_MMU_AWCACHE_DEVICE_BUFFERABLE (0X00000100U)
  2216. #define VHA_CR_ACE_CTRL_MMU_AWCACHE_NORMAL_NC_NON_BUFFERABLE (0X00000200U)
  2217. #define VHA_CR_ACE_CTRL_MMU_AWCACHE_NORMAL_NC_BUFFERABLE (0X00000300U)
  2218. #define VHA_CR_ACE_CTRL_MMU_AWCACHE_WRITE_THROUGH_NO_ALLOCATE (0X00000600U)
  2219. #define VHA_CR_ACE_CTRL_MMU_AWCACHE_WRITE_THROUGH_WRITE_ALLOCATE (0X00000E00U)
  2220. #define VHA_CR_ACE_CTRL_MMU_AWCACHE_WRITE_BACK_NO_ALLOCATE (0X00000700U)
  2221. #define VHA_CR_ACE_CTRL_MMU_AWCACHE_WRITE_BACK_WRITE_ALLOCATE (0X00000F00U)
  2222. #define VHA_CR_ACE_CTRL_MMU_ARCACHE_SHIFT (4U)
  2223. #define VHA_CR_ACE_CTRL_MMU_ARCACHE_CLRMSK (0XFFFFFF0FU)
  2224. #define VHA_CR_ACE_CTRL_MMU_ARCACHE_DEVICE_NON_BUFFERABLE (00000000U)
  2225. #define VHA_CR_ACE_CTRL_MMU_ARCACHE_DEVICE_BUFFERABLE (0X00000010U)
  2226. #define VHA_CR_ACE_CTRL_MMU_ARCACHE_NORMAL_NC_NON_BUFFERABLE (0X00000020U)
  2227. #define VHA_CR_ACE_CTRL_MMU_ARCACHE_NORMAL_NC_BUFFERABLE (0X00000030U)
  2228. #define VHA_CR_ACE_CTRL_MMU_ARCACHE_WRITE_THROUGH_NO_ALLOCATE (0X000000A0U)
  2229. #define VHA_CR_ACE_CTRL_MMU_ARCACHE_WRITE_THROUGH_READ_ALLOCATE (0X000000E0U)
  2230. #define VHA_CR_ACE_CTRL_MMU_ARCACHE_WRITE_BACK_NO_ALLOCATE (0X000000B0U)
  2231. #define VHA_CR_ACE_CTRL_MMU_ARCACHE_WRITE_BACK_READ_ALLOCATE (0X000000F0U)
  2232. #define VHA_CR_ACE_CTRL_MMU_DOMAIN_SHIFT (2U)
  2233. #define VHA_CR_ACE_CTRL_MMU_DOMAIN_CLRMSK (0XFFFFFFF3U)
  2234. #define VHA_CR_ACE_CTRL_COH_DOMAIN_SHIFT (1U)
  2235. #define VHA_CR_ACE_CTRL_COH_DOMAIN_CLRMSK (0XFFFFFFFDU)
  2236. #define VHA_CR_ACE_CTRL_COH_DOMAIN_INNER_SHAREABLE (00000000U)
  2237. #define VHA_CR_ACE_CTRL_COH_DOMAIN_OUTER_SHAREABLE (0X00000002U)
  2238. #define VHA_CR_ACE_CTRL_NON_COH_DOMAIN_SHIFT (0U)
  2239. #define VHA_CR_ACE_CTRL_NON_COH_DOMAIN_CLRMSK (0XFFFFFFFEU)
  2240. #define VHA_CR_ACE_CTRL_NON_COH_DOMAIN_NON_SHAREABLE (00000000U)
  2241. #define VHA_CR_ACE_CTRL_NON_COH_DOMAIN_SYSTEM (0X00000001U)
  2242. #define VHA_CR_ACE_PROT_CTRL_ENUM_PROT_MASK (0x00000007U)
  2243. /*
  2244. Unprivileged secure data access*/
  2245. #define VHA_CR_ACE_PROT_CTRL_ENUM_PROT_UNPRIVILEGED_SECURE_DATA (0x00000000U)
  2246. /*
  2247. Privileged secure data access*/
  2248. #define VHA_CR_ACE_PROT_CTRL_ENUM_PROT_PRIVILEGED_SECURE_DATA (0x00000001U)
  2249. /*
  2250. Unprivileged non-secure data access*/
  2251. #define VHA_CR_ACE_PROT_CTRL_ENUM_PROT_UNPRIVILEGED_NONSECURE_DATA (0x00000002U)
  2252. /*
  2253. Privileged non-secure data access*/
  2254. #define VHA_CR_ACE_PROT_CTRL_ENUM_PROT_PRIVILEGED_NONSECURE_DATA (0x00000003U)
  2255. /*
  2256. Unprivileged secure instruction access*/
  2257. #define VHA_CR_ACE_PROT_CTRL_ENUM_PROT_UNPRIVILEGED_SECURE_INSTRUCTION (0x00000004U)
  2258. /*
  2259. Privileged secure instruction access*/
  2260. #define VHA_CR_ACE_PROT_CTRL_ENUM_PROT_PRIVILEGED_SECURE_INSTRUCTION (0x00000005U)
  2261. /*
  2262. Unprivileged non-secure instruction access*/
  2263. #define VHA_CR_ACE_PROT_CTRL_ENUM_PROT_UNPRIVILEGED_NONSECURE_INSTRUCTION (0x00000006U)
  2264. /*
  2265. Privileged non-secure instruction access*/
  2266. #define VHA_CR_ACE_PROT_CTRL_ENUM_PROT_PRIVILEGED_NONSECURE_INSTRUCTION (0x00000007U)
  2267. /*
  2268. Register VHA_CR_ACE_PROT_CTRL
  2269. */
  2270. #define VHA_CR_ACE_PROT_CTRL (0xE328U)
  2271. #define VHA_CR_ACE_PROT_CTRL_MASKFULL (IMG_UINT64_C(0x0707070707070707))
  2272. #define VHA_CR_ACE_PROT_CTRL_OSID7_SHIFT (56U)
  2273. #define VHA_CR_ACE_PROT_CTRL_OSID7_CLRMSK (IMG_UINT64_C(0XF8FFFFFFFFFFFFFF))
  2274. #define VHA_CR_ACE_PROT_CTRL_OSID7_UNPRIVILEGED_SECURE_DATA (IMG_UINT64_C(0000000000000000))
  2275. #define VHA_CR_ACE_PROT_CTRL_OSID7_PRIVILEGED_SECURE_DATA (IMG_UINT64_C(0x0100000000000000))
  2276. #define VHA_CR_ACE_PROT_CTRL_OSID7_UNPRIVILEGED_NONSECURE_DATA (IMG_UINT64_C(0x0200000000000000))
  2277. #define VHA_CR_ACE_PROT_CTRL_OSID7_PRIVILEGED_NONSECURE_DATA (IMG_UINT64_C(0x0300000000000000))
  2278. #define VHA_CR_ACE_PROT_CTRL_OSID7_UNPRIVILEGED_SECURE_INSTRUCTION (IMG_UINT64_C(0x0400000000000000))
  2279. #define VHA_CR_ACE_PROT_CTRL_OSID7_PRIVILEGED_SECURE_INSTRUCTION (IMG_UINT64_C(0x0500000000000000))
  2280. #define VHA_CR_ACE_PROT_CTRL_OSID7_UNPRIVILEGED_NONSECURE_INSTRUCTION (IMG_UINT64_C(0x0600000000000000))
  2281. #define VHA_CR_ACE_PROT_CTRL_OSID7_PRIVILEGED_NONSECURE_INSTRUCTION (IMG_UINT64_C(0x0700000000000000))
  2282. #define VHA_CR_ACE_PROT_CTRL_OSID6_SHIFT (48U)
  2283. #define VHA_CR_ACE_PROT_CTRL_OSID6_CLRMSK (IMG_UINT64_C(0XFFF8FFFFFFFFFFFF))
  2284. #define VHA_CR_ACE_PROT_CTRL_OSID6_UNPRIVILEGED_SECURE_DATA (IMG_UINT64_C(0000000000000000))
  2285. #define VHA_CR_ACE_PROT_CTRL_OSID6_PRIVILEGED_SECURE_DATA (IMG_UINT64_C(0x0001000000000000))
  2286. #define VHA_CR_ACE_PROT_CTRL_OSID6_UNPRIVILEGED_NONSECURE_DATA (IMG_UINT64_C(0x0002000000000000))
  2287. #define VHA_CR_ACE_PROT_CTRL_OSID6_PRIVILEGED_NONSECURE_DATA (IMG_UINT64_C(0x0003000000000000))
  2288. #define VHA_CR_ACE_PROT_CTRL_OSID6_UNPRIVILEGED_SECURE_INSTRUCTION (IMG_UINT64_C(0x0004000000000000))
  2289. #define VHA_CR_ACE_PROT_CTRL_OSID6_PRIVILEGED_SECURE_INSTRUCTION (IMG_UINT64_C(0x0005000000000000))
  2290. #define VHA_CR_ACE_PROT_CTRL_OSID6_UNPRIVILEGED_NONSECURE_INSTRUCTION (IMG_UINT64_C(0x0006000000000000))
  2291. #define VHA_CR_ACE_PROT_CTRL_OSID6_PRIVILEGED_NONSECURE_INSTRUCTION (IMG_UINT64_C(0x0007000000000000))
  2292. #define VHA_CR_ACE_PROT_CTRL_OSID5_SHIFT (40U)
  2293. #define VHA_CR_ACE_PROT_CTRL_OSID5_CLRMSK (IMG_UINT64_C(0XFFFFF8FFFFFFFFFF))
  2294. #define VHA_CR_ACE_PROT_CTRL_OSID5_UNPRIVILEGED_SECURE_DATA (IMG_UINT64_C(0000000000000000))
  2295. #define VHA_CR_ACE_PROT_CTRL_OSID5_PRIVILEGED_SECURE_DATA (IMG_UINT64_C(0x0000010000000000))
  2296. #define VHA_CR_ACE_PROT_CTRL_OSID5_UNPRIVILEGED_NONSECURE_DATA (IMG_UINT64_C(0x0000020000000000))
  2297. #define VHA_CR_ACE_PROT_CTRL_OSID5_PRIVILEGED_NONSECURE_DATA (IMG_UINT64_C(0x0000030000000000))
  2298. #define VHA_CR_ACE_PROT_CTRL_OSID5_UNPRIVILEGED_SECURE_INSTRUCTION (IMG_UINT64_C(0x0000040000000000))
  2299. #define VHA_CR_ACE_PROT_CTRL_OSID5_PRIVILEGED_SECURE_INSTRUCTION (IMG_UINT64_C(0x0000050000000000))
  2300. #define VHA_CR_ACE_PROT_CTRL_OSID5_UNPRIVILEGED_NONSECURE_INSTRUCTION (IMG_UINT64_C(0x0000060000000000))
  2301. #define VHA_CR_ACE_PROT_CTRL_OSID5_PRIVILEGED_NONSECURE_INSTRUCTION (IMG_UINT64_C(0x0000070000000000))
  2302. #define VHA_CR_ACE_PROT_CTRL_OSID4_SHIFT (32U)
  2303. #define VHA_CR_ACE_PROT_CTRL_OSID4_CLRMSK (IMG_UINT64_C(0XFFFFFFF8FFFFFFFF))
  2304. #define VHA_CR_ACE_PROT_CTRL_OSID4_UNPRIVILEGED_SECURE_DATA (IMG_UINT64_C(0000000000000000))
  2305. #define VHA_CR_ACE_PROT_CTRL_OSID4_PRIVILEGED_SECURE_DATA (IMG_UINT64_C(0x0000000100000000))
  2306. #define VHA_CR_ACE_PROT_CTRL_OSID4_UNPRIVILEGED_NONSECURE_DATA (IMG_UINT64_C(0x0000000200000000))
  2307. #define VHA_CR_ACE_PROT_CTRL_OSID4_PRIVILEGED_NONSECURE_DATA (IMG_UINT64_C(0x0000000300000000))
  2308. #define VHA_CR_ACE_PROT_CTRL_OSID4_UNPRIVILEGED_SECURE_INSTRUCTION (IMG_UINT64_C(0x0000000400000000))
  2309. #define VHA_CR_ACE_PROT_CTRL_OSID4_PRIVILEGED_SECURE_INSTRUCTION (IMG_UINT64_C(0x0000000500000000))
  2310. #define VHA_CR_ACE_PROT_CTRL_OSID4_UNPRIVILEGED_NONSECURE_INSTRUCTION (IMG_UINT64_C(0x0000000600000000))
  2311. #define VHA_CR_ACE_PROT_CTRL_OSID4_PRIVILEGED_NONSECURE_INSTRUCTION (IMG_UINT64_C(0x0000000700000000))
  2312. #define VHA_CR_ACE_PROT_CTRL_OSID3_SHIFT (24U)
  2313. #define VHA_CR_ACE_PROT_CTRL_OSID3_CLRMSK (IMG_UINT64_C(0XFFFFFFFFF8FFFFFF))
  2314. #define VHA_CR_ACE_PROT_CTRL_OSID3_UNPRIVILEGED_SECURE_DATA (IMG_UINT64_C(0000000000000000))
  2315. #define VHA_CR_ACE_PROT_CTRL_OSID3_PRIVILEGED_SECURE_DATA (IMG_UINT64_C(0x0000000001000000))
  2316. #define VHA_CR_ACE_PROT_CTRL_OSID3_UNPRIVILEGED_NONSECURE_DATA (IMG_UINT64_C(0x0000000002000000))
  2317. #define VHA_CR_ACE_PROT_CTRL_OSID3_PRIVILEGED_NONSECURE_DATA (IMG_UINT64_C(0x0000000003000000))
  2318. #define VHA_CR_ACE_PROT_CTRL_OSID3_UNPRIVILEGED_SECURE_INSTRUCTION (IMG_UINT64_C(0x0000000004000000))
  2319. #define VHA_CR_ACE_PROT_CTRL_OSID3_PRIVILEGED_SECURE_INSTRUCTION (IMG_UINT64_C(0x0000000005000000))
  2320. #define VHA_CR_ACE_PROT_CTRL_OSID3_UNPRIVILEGED_NONSECURE_INSTRUCTION (IMG_UINT64_C(0x0000000006000000))
  2321. #define VHA_CR_ACE_PROT_CTRL_OSID3_PRIVILEGED_NONSECURE_INSTRUCTION (IMG_UINT64_C(0x0000000007000000))
  2322. #define VHA_CR_ACE_PROT_CTRL_OSID2_SHIFT (16U)
  2323. #define VHA_CR_ACE_PROT_CTRL_OSID2_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFF8FFFF))
  2324. #define VHA_CR_ACE_PROT_CTRL_OSID2_UNPRIVILEGED_SECURE_DATA (IMG_UINT64_C(0000000000000000))
  2325. #define VHA_CR_ACE_PROT_CTRL_OSID2_PRIVILEGED_SECURE_DATA (IMG_UINT64_C(0x0000000000010000))
  2326. #define VHA_CR_ACE_PROT_CTRL_OSID2_UNPRIVILEGED_NONSECURE_DATA (IMG_UINT64_C(0x0000000000020000))
  2327. #define VHA_CR_ACE_PROT_CTRL_OSID2_PRIVILEGED_NONSECURE_DATA (IMG_UINT64_C(0x0000000000030000))
  2328. #define VHA_CR_ACE_PROT_CTRL_OSID2_UNPRIVILEGED_SECURE_INSTRUCTION (IMG_UINT64_C(0x0000000000040000))
  2329. #define VHA_CR_ACE_PROT_CTRL_OSID2_PRIVILEGED_SECURE_INSTRUCTION (IMG_UINT64_C(0x0000000000050000))
  2330. #define VHA_CR_ACE_PROT_CTRL_OSID2_UNPRIVILEGED_NONSECURE_INSTRUCTION (IMG_UINT64_C(0x0000000000060000))
  2331. #define VHA_CR_ACE_PROT_CTRL_OSID2_PRIVILEGED_NONSECURE_INSTRUCTION (IMG_UINT64_C(0x0000000000070000))
  2332. #define VHA_CR_ACE_PROT_CTRL_OSID1_SHIFT (8U)
  2333. #define VHA_CR_ACE_PROT_CTRL_OSID1_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFF8FF))
  2334. #define VHA_CR_ACE_PROT_CTRL_OSID1_UNPRIVILEGED_SECURE_DATA (IMG_UINT64_C(0000000000000000))
  2335. #define VHA_CR_ACE_PROT_CTRL_OSID1_PRIVILEGED_SECURE_DATA (IMG_UINT64_C(0x0000000000000100))
  2336. #define VHA_CR_ACE_PROT_CTRL_OSID1_UNPRIVILEGED_NONSECURE_DATA (IMG_UINT64_C(0x0000000000000200))
  2337. #define VHA_CR_ACE_PROT_CTRL_OSID1_PRIVILEGED_NONSECURE_DATA (IMG_UINT64_C(0x0000000000000300))
  2338. #define VHA_CR_ACE_PROT_CTRL_OSID1_UNPRIVILEGED_SECURE_INSTRUCTION (IMG_UINT64_C(0x0000000000000400))
  2339. #define VHA_CR_ACE_PROT_CTRL_OSID1_PRIVILEGED_SECURE_INSTRUCTION (IMG_UINT64_C(0x0000000000000500))
  2340. #define VHA_CR_ACE_PROT_CTRL_OSID1_UNPRIVILEGED_NONSECURE_INSTRUCTION (IMG_UINT64_C(0x0000000000000600))
  2341. #define VHA_CR_ACE_PROT_CTRL_OSID1_PRIVILEGED_NONSECURE_INSTRUCTION (IMG_UINT64_C(0x0000000000000700))
  2342. #define VHA_CR_ACE_PROT_CTRL_OSID0_SHIFT (0U)
  2343. #define VHA_CR_ACE_PROT_CTRL_OSID0_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFF8))
  2344. #define VHA_CR_ACE_PROT_CTRL_OSID0_UNPRIVILEGED_SECURE_DATA (IMG_UINT64_C(0000000000000000))
  2345. #define VHA_CR_ACE_PROT_CTRL_OSID0_PRIVILEGED_SECURE_DATA (IMG_UINT64_C(0x0000000000000001))
  2346. #define VHA_CR_ACE_PROT_CTRL_OSID0_UNPRIVILEGED_NONSECURE_DATA (IMG_UINT64_C(0x0000000000000002))
  2347. #define VHA_CR_ACE_PROT_CTRL_OSID0_PRIVILEGED_NONSECURE_DATA (IMG_UINT64_C(0x0000000000000003))
  2348. #define VHA_CR_ACE_PROT_CTRL_OSID0_UNPRIVILEGED_SECURE_INSTRUCTION (IMG_UINT64_C(0x0000000000000004))
  2349. #define VHA_CR_ACE_PROT_CTRL_OSID0_PRIVILEGED_SECURE_INSTRUCTION (IMG_UINT64_C(0x0000000000000005))
  2350. #define VHA_CR_ACE_PROT_CTRL_OSID0_UNPRIVILEGED_NONSECURE_INSTRUCTION (IMG_UINT64_C(0x0000000000000006))
  2351. #define VHA_CR_ACE_PROT_CTRL_OSID0_PRIVILEGED_NONSECURE_INSTRUCTION (IMG_UINT64_C(0x0000000000000007))
  2352. /*
  2353. Register VHA_CR_ACE_STATUS
  2354. */
  2355. #define VHA_CR_ACE_STATUS (0xE330U)
  2356. #define VHA_CR_ACE_STATUS_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  2357. #define VHA_CR_ACE_STATUS_WR_BUS3_ERROR_SHIFT (28U)
  2358. #define VHA_CR_ACE_STATUS_WR_BUS3_ERROR_CLRMSK (0X0FFFFFFFU)
  2359. #define VHA_CR_ACE_STATUS_RD_BUS3_ERROR_SHIFT (24U)
  2360. #define VHA_CR_ACE_STATUS_RD_BUS3_ERROR_CLRMSK (0XF0FFFFFFU)
  2361. #define VHA_CR_ACE_STATUS_WR_BUS2_ERROR_SHIFT (20U)
  2362. #define VHA_CR_ACE_STATUS_WR_BUS2_ERROR_CLRMSK (0XFF0FFFFFU)
  2363. #define VHA_CR_ACE_STATUS_RD_BUS2_ERROR_SHIFT (16U)
  2364. #define VHA_CR_ACE_STATUS_RD_BUS2_ERROR_CLRMSK (0XFFF0FFFFU)
  2365. #define VHA_CR_ACE_STATUS_WR_BUS1_ERROR_SHIFT (12U)
  2366. #define VHA_CR_ACE_STATUS_WR_BUS1_ERROR_CLRMSK (0XFFFF0FFFU)
  2367. #define VHA_CR_ACE_STATUS_RD_BUS1_ERROR_SHIFT (8U)
  2368. #define VHA_CR_ACE_STATUS_RD_BUS1_ERROR_CLRMSK (0XFFFFF0FFU)
  2369. #define VHA_CR_ACE_STATUS_WR_BUS0_ERROR_SHIFT (4U)
  2370. #define VHA_CR_ACE_STATUS_WR_BUS0_ERROR_CLRMSK (0XFFFFFF0FU)
  2371. #define VHA_CR_ACE_STATUS_RD_BUS0_ERROR_SHIFT (0U)
  2372. #define VHA_CR_ACE_STATUS_RD_BUS0_ERROR_CLRMSK (0XFFFFFFF0U)
  2373. #define VHA_CR_SOC_AXI_ENUM_COH_MASK (0x00000003U)
  2374. /*
  2375. The SoC does not support any form of Coherency*/
  2376. #define VHA_CR_SOC_AXI_ENUM_COH_NO_COHERENCY (0x00000000U)
  2377. /*
  2378. The SoC supports ACE-Lite or I/O Coherency*/
  2379. #define VHA_CR_SOC_AXI_ENUM_COH_ACE_LITE_COHERENCY (0x00000001U)
  2380. /*
  2381. The SoC supports full ACE or 2-Way Coherency*/
  2382. #define VHA_CR_SOC_AXI_ENUM_COH_FULL_ACE_COHERENCY (0x00000002U)
  2383. /*
  2384. Register VHA_CR_SOC_AXI
  2385. */
  2386. #define VHA_CR_SOC_AXI (0xE338U)
  2387. #define VHA_CR_SOC_AXI_MASKFULL (IMG_UINT64_C(0x000000000000000F))
  2388. #define VHA_CR_SOC_AXI_NON_COHERENT_128_BYTE_BURST_SUPPORT_SHIFT (3U)
  2389. #define VHA_CR_SOC_AXI_NON_COHERENT_128_BYTE_BURST_SUPPORT_CLRMSK (0XFFFFFFF7U)
  2390. #define VHA_CR_SOC_AXI_NON_COHERENT_128_BYTE_BURST_SUPPORT_EN (0X00000008U)
  2391. #define VHA_CR_SOC_AXI_COHERENT_128_BYTE_BURST_SUPPORT_SHIFT (2U)
  2392. #define VHA_CR_SOC_AXI_COHERENT_128_BYTE_BURST_SUPPORT_CLRMSK (0XFFFFFFFBU)
  2393. #define VHA_CR_SOC_AXI_COHERENT_128_BYTE_BURST_SUPPORT_EN (0X00000004U)
  2394. #define VHA_CR_SOC_AXI_COHERENCY_SUPPORT_SHIFT (0U)
  2395. #define VHA_CR_SOC_AXI_COHERENCY_SUPPORT_CLRMSK (0XFFFFFFFCU)
  2396. #define VHA_CR_SOC_AXI_COHERENCY_SUPPORT_NO_COHERENCY (00000000U)
  2397. #define VHA_CR_SOC_AXI_COHERENCY_SUPPORT_ACE_LITE_COHERENCY (0X00000001U)
  2398. #define VHA_CR_SOC_AXI_COHERENCY_SUPPORT_FULL_ACE_COHERENCY (0X00000002U)
  2399. #define VHA_CR_L1_GLB_CTRL_ENUM_HASH_MODE_MASK (0x00000003U)
  2400. /*
  2401. Addresses interleaved between Cache Banks using a weaved XOR hash of address bits */
  2402. #define VHA_CR_L1_GLB_CTRL_ENUM_HASH_MODE_WEAVED_HASH (0x00000000U)
  2403. /*
  2404. Addresses interleaved between Cache Bank using a combined Set & Bank hash of the upper address bits */
  2405. #define VHA_CR_L1_GLB_CTRL_ENUM_HASH_MODE_PVR_V3_HASHING (0x00000001U)
  2406. /*
  2407. Register VHA_CR_L1_GLB_CTRL
  2408. */
  2409. #define VHA_CR_L1_GLB_CTRL (0xE400U)
  2410. #define VHA_CR_L1_GLB_CTRL_MASKFULL (IMG_UINT64_C(0x0000000000000003))
  2411. #define VHA_CR_L1_GLB_CTRL_HASH_MODE_SHIFT (0U)
  2412. #define VHA_CR_L1_GLB_CTRL_HASH_MODE_CLRMSK (0XFFFFFFFCU)
  2413. #define VHA_CR_L1_GLB_CTRL_HASH_MODE_WEAVED_HASH (00000000U)
  2414. #define VHA_CR_L1_GLB_CTRL_HASH_MODE_PVR_V3_HASHING (0X00000001U)
  2415. /*
  2416. Register VHA_CR_CONTEXT_MAPPING2
  2417. */
  2418. #define VHA_CR_CONTEXT_MAPPING2 (0xF088U)
  2419. #define VHA_CR_CONTEXT_MAPPING2_MASKFULL (IMG_UINT64_C(0x0000000000FFFFFF))
  2420. #define VHA_CR_CONTEXT_MAPPING2_ALIST0_SHIFT (16U)
  2421. #define VHA_CR_CONTEXT_MAPPING2_ALIST0_CLRMSK (0XFF00FFFFU)
  2422. #define VHA_CR_CONTEXT_MAPPING2_TE0_SHIFT (8U)
  2423. #define VHA_CR_CONTEXT_MAPPING2_TE0_CLRMSK (0XFFFF00FFU)
  2424. #define VHA_CR_CONTEXT_MAPPING2_VCE0_SHIFT (0U)
  2425. #define VHA_CR_CONTEXT_MAPPING2_VCE0_CLRMSK (0XFFFFFF00U)
  2426. /*
  2427. Register VHA_CR_CONTEXT_MAPPING3
  2428. */
  2429. #define VHA_CR_CONTEXT_MAPPING3 (0xF090U)
  2430. #define VHA_CR_CONTEXT_MAPPING3_MASKFULL (IMG_UINT64_C(0x0000000000FFFFFF))
  2431. #define VHA_CR_CONTEXT_MAPPING3_ALIST1_SHIFT (16U)
  2432. #define VHA_CR_CONTEXT_MAPPING3_ALIST1_CLRMSK (0XFF00FFFFU)
  2433. #define VHA_CR_CONTEXT_MAPPING3_TE1_SHIFT (8U)
  2434. #define VHA_CR_CONTEXT_MAPPING3_TE1_CLRMSK (0XFFFF00FFU)
  2435. #define VHA_CR_CONTEXT_MAPPING3_VCE1_SHIFT (0U)
  2436. #define VHA_CR_CONTEXT_MAPPING3_VCE1_CLRMSK (0XFFFFFF00U)
  2437. /*
  2438. Register VHA_CR_SLC_FIX
  2439. */
  2440. #define VHA_CR_SLC_FIX (0xF0D8U)
  2441. #define VHA_CR_SLC_FIX_MASKFULL (IMG_UINT64_C(0x000000000000FFFF))
  2442. #define VHA_CR_SLC_FIX_DISABLE_SHIFT (0U)
  2443. #define VHA_CR_SLC_FIX_DISABLE_CLRMSK (0XFFFF0000U)
  2444. /*
  2445. Register VHA_CR_PERF_SLC
  2446. */
  2447. #define VHA_CR_PERF_SLC (0xF0F0U)
  2448. #define VHA_CR_PERF_SLC_MASKFULL (IMG_UINT64_C(0x000000000FFFFFFF))
  2449. #define VHA_CR_PERF_SLC_EWO_REQ_RD_WORD_COUNTER_RESET_SHIFT (27U)
  2450. #define VHA_CR_PERF_SLC_EWO_REQ_RD_WORD_COUNTER_RESET_CLRMSK (0XF7FFFFFFU)
  2451. #define VHA_CR_PERF_SLC_EWO_REQ_RD_WORD_COUNTER_RESET_EN (0X08000000U)
  2452. #define VHA_CR_PERF_SLC_EWO_REQ_RD_COUNTER_RESET_SHIFT (26U)
  2453. #define VHA_CR_PERF_SLC_EWO_REQ_RD_COUNTER_RESET_CLRMSK (0XFBFFFFFFU)
  2454. #define VHA_CR_PERF_SLC_EWO_REQ_RD_COUNTER_RESET_EN (0X04000000U)
  2455. #define VHA_CR_PERF_SLC_MMU_REQ_RD_WORD_COUNTER_RESET_SHIFT (25U)
  2456. #define VHA_CR_PERF_SLC_MMU_REQ_RD_WORD_COUNTER_RESET_CLRMSK (0XFDFFFFFFU)
  2457. #define VHA_CR_PERF_SLC_MMU_REQ_RD_WORD_COUNTER_RESET_EN (0X02000000U)
  2458. #define VHA_CR_PERF_SLC_MMU_REQ_RD_COUNTER_RESET_SHIFT (24U)
  2459. #define VHA_CR_PERF_SLC_MMU_REQ_RD_COUNTER_RESET_CLRMSK (0XFEFFFFFFU)
  2460. #define VHA_CR_PERF_SLC_MMU_REQ_RD_COUNTER_RESET_EN (0X01000000U)
  2461. #define VHA_CR_PERF_SLC_OPK_REQ_WR_WORD_COUNTER_RESET_SHIFT (23U)
  2462. #define VHA_CR_PERF_SLC_OPK_REQ_WR_WORD_COUNTER_RESET_CLRMSK (0XFF7FFFFFU)
  2463. #define VHA_CR_PERF_SLC_OPK_REQ_WR_WORD_COUNTER_RESET_EN (0X00800000U)
  2464. #define VHA_CR_PERF_SLC_ABUF_REQ_RD_WORD_COUNTER_RESET_SHIFT (22U)
  2465. #define VHA_CR_PERF_SLC_ABUF_REQ_RD_WORD_COUNTER_RESET_CLRMSK (0XFFBFFFFFU)
  2466. #define VHA_CR_PERF_SLC_ABUF_REQ_RD_WORD_COUNTER_RESET_EN (0X00400000U)
  2467. #define VHA_CR_PERF_SLC_CBUF_REQ_RD_WORD_COUNTER_RESET_SHIFT (21U)
  2468. #define VHA_CR_PERF_SLC_CBUF_REQ_RD_WORD_COUNTER_RESET_CLRMSK (0XFFDFFFFFU)
  2469. #define VHA_CR_PERF_SLC_CBUF_REQ_RD_WORD_COUNTER_RESET_EN (0X00200000U)
  2470. #define VHA_CR_PERF_SLC_IBUF_REQ3_RD_WORD_COUNTER_RESET_SHIFT (20U)
  2471. #define VHA_CR_PERF_SLC_IBUF_REQ3_RD_WORD_COUNTER_RESET_CLRMSK (0XFFEFFFFFU)
  2472. #define VHA_CR_PERF_SLC_IBUF_REQ3_RD_WORD_COUNTER_RESET_EN (0X00100000U)
  2473. #define VHA_CR_PERF_SLC_IBUF_REQ2_RD_WORD_COUNTER_RESET_SHIFT (19U)
  2474. #define VHA_CR_PERF_SLC_IBUF_REQ2_RD_WORD_COUNTER_RESET_CLRMSK (0XFFF7FFFFU)
  2475. #define VHA_CR_PERF_SLC_IBUF_REQ2_RD_WORD_COUNTER_RESET_EN (0X00080000U)
  2476. #define VHA_CR_PERF_SLC_IBUF_REQ1_RD_WORD_COUNTER_RESET_SHIFT (18U)
  2477. #define VHA_CR_PERF_SLC_IBUF_REQ1_RD_WORD_COUNTER_RESET_CLRMSK (0XFFFBFFFFU)
  2478. #define VHA_CR_PERF_SLC_IBUF_REQ1_RD_WORD_COUNTER_RESET_EN (0X00040000U)
  2479. #define VHA_CR_PERF_SLC_IBUF_REQ0_RD_WORD_COUNTER_RESET_SHIFT (17U)
  2480. #define VHA_CR_PERF_SLC_IBUF_REQ0_RD_WORD_COUNTER_RESET_CLRMSK (0XFFFDFFFFU)
  2481. #define VHA_CR_PERF_SLC_IBUF_REQ0_RD_WORD_COUNTER_RESET_EN (0X00020000U)
  2482. #define VHA_CR_PERF_SLC_CMD_REQ_FENCE_WORD_COUNTER_RESET_SHIFT (16U)
  2483. #define VHA_CR_PERF_SLC_CMD_REQ_FENCE_WORD_COUNTER_RESET_CLRMSK (0XFFFEFFFFU)
  2484. #define VHA_CR_PERF_SLC_CMD_REQ_FENCE_WORD_COUNTER_RESET_EN (0X00010000U)
  2485. #define VHA_CR_PERF_SLC_CMD_DBG_REQ_WR_WORD_COUNTER_RESET_SHIFT (15U)
  2486. #define VHA_CR_PERF_SLC_CMD_DBG_REQ_WR_WORD_COUNTER_RESET_CLRMSK (0XFFFF7FFFU)
  2487. #define VHA_CR_PERF_SLC_CMD_DBG_REQ_WR_WORD_COUNTER_RESET_EN (0X00008000U)
  2488. #define VHA_CR_PERF_SLC_CMD_CRC_REQ_WR_WORD_COUNTER_RESET_SHIFT (14U)
  2489. #define VHA_CR_PERF_SLC_CMD_CRC_REQ_WR_WORD_COUNTER_RESET_CLRMSK (0XFFFFBFFFU)
  2490. #define VHA_CR_PERF_SLC_CMD_CRC_REQ_WR_WORD_COUNTER_RESET_EN (0X00004000U)
  2491. #define VHA_CR_PERF_SLC_CMD_BCK_REQ_WR_WORD_COUNTER_RESET_SHIFT (13U)
  2492. #define VHA_CR_PERF_SLC_CMD_BCK_REQ_WR_WORD_COUNTER_RESET_CLRMSK (0XFFFFDFFFU)
  2493. #define VHA_CR_PERF_SLC_CMD_BCK_REQ_WR_WORD_COUNTER_RESET_EN (0X00002000U)
  2494. #define VHA_CR_PERF_SLC_CMD_REQ_RD_WORD_COUNTER_RESET_SHIFT (12U)
  2495. #define VHA_CR_PERF_SLC_CMD_REQ_RD_WORD_COUNTER_RESET_CLRMSK (0XFFFFEFFFU)
  2496. #define VHA_CR_PERF_SLC_CMD_REQ_RD_WORD_COUNTER_RESET_EN (0X00001000U)
  2497. #define VHA_CR_PERF_SLC_OPK_REQ_WR_COUNTER_RESET_SHIFT (11U)
  2498. #define VHA_CR_PERF_SLC_OPK_REQ_WR_COUNTER_RESET_CLRMSK (0XFFFFF7FFU)
  2499. #define VHA_CR_PERF_SLC_OPK_REQ_WR_COUNTER_RESET_EN (0X00000800U)
  2500. #define VHA_CR_PERF_SLC_ABUF_REQ_RD_COUNTER_RESET_SHIFT (10U)
  2501. #define VHA_CR_PERF_SLC_ABUF_REQ_RD_COUNTER_RESET_CLRMSK (0XFFFFFBFFU)
  2502. #define VHA_CR_PERF_SLC_ABUF_REQ_RD_COUNTER_RESET_EN (0X00000400U)
  2503. #define VHA_CR_PERF_SLC_CBUF_REQ_RD_COUNTER_RESET_SHIFT (9U)
  2504. #define VHA_CR_PERF_SLC_CBUF_REQ_RD_COUNTER_RESET_CLRMSK (0XFFFFFDFFU)
  2505. #define VHA_CR_PERF_SLC_CBUF_REQ_RD_COUNTER_RESET_EN (0X00000200U)
  2506. #define VHA_CR_PERF_SLC_IBUF_REQ3_RD_COUNTER_RESET_SHIFT (8U)
  2507. #define VHA_CR_PERF_SLC_IBUF_REQ3_RD_COUNTER_RESET_CLRMSK (0XFFFFFEFFU)
  2508. #define VHA_CR_PERF_SLC_IBUF_REQ3_RD_COUNTER_RESET_EN (0X00000100U)
  2509. #define VHA_CR_PERF_SLC_IBUF_REQ2_RD_COUNTER_RESET_SHIFT (7U)
  2510. #define VHA_CR_PERF_SLC_IBUF_REQ2_RD_COUNTER_RESET_CLRMSK (0XFFFFFF7FU)
  2511. #define VHA_CR_PERF_SLC_IBUF_REQ2_RD_COUNTER_RESET_EN (0X00000080U)
  2512. #define VHA_CR_PERF_SLC_IBUF_REQ1_RD_COUNTER_RESET_SHIFT (6U)
  2513. #define VHA_CR_PERF_SLC_IBUF_REQ1_RD_COUNTER_RESET_CLRMSK (0XFFFFFFBFU)
  2514. #define VHA_CR_PERF_SLC_IBUF_REQ1_RD_COUNTER_RESET_EN (0X00000040U)
  2515. #define VHA_CR_PERF_SLC_IBUF_REQ0_RD_COUNTER_RESET_SHIFT (5U)
  2516. #define VHA_CR_PERF_SLC_IBUF_REQ0_RD_COUNTER_RESET_CLRMSK (0XFFFFFFDFU)
  2517. #define VHA_CR_PERF_SLC_IBUF_REQ0_RD_COUNTER_RESET_EN (0X00000020U)
  2518. #define VHA_CR_PERF_SLC_CMD_REQ_FENCE_COUNTER_RESET_SHIFT (4U)
  2519. #define VHA_CR_PERF_SLC_CMD_REQ_FENCE_COUNTER_RESET_CLRMSK (0XFFFFFFEFU)
  2520. #define VHA_CR_PERF_SLC_CMD_REQ_FENCE_COUNTER_RESET_EN (0X00000010U)
  2521. #define VHA_CR_PERF_SLC_CMD_DBG_REQ_WR_COUNTER_RESET_SHIFT (3U)
  2522. #define VHA_CR_PERF_SLC_CMD_DBG_REQ_WR_COUNTER_RESET_CLRMSK (0XFFFFFFF7U)
  2523. #define VHA_CR_PERF_SLC_CMD_DBG_REQ_WR_COUNTER_RESET_EN (0X00000008U)
  2524. #define VHA_CR_PERF_SLC_CMD_CRC_REQ_WR_COUNTER_RESET_SHIFT (2U)
  2525. #define VHA_CR_PERF_SLC_CMD_CRC_REQ_WR_COUNTER_RESET_CLRMSK (0XFFFFFFFBU)
  2526. #define VHA_CR_PERF_SLC_CMD_CRC_REQ_WR_COUNTER_RESET_EN (0X00000004U)
  2527. #define VHA_CR_PERF_SLC_CMD_BCK_REQ_WR_COUNTER_RESET_SHIFT (1U)
  2528. #define VHA_CR_PERF_SLC_CMD_BCK_REQ_WR_COUNTER_RESET_CLRMSK (0XFFFFFFFDU)
  2529. #define VHA_CR_PERF_SLC_CMD_BCK_REQ_WR_COUNTER_RESET_EN (0X00000002U)
  2530. #define VHA_CR_PERF_SLC_CMD_REQ_RD_COUNTER_RESET_SHIFT (0U)
  2531. #define VHA_CR_PERF_SLC_CMD_REQ_RD_COUNTER_RESET_CLRMSK (0XFFFFFFFEU)
  2532. #define VHA_CR_PERF_SLC_CMD_REQ_RD_COUNTER_RESET_EN (0X00000001U)
  2533. /*
  2534. Register VHA_CR_PERF_SLC_REQ_COUNT
  2535. */
  2536. #define VHA_CR_PERF_SLC_REQ_COUNT (0xF0F8U)
  2537. #define VHA_CR_PERF_SLC_REQ_COUNT_MASKFULL (IMG_UINT64_C(0x0000000000000001))
  2538. #define VHA_CR_PERF_SLC_REQ_COUNT_ENABLE_SHIFT (0U)
  2539. #define VHA_CR_PERF_SLC_REQ_COUNT_ENABLE_CLRMSK (0XFFFFFFFEU)
  2540. #define VHA_CR_PERF_SLC_REQ_COUNT_ENABLE_EN (0X00000001U)
  2541. /*
  2542. Register VHA_CR_PERF_SLC_CMD_REQ_RD
  2543. */
  2544. #define VHA_CR_PERF_SLC_CMD_REQ_RD (0xF110U)
  2545. #define VHA_CR_PERF_SLC_CMD_REQ_RD_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  2546. #define VHA_CR_PERF_SLC_CMD_REQ_RD_COUNTER_SHIFT (0U)
  2547. #define VHA_CR_PERF_SLC_CMD_REQ_RD_COUNTER_CLRMSK (00000000U)
  2548. /*
  2549. Register VHA_CR_PERF_SLC_CMD_BCK_REQ_WR
  2550. */
  2551. #define VHA_CR_PERF_SLC_CMD_BCK_REQ_WR (0xF118U)
  2552. #define VHA_CR_PERF_SLC_CMD_BCK_REQ_WR_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  2553. #define VHA_CR_PERF_SLC_CMD_BCK_REQ_WR_COUNTER_SHIFT (0U)
  2554. #define VHA_CR_PERF_SLC_CMD_BCK_REQ_WR_COUNTER_CLRMSK (00000000U)
  2555. /*
  2556. Register VHA_CR_PERF_SLC_CMD_CRC_REQ_WR
  2557. */
  2558. #define VHA_CR_PERF_SLC_CMD_CRC_REQ_WR (0xF120U)
  2559. #define VHA_CR_PERF_SLC_CMD_CRC_REQ_WR_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  2560. #define VHA_CR_PERF_SLC_CMD_CRC_REQ_WR_COUNTER_SHIFT (0U)
  2561. #define VHA_CR_PERF_SLC_CMD_CRC_REQ_WR_COUNTER_CLRMSK (00000000U)
  2562. /*
  2563. Register VHA_CR_PERF_SLC_CMD_DBG_REQ_WR
  2564. */
  2565. #define VHA_CR_PERF_SLC_CMD_DBG_REQ_WR (0xF128U)
  2566. #define VHA_CR_PERF_SLC_CMD_DBG_REQ_WR_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  2567. #define VHA_CR_PERF_SLC_CMD_DBG_REQ_WR_COUNTER_SHIFT (0U)
  2568. #define VHA_CR_PERF_SLC_CMD_DBG_REQ_WR_COUNTER_CLRMSK (00000000U)
  2569. /*
  2570. Register VHA_CR_PERF_SLC_CMD_REQ_FENCE
  2571. */
  2572. #define VHA_CR_PERF_SLC_CMD_REQ_FENCE (0xF130U)
  2573. #define VHA_CR_PERF_SLC_CMD_REQ_FENCE_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  2574. #define VHA_CR_PERF_SLC_CMD_REQ_FENCE_COUNTER_SHIFT (0U)
  2575. #define VHA_CR_PERF_SLC_CMD_REQ_FENCE_COUNTER_CLRMSK (00000000U)
  2576. /*
  2577. Register VHA_CR_PERF_SLC_IBUF_REQ0_RD
  2578. */
  2579. #define VHA_CR_PERF_SLC_IBUF_REQ0_RD (0xF138U)
  2580. #define VHA_CR_PERF_SLC_IBUF_REQ0_RD_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  2581. #define VHA_CR_PERF_SLC_IBUF_REQ0_RD_COUNTER_SHIFT (0U)
  2582. #define VHA_CR_PERF_SLC_IBUF_REQ0_RD_COUNTER_CLRMSK (00000000U)
  2583. /*
  2584. Register VHA_CR_PERF_SLC_IBUF_REQ1_RD
  2585. */
  2586. #define VHA_CR_PERF_SLC_IBUF_REQ1_RD (0xF140U)
  2587. #define VHA_CR_PERF_SLC_IBUF_REQ1_RD_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  2588. #define VHA_CR_PERF_SLC_IBUF_REQ1_RD_COUNTER_SHIFT (0U)
  2589. #define VHA_CR_PERF_SLC_IBUF_REQ1_RD_COUNTER_CLRMSK (00000000U)
  2590. /*
  2591. Register VHA_CR_PERF_SLC_IBUF_REQ2_RD
  2592. */
  2593. #define VHA_CR_PERF_SLC_IBUF_REQ2_RD (0xF148U)
  2594. #define VHA_CR_PERF_SLC_IBUF_REQ2_RD_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  2595. #define VHA_CR_PERF_SLC_IBUF_REQ2_RD_COUNTER_SHIFT (0U)
  2596. #define VHA_CR_PERF_SLC_IBUF_REQ2_RD_COUNTER_CLRMSK (00000000U)
  2597. /*
  2598. Register VHA_CR_PERF_SLC_IBUF_REQ3_RD
  2599. */
  2600. #define VHA_CR_PERF_SLC_IBUF_REQ3_RD (0xF150U)
  2601. #define VHA_CR_PERF_SLC_IBUF_REQ3_RD_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  2602. #define VHA_CR_PERF_SLC_IBUF_REQ3_RD_COUNTER_SHIFT (0U)
  2603. #define VHA_CR_PERF_SLC_IBUF_REQ3_RD_COUNTER_CLRMSK (00000000U)
  2604. /*
  2605. Register VHA_CR_PERF_SLC_CBUF_REQ_RD
  2606. */
  2607. #define VHA_CR_PERF_SLC_CBUF_REQ_RD (0xF158U)
  2608. #define VHA_CR_PERF_SLC_CBUF_REQ_RD_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  2609. #define VHA_CR_PERF_SLC_CBUF_REQ_RD_COUNTER_SHIFT (0U)
  2610. #define VHA_CR_PERF_SLC_CBUF_REQ_RD_COUNTER_CLRMSK (00000000U)
  2611. /*
  2612. Register VHA_CR_PERF_SLC_ABUF_REQ_RD
  2613. */
  2614. #define VHA_CR_PERF_SLC_ABUF_REQ_RD (0xF160U)
  2615. #define VHA_CR_PERF_SLC_ABUF_REQ_RD_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  2616. #define VHA_CR_PERF_SLC_ABUF_REQ_RD_COUNTER_SHIFT (0U)
  2617. #define VHA_CR_PERF_SLC_ABUF_REQ_RD_COUNTER_CLRMSK (00000000U)
  2618. /*
  2619. Register VHA_CR_PERF_SLC_OPK_REQ_WR
  2620. */
  2621. #define VHA_CR_PERF_SLC_OPK_REQ_WR (0xF168U)
  2622. #define VHA_CR_PERF_SLC_OPK_REQ_WR_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  2623. #define VHA_CR_PERF_SLC_OPK_REQ_WR_COUNTER_SHIFT (0U)
  2624. #define VHA_CR_PERF_SLC_OPK_REQ_WR_COUNTER_CLRMSK (00000000U)
  2625. /*
  2626. Register VHA_CR_PERF_SLC_CMD_REQ_RD_WORD
  2627. */
  2628. #define VHA_CR_PERF_SLC_CMD_REQ_RD_WORD (0xF170U)
  2629. #define VHA_CR_PERF_SLC_CMD_REQ_RD_WORD_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  2630. #define VHA_CR_PERF_SLC_CMD_REQ_RD_WORD_COUNTER_SHIFT (0U)
  2631. #define VHA_CR_PERF_SLC_CMD_REQ_RD_WORD_COUNTER_CLRMSK (00000000U)
  2632. /*
  2633. Register VHA_CR_PERF_SLC_CMD_BCK_REQ_WR_WORD
  2634. */
  2635. #define VHA_CR_PERF_SLC_CMD_BCK_REQ_WR_WORD (0xF178U)
  2636. #define VHA_CR_PERF_SLC_CMD_BCK_REQ_WR_WORD_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  2637. #define VHA_CR_PERF_SLC_CMD_BCK_REQ_WR_WORD_COUNTER_SHIFT (0U)
  2638. #define VHA_CR_PERF_SLC_CMD_BCK_REQ_WR_WORD_COUNTER_CLRMSK (00000000U)
  2639. /*
  2640. Register VHA_CR_PERF_SLC_CMD_CRC_REQ_WR_WORD
  2641. */
  2642. #define VHA_CR_PERF_SLC_CMD_CRC_REQ_WR_WORD (0xF180U)
  2643. #define VHA_CR_PERF_SLC_CMD_CRC_REQ_WR_WORD_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  2644. #define VHA_CR_PERF_SLC_CMD_CRC_REQ_WR_WORD_COUNTER_SHIFT (0U)
  2645. #define VHA_CR_PERF_SLC_CMD_CRC_REQ_WR_WORD_COUNTER_CLRMSK (00000000U)
  2646. /*
  2647. Register VHA_CR_PERF_SLC_CMD_DBG_REQ_WR_WORD
  2648. */
  2649. #define VHA_CR_PERF_SLC_CMD_DBG_REQ_WR_WORD (0xF188U)
  2650. #define VHA_CR_PERF_SLC_CMD_DBG_REQ_WR_WORD_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  2651. #define VHA_CR_PERF_SLC_CMD_DBG_REQ_WR_WORD_COUNTER_SHIFT (0U)
  2652. #define VHA_CR_PERF_SLC_CMD_DBG_REQ_WR_WORD_COUNTER_CLRMSK (00000000U)
  2653. /*
  2654. Register VHA_CR_PERF_SLC_CMD_REQ_FENCE_WORD
  2655. */
  2656. #define VHA_CR_PERF_SLC_CMD_REQ_FENCE_WORD (0xF190U)
  2657. #define VHA_CR_PERF_SLC_CMD_REQ_FENCE_WORD_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  2658. #define VHA_CR_PERF_SLC_CMD_REQ_FENCE_WORD_COUNTER_SHIFT (0U)
  2659. #define VHA_CR_PERF_SLC_CMD_REQ_FENCE_WORD_COUNTER_CLRMSK (00000000U)
  2660. /*
  2661. Register VHA_CR_PERF_SLC_IBUF_REQ0_RD_WORD
  2662. */
  2663. #define VHA_CR_PERF_SLC_IBUF_REQ0_RD_WORD (0xF198U)
  2664. #define VHA_CR_PERF_SLC_IBUF_REQ0_RD_WORD_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  2665. #define VHA_CR_PERF_SLC_IBUF_REQ0_RD_WORD_COUNTER_SHIFT (0U)
  2666. #define VHA_CR_PERF_SLC_IBUF_REQ0_RD_WORD_COUNTER_CLRMSK (00000000U)
  2667. /*
  2668. Register VHA_CR_PERF_SLC_IBUF_REQ1_RD_WORD
  2669. */
  2670. #define VHA_CR_PERF_SLC_IBUF_REQ1_RD_WORD (0xF1A0U)
  2671. #define VHA_CR_PERF_SLC_IBUF_REQ1_RD_WORD_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  2672. #define VHA_CR_PERF_SLC_IBUF_REQ1_RD_WORD_COUNTER_SHIFT (0U)
  2673. #define VHA_CR_PERF_SLC_IBUF_REQ1_RD_WORD_COUNTER_CLRMSK (00000000U)
  2674. /*
  2675. Register VHA_CR_PERF_SLC_IBUF_REQ2_RD_WORD
  2676. */
  2677. #define VHA_CR_PERF_SLC_IBUF_REQ2_RD_WORD (0xF1A8U)
  2678. #define VHA_CR_PERF_SLC_IBUF_REQ2_RD_WORD_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  2679. #define VHA_CR_PERF_SLC_IBUF_REQ2_RD_WORD_COUNTER_SHIFT (0U)
  2680. #define VHA_CR_PERF_SLC_IBUF_REQ2_RD_WORD_COUNTER_CLRMSK (00000000U)
  2681. /*
  2682. Register VHA_CR_PERF_SLC_IBUF_REQ3_RD_WORD
  2683. */
  2684. #define VHA_CR_PERF_SLC_IBUF_REQ3_RD_WORD (0xF1B0U)
  2685. #define VHA_CR_PERF_SLC_IBUF_REQ3_RD_WORD_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  2686. #define VHA_CR_PERF_SLC_IBUF_REQ3_RD_WORD_COUNTER_SHIFT (0U)
  2687. #define VHA_CR_PERF_SLC_IBUF_REQ3_RD_WORD_COUNTER_CLRMSK (00000000U)
  2688. /*
  2689. Register VHA_CR_PERF_SLC_CBUF_REQ_RD_WORD
  2690. */
  2691. #define VHA_CR_PERF_SLC_CBUF_REQ_RD_WORD (0xF1B8U)
  2692. #define VHA_CR_PERF_SLC_CBUF_REQ_RD_WORD_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  2693. #define VHA_CR_PERF_SLC_CBUF_REQ_RD_WORD_COUNTER_SHIFT (0U)
  2694. #define VHA_CR_PERF_SLC_CBUF_REQ_RD_WORD_COUNTER_CLRMSK (00000000U)
  2695. /*
  2696. Register VHA_CR_PERF_SLC_ABUF_REQ_RD_WORD
  2697. */
  2698. #define VHA_CR_PERF_SLC_ABUF_REQ_RD_WORD (0xF1C0U)
  2699. #define VHA_CR_PERF_SLC_ABUF_REQ_RD_WORD_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  2700. #define VHA_CR_PERF_SLC_ABUF_REQ_RD_WORD_COUNTER_SHIFT (0U)
  2701. #define VHA_CR_PERF_SLC_ABUF_REQ_RD_WORD_COUNTER_CLRMSK (00000000U)
  2702. /*
  2703. Register VHA_CR_PERF_SLC_OPK_REQ_WR_WORD
  2704. */
  2705. #define VHA_CR_PERF_SLC_OPK_REQ_WR_WORD (0xF1C8U)
  2706. #define VHA_CR_PERF_SLC_OPK_REQ_WR_WORD_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  2707. #define VHA_CR_PERF_SLC_OPK_REQ_WR_WORD_COUNTER_SHIFT (0U)
  2708. #define VHA_CR_PERF_SLC_OPK_REQ_WR_WORD_COUNTER_CLRMSK (00000000U)
  2709. /*
  2710. Register VHA_CR_PERF_SLC_MMU_REQ_RD
  2711. */
  2712. #define VHA_CR_PERF_SLC_MMU_REQ_RD (0xF1D0U)
  2713. #define VHA_CR_PERF_SLC_MMU_REQ_RD_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  2714. #define VHA_CR_PERF_SLC_MMU_REQ_RD_COUNTER_SHIFT (0U)
  2715. #define VHA_CR_PERF_SLC_MMU_REQ_RD_COUNTER_CLRMSK (00000000U)
  2716. /*
  2717. Register VHA_CR_PERF_SLC_MMU_REQ_RD_WORD
  2718. */
  2719. #define VHA_CR_PERF_SLC_MMU_REQ_RD_WORD (0xF1D8U)
  2720. #define VHA_CR_PERF_SLC_MMU_REQ_RD_WORD_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  2721. #define VHA_CR_PERF_SLC_MMU_REQ_RD_WORD_COUNTER_SHIFT (0U)
  2722. #define VHA_CR_PERF_SLC_MMU_REQ_RD_WORD_COUNTER_CLRMSK (00000000U)
  2723. /*
  2724. Register VHA_CR_PERF_SLC_EWO_REQ_RD
  2725. */
  2726. #define VHA_CR_PERF_SLC_EWO_REQ_RD (0xF1E0U)
  2727. #define VHA_CR_PERF_SLC_EWO_REQ_RD_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  2728. #define VHA_CR_PERF_SLC_EWO_REQ_RD_COUNTER_SHIFT (0U)
  2729. #define VHA_CR_PERF_SLC_EWO_REQ_RD_COUNTER_CLRMSK (00000000U)
  2730. /*
  2731. Register VHA_CR_PERF_SLC_EWO_REQ_RD_WORD
  2732. */
  2733. #define VHA_CR_PERF_SLC_EWO_REQ_RD_WORD (0xF1E8U)
  2734. #define VHA_CR_PERF_SLC_EWO_REQ_RD_WORD_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  2735. #define VHA_CR_PERF_SLC_EWO_REQ_RD_WORD_COUNTER_SHIFT (0U)
  2736. #define VHA_CR_PERF_SLC_EWO_REQ_RD_WORD_COUNTER_CLRMSK (00000000U)
  2737. /*
  2738. Register VHA_CR_PWR_MAN_HYSTERESIS
  2739. */
  2740. #define VHA_CR_PWR_MAN_HYSTERESIS (0xF100U)
  2741. #define VHA_CR_PWR_MAN_HYSTERESIS_MASKFULL (IMG_UINT64_C(0x000000000000001F))
  2742. #define VHA_CR_PWR_MAN_HYSTERESIS_VALUE_SHIFT (0U)
  2743. #define VHA_CR_PWR_MAN_HYSTERESIS_VALUE_CLRMSK (0XFFFFFFE0U)
  2744. #endif /* _VHA_CR_MIRAGE_H_ */
  2745. /*****************************************************************************
  2746. End of file (vha_cr_mirage.h)
  2747. *****************************************************************************/