/*************************************************************************/ /*! @Title Hardware definition file vha_cr_mirage.h @Copyright Copyright (c) Imagination Technologies Ltd. All Rights Reserved */ /**************************************************************************/ /* **** Autogenerated C -- do not edit **** */ /* */ #ifndef _VHA_CR_MIRAGE_H_ #define _VHA_CR_MIRAGE_H_ #define VHA_CR_MIRAGE_REVISION 1 #define VHA_CR_MH_CONTROL_PERSISTENCE_TYPE_MASK (0x00000003U) #define VHA_CR_MH_CONTROL_MAX_BURST_LENGTH_MASK (0x00000003U) #define VHA_CR_CLK_CTRL0_MODE_MASK (0x00000003U) /* The domain clock is forced off */ #define VHA_CR_CLK_CTRL0_MODE_OFF (0x00000000U) /* The domain clock is forced on */ #define VHA_CR_CLK_CTRL0_MODE_ON (0x00000001U) /* Automatic clock gating is active, the domain clock is only on whilst data is being processed */ #define VHA_CR_CLK_CTRL0_MODE_AUTO (0x00000002U) /* Register VHA_CR_CLK_CTRL0 */ #define VHA_CR_CLK_CTRL0 (0x0000U) #define VHA_CR_CLK_CTRL0_MASKFULL (IMG_UINT64_C(0x03FFFFFF30000330)) #define VHA_CR_CLK_CTRL0_CNN_EWO_SHIFT (56U) #define VHA_CR_CLK_CTRL0_CNN_EWO_CLRMSK (IMG_UINT64_C(0XFCFFFFFFFFFFFFFF)) #define VHA_CR_CLK_CTRL0_CNN_EWO_OFF (IMG_UINT64_C(0000000000000000)) #define VHA_CR_CLK_CTRL0_CNN_EWO_ON (IMG_UINT64_C(0x0100000000000000)) #define VHA_CR_CLK_CTRL0_CNN_EWO_AUTO (IMG_UINT64_C(0x0200000000000000)) #define VHA_CR_CLK_CTRL0_CNN_PACK_SHIFT (54U) #define VHA_CR_CLK_CTRL0_CNN_PACK_CLRMSK (IMG_UINT64_C(0XFF3FFFFFFFFFFFFF)) #define VHA_CR_CLK_CTRL0_CNN_PACK_OFF (IMG_UINT64_C(0000000000000000)) #define VHA_CR_CLK_CTRL0_CNN_PACK_ON (IMG_UINT64_C(0x0040000000000000)) #define VHA_CR_CLK_CTRL0_CNN_PACK_AUTO (IMG_UINT64_C(0x0080000000000000)) #define VHA_CR_CLK_CTRL0_CNN_OIN_SHIFT (52U) #define VHA_CR_CLK_CTRL0_CNN_OIN_CLRMSK (IMG_UINT64_C(0XFFCFFFFFFFFFFFFF)) #define VHA_CR_CLK_CTRL0_CNN_OIN_OFF (IMG_UINT64_C(0000000000000000)) #define VHA_CR_CLK_CTRL0_CNN_OIN_ON (IMG_UINT64_C(0x0010000000000000)) #define VHA_CR_CLK_CTRL0_CNN_OIN_AUTO (IMG_UINT64_C(0x0020000000000000)) #define VHA_CR_CLK_CTRL0_CNN_POOL_SHIFT (50U) #define VHA_CR_CLK_CTRL0_CNN_POOL_CLRMSK (IMG_UINT64_C(0XFFF3FFFFFFFFFFFF)) #define VHA_CR_CLK_CTRL0_CNN_POOL_OFF (IMG_UINT64_C(0000000000000000)) #define VHA_CR_CLK_CTRL0_CNN_POOL_ON (IMG_UINT64_C(0x0004000000000000)) #define VHA_CR_CLK_CTRL0_CNN_POOL_AUTO (IMG_UINT64_C(0x0008000000000000)) #define VHA_CR_CLK_CTRL0_CNN_SB_SHIFT (48U) #define VHA_CR_CLK_CTRL0_CNN_SB_CLRMSK (IMG_UINT64_C(0XFFFCFFFFFFFFFFFF)) #define VHA_CR_CLK_CTRL0_CNN_SB_OFF (IMG_UINT64_C(0000000000000000)) #define VHA_CR_CLK_CTRL0_CNN_SB_ON (IMG_UINT64_C(0x0001000000000000)) #define VHA_CR_CLK_CTRL0_CNN_SB_AUTO (IMG_UINT64_C(0x0002000000000000)) #define VHA_CR_CLK_CTRL0_CNN_XBAR_SHIFT (46U) #define VHA_CR_CLK_CTRL0_CNN_XBAR_CLRMSK (IMG_UINT64_C(0XFFFF3FFFFFFFFFFF)) #define VHA_CR_CLK_CTRL0_CNN_XBAR_OFF (IMG_UINT64_C(0000000000000000)) #define VHA_CR_CLK_CTRL0_CNN_XBAR_ON (IMG_UINT64_C(0x0000400000000000)) #define VHA_CR_CLK_CTRL0_CNN_XBAR_AUTO (IMG_UINT64_C(0x0000800000000000)) #define VHA_CR_CLK_CTRL0_CNN_NORM_SHIFT (44U) #define VHA_CR_CLK_CTRL0_CNN_NORM_CLRMSK (IMG_UINT64_C(0XFFFFCFFFFFFFFFFF)) #define VHA_CR_CLK_CTRL0_CNN_NORM_OFF (IMG_UINT64_C(0000000000000000)) #define VHA_CR_CLK_CTRL0_CNN_NORM_ON (IMG_UINT64_C(0x0000100000000000)) #define VHA_CR_CLK_CTRL0_CNN_NORM_AUTO (IMG_UINT64_C(0x0000200000000000)) #define VHA_CR_CLK_CTRL0_CNN_ACT_SHIFT (42U) #define VHA_CR_CLK_CTRL0_CNN_ACT_CLRMSK (IMG_UINT64_C(0XFFFFF3FFFFFFFFFF)) #define VHA_CR_CLK_CTRL0_CNN_ACT_OFF (IMG_UINT64_C(0000000000000000)) #define VHA_CR_CLK_CTRL0_CNN_ACT_ON (IMG_UINT64_C(0x0000040000000000)) #define VHA_CR_CLK_CTRL0_CNN_ACT_AUTO (IMG_UINT64_C(0x0000080000000000)) #define VHA_CR_CLK_CTRL0_CNN_ACCUM_SHIFT (40U) #define VHA_CR_CLK_CTRL0_CNN_ACCUM_CLRMSK (IMG_UINT64_C(0XFFFFFCFFFFFFFFFF)) #define VHA_CR_CLK_CTRL0_CNN_ACCUM_OFF (IMG_UINT64_C(0000000000000000)) #define VHA_CR_CLK_CTRL0_CNN_ACCUM_ON (IMG_UINT64_C(0x0000010000000000)) #define VHA_CR_CLK_CTRL0_CNN_ACCUM_AUTO (IMG_UINT64_C(0x0000020000000000)) #define VHA_CR_CLK_CTRL0_CNN_CNV_SHIFT (38U) #define VHA_CR_CLK_CTRL0_CNN_CNV_CLRMSK (IMG_UINT64_C(0XFFFFFF3FFFFFFFFF)) #define VHA_CR_CLK_CTRL0_CNN_CNV_OFF (IMG_UINT64_C(0000000000000000)) #define VHA_CR_CLK_CTRL0_CNN_CNV_ON (IMG_UINT64_C(0x0000004000000000)) #define VHA_CR_CLK_CTRL0_CNN_CNV_AUTO (IMG_UINT64_C(0x0000008000000000)) #define VHA_CR_CLK_CTRL0_CNN_CBUF_SHIFT (36U) #define VHA_CR_CLK_CTRL0_CNN_CBUF_CLRMSK (IMG_UINT64_C(0XFFFFFFCFFFFFFFFF)) #define VHA_CR_CLK_CTRL0_CNN_CBUF_OFF (IMG_UINT64_C(0000000000000000)) #define VHA_CR_CLK_CTRL0_CNN_CBUF_ON (IMG_UINT64_C(0x0000001000000000)) #define VHA_CR_CLK_CTRL0_CNN_CBUF_AUTO (IMG_UINT64_C(0x0000002000000000)) #define VHA_CR_CLK_CTRL0_CNN_IBUF_SHIFT (34U) #define VHA_CR_CLK_CTRL0_CNN_IBUF_CLRMSK (IMG_UINT64_C(0XFFFFFFF3FFFFFFFF)) #define VHA_CR_CLK_CTRL0_CNN_IBUF_OFF (IMG_UINT64_C(0000000000000000)) #define VHA_CR_CLK_CTRL0_CNN_IBUF_ON (IMG_UINT64_C(0x0000000400000000)) #define VHA_CR_CLK_CTRL0_CNN_IBUF_AUTO (IMG_UINT64_C(0x0000000800000000)) #define VHA_CR_CLK_CTRL0_CNN_CMD_SHIFT (32U) #define VHA_CR_CLK_CTRL0_CNN_CMD_CLRMSK (IMG_UINT64_C(0XFFFFFFFCFFFFFFFF)) #define VHA_CR_CLK_CTRL0_CNN_CMD_OFF (IMG_UINT64_C(0000000000000000)) #define VHA_CR_CLK_CTRL0_CNN_CMD_ON (IMG_UINT64_C(0x0000000100000000)) #define VHA_CR_CLK_CTRL0_CNN_CMD_AUTO (IMG_UINT64_C(0x0000000200000000)) #define VHA_CR_CLK_CTRL0_CNN_SHIFT (28U) #define VHA_CR_CLK_CTRL0_CNN_CLRMSK (IMG_UINT64_C(0XFFFFFFFFCFFFFFFF)) #define VHA_CR_CLK_CTRL0_CNN_OFF (IMG_UINT64_C(0000000000000000)) #define VHA_CR_CLK_CTRL0_CNN_ON (IMG_UINT64_C(0x0000000010000000)) #define VHA_CR_CLK_CTRL0_CNN_AUTO (IMG_UINT64_C(0x0000000020000000)) #define VHA_CR_CLK_CTRL0_SLC_SHIFT (8U) #define VHA_CR_CLK_CTRL0_SLC_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFCFF)) #define VHA_CR_CLK_CTRL0_SLC_OFF (IMG_UINT64_C(0000000000000000)) #define VHA_CR_CLK_CTRL0_SLC_ON (IMG_UINT64_C(0x0000000000000100)) #define VHA_CR_CLK_CTRL0_SLC_AUTO (IMG_UINT64_C(0x0000000000000200)) #define VHA_CR_CLK_CTRL0_BIF_SHIFT (4U) #define VHA_CR_CLK_CTRL0_BIF_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFCF)) #define VHA_CR_CLK_CTRL0_BIF_OFF (IMG_UINT64_C(0000000000000000)) #define VHA_CR_CLK_CTRL0_BIF_ON (IMG_UINT64_C(0x0000000000000010)) #define VHA_CR_CLK_CTRL0_BIF_AUTO (IMG_UINT64_C(0x0000000000000020)) /* Clock is gated and the module is inactive */ #define VHA_CR_CLK_STATUS0_MODE_GATED (0x00000000U) /* Clock is running */ #define VHA_CR_CLK_STATUS0_MODE_RUNNING (0x00000001U) /* Register VHA_CR_CLK_STATUS0 */ #define VHA_CR_CLK_STATUS0 (0x0008U) #define VHA_CR_CLK_STATUS0_MASKFULL (IMG_UINT64_C(0x00000007FFD00104)) #define VHA_CR_CLK_STATUS0_CNN_EWO_SHIFT (34U) #define VHA_CR_CLK_STATUS0_CNN_EWO_CLRMSK (IMG_UINT64_C(0XFFFFFFFBFFFFFFFF)) #define VHA_CR_CLK_STATUS0_CNN_EWO_GATED (IMG_UINT64_C(0000000000000000)) #define VHA_CR_CLK_STATUS0_CNN_EWO_RUNNING (IMG_UINT64_C(0x0000000400000000)) #define VHA_CR_CLK_STATUS0_CNN_PACK_SHIFT (33U) #define VHA_CR_CLK_STATUS0_CNN_PACK_CLRMSK (IMG_UINT64_C(0XFFFFFFFDFFFFFFFF)) #define VHA_CR_CLK_STATUS0_CNN_PACK_GATED (IMG_UINT64_C(0000000000000000)) #define VHA_CR_CLK_STATUS0_CNN_PACK_RUNNING (IMG_UINT64_C(0x0000000200000000)) #define VHA_CR_CLK_STATUS0_CNN_OIN_SHIFT (32U) #define VHA_CR_CLK_STATUS0_CNN_OIN_CLRMSK (IMG_UINT64_C(0XFFFFFFFEFFFFFFFF)) #define VHA_CR_CLK_STATUS0_CNN_OIN_GATED (IMG_UINT64_C(0000000000000000)) #define VHA_CR_CLK_STATUS0_CNN_OIN_RUNNING (IMG_UINT64_C(0x0000000100000000)) #define VHA_CR_CLK_STATUS0_CNN_POOL_SHIFT (31U) #define VHA_CR_CLK_STATUS0_CNN_POOL_CLRMSK (IMG_UINT64_C(0XFFFFFFFF7FFFFFFF)) #define VHA_CR_CLK_STATUS0_CNN_POOL_GATED (IMG_UINT64_C(0000000000000000)) #define VHA_CR_CLK_STATUS0_CNN_POOL_RUNNING (IMG_UINT64_C(0x0000000080000000)) #define VHA_CR_CLK_STATUS0_CNN_SB_SHIFT (30U) #define VHA_CR_CLK_STATUS0_CNN_SB_CLRMSK (IMG_UINT64_C(0XFFFFFFFFBFFFFFFF)) #define VHA_CR_CLK_STATUS0_CNN_SB_GATED (IMG_UINT64_C(0000000000000000)) #define VHA_CR_CLK_STATUS0_CNN_SB_RUNNING (IMG_UINT64_C(0x0000000040000000)) #define VHA_CR_CLK_STATUS0_CNN_XBAR_SHIFT (29U) #define VHA_CR_CLK_STATUS0_CNN_XBAR_CLRMSK (IMG_UINT64_C(0XFFFFFFFFDFFFFFFF)) #define VHA_CR_CLK_STATUS0_CNN_XBAR_GATED (IMG_UINT64_C(0000000000000000)) #define VHA_CR_CLK_STATUS0_CNN_XBAR_RUNNING (IMG_UINT64_C(0x0000000020000000)) #define VHA_CR_CLK_STATUS0_CNN_NORM_SHIFT (28U) #define VHA_CR_CLK_STATUS0_CNN_NORM_CLRMSK (IMG_UINT64_C(0XFFFFFFFFEFFFFFFF)) #define VHA_CR_CLK_STATUS0_CNN_NORM_GATED (IMG_UINT64_C(0000000000000000)) #define VHA_CR_CLK_STATUS0_CNN_NORM_RUNNING (IMG_UINT64_C(0x0000000010000000)) #define VHA_CR_CLK_STATUS0_CNN_ACT_SHIFT (27U) #define VHA_CR_CLK_STATUS0_CNN_ACT_CLRMSK (IMG_UINT64_C(0XFFFFFFFFF7FFFFFF)) #define VHA_CR_CLK_STATUS0_CNN_ACT_GATED (IMG_UINT64_C(0000000000000000)) #define VHA_CR_CLK_STATUS0_CNN_ACT_RUNNING (IMG_UINT64_C(0x0000000008000000)) #define VHA_CR_CLK_STATUS0_CNN_ACCUM_SHIFT (26U) #define VHA_CR_CLK_STATUS0_CNN_ACCUM_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFBFFFFFF)) #define VHA_CR_CLK_STATUS0_CNN_ACCUM_GATED (IMG_UINT64_C(0000000000000000)) #define VHA_CR_CLK_STATUS0_CNN_ACCUM_RUNNING (IMG_UINT64_C(0x0000000004000000)) #define VHA_CR_CLK_STATUS0_CNN_CNV_SHIFT (25U) #define VHA_CR_CLK_STATUS0_CNN_CNV_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFDFFFFFF)) #define VHA_CR_CLK_STATUS0_CNN_CNV_GATED (IMG_UINT64_C(0000000000000000)) #define VHA_CR_CLK_STATUS0_CNN_CNV_RUNNING (IMG_UINT64_C(0x0000000002000000)) #define VHA_CR_CLK_STATUS0_CNN_CBUF_SHIFT (24U) #define VHA_CR_CLK_STATUS0_CNN_CBUF_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFEFFFFFF)) #define VHA_CR_CLK_STATUS0_CNN_CBUF_GATED (IMG_UINT64_C(0000000000000000)) #define VHA_CR_CLK_STATUS0_CNN_CBUF_RUNNING (IMG_UINT64_C(0x0000000001000000)) #define VHA_CR_CLK_STATUS0_CNN_IBUF_SHIFT (23U) #define VHA_CR_CLK_STATUS0_CNN_IBUF_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFF7FFFFF)) #define VHA_CR_CLK_STATUS0_CNN_IBUF_GATED (IMG_UINT64_C(0000000000000000)) #define VHA_CR_CLK_STATUS0_CNN_IBUF_RUNNING (IMG_UINT64_C(0x0000000000800000)) #define VHA_CR_CLK_STATUS0_CNN_CMD_SHIFT (22U) #define VHA_CR_CLK_STATUS0_CNN_CMD_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFBFFFFF)) #define VHA_CR_CLK_STATUS0_CNN_CMD_GATED (IMG_UINT64_C(0000000000000000)) #define VHA_CR_CLK_STATUS0_CNN_CMD_RUNNING (IMG_UINT64_C(0x0000000000400000)) #define VHA_CR_CLK_STATUS0_CNN_SHIFT (20U) #define VHA_CR_CLK_STATUS0_CNN_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFEFFFFF)) #define VHA_CR_CLK_STATUS0_CNN_GATED (IMG_UINT64_C(0000000000000000)) #define VHA_CR_CLK_STATUS0_CNN_RUNNING (IMG_UINT64_C(0x0000000000100000)) #define VHA_CR_CLK_STATUS0_SLC_SHIFT (8U) #define VHA_CR_CLK_STATUS0_SLC_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFEFF)) #define VHA_CR_CLK_STATUS0_SLC_GATED (IMG_UINT64_C(0000000000000000)) #define VHA_CR_CLK_STATUS0_SLC_RUNNING (IMG_UINT64_C(0x0000000000000100)) #define VHA_CR_CLK_STATUS0_BIF_SHIFT (2U) #define VHA_CR_CLK_STATUS0_BIF_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFB)) #define VHA_CR_CLK_STATUS0_BIF_GATED (IMG_UINT64_C(0000000000000000)) #define VHA_CR_CLK_STATUS0_BIF_RUNNING (IMG_UINT64_C(0x0000000000000004)) /* Register VHA_CR_PRODUCT_ID */ #define VHA_CR_PRODUCT_ID (0x0018U) #define VHA_CR_PRODUCT_ID_MASKFULL (IMG_UINT64_C(0x00000000FFFF0000)) #define VHA_CR_PRODUCT_ID_IMG_PRODUCT_ID_SHIFT (16U) #define VHA_CR_PRODUCT_ID_IMG_PRODUCT_ID_CLRMSK (IMG_UINT64_C(0XFFFFFFFF0000FFFF)) /* Register VHA_CR_CORE_ID */ #define VHA_CR_CORE_ID (0x0020U) #define VHA_CR_CORE_ID_MASKFULL (IMG_UINT64_C(0xFFFFFFFFFFFFFFFF)) #define VHA_CR_CORE_ID_BRANCH_ID_SHIFT (48U) #define VHA_CR_CORE_ID_BRANCH_ID_CLRMSK (IMG_UINT64_C(0X0000FFFFFFFFFFFF)) #define VHA_CR_CORE_ID_VERSION_ID_SHIFT (32U) #define VHA_CR_CORE_ID_VERSION_ID_CLRMSK (IMG_UINT64_C(0XFFFF0000FFFFFFFF)) #define VHA_CR_CORE_ID_NUMBER_OF_SCALABLE_UNITS_SHIFT (16U) #define VHA_CR_CORE_ID_NUMBER_OF_SCALABLE_UNITS_CLRMSK (IMG_UINT64_C(0XFFFFFFFF0000FFFF)) #define VHA_CR_CORE_ID_CONFIG_ID_SHIFT (0U) #define VHA_CR_CORE_ID_CONFIG_ID_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFF0000)) /* Register VHA_CR_CORE_IP_INTEGRATOR_ID */ #define VHA_CR_CORE_IP_INTEGRATOR_ID (0x0028U) #define VHA_CR_CORE_IP_INTEGRATOR_ID_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF)) #define VHA_CR_CORE_IP_INTEGRATOR_ID_VALUE_SHIFT (0U) #define VHA_CR_CORE_IP_INTEGRATOR_ID_VALUE_CLRMSK (IMG_UINT64_C(0XFFFFFFFF00000000)) /* Register VHA_CR_CORE_IP_CHANGELIST */ #define VHA_CR_CORE_IP_CHANGELIST (0x0030U) #define VHA_CR_CORE_IP_CHANGELIST_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF)) #define VHA_CR_CORE_IP_CHANGELIST_VALUE_SHIFT (0U) #define VHA_CR_CORE_IP_CHANGELIST_VALUE_CLRMSK (IMG_UINT64_C(0XFFFFFFFF00000000)) /* Register VHA_CR_CORE_IP_CONFIG */ #define VHA_CR_CORE_IP_CONFIG (0x0038U) #define VHA_CR_CORE_IP_CONFIG_MASKFULL (IMG_UINT64_C(0x0000000000000F03)) #define VHA_CR_CORE_IP_CONFIG_SIGNATURES_SUPPORTED_SUBSET_SHIFT (11U) #define VHA_CR_CORE_IP_CONFIG_SIGNATURES_SUPPORTED_SUBSET_CLRMSK (0XFFFFF7FFU) #define VHA_CR_CORE_IP_CONFIG_SIGNATURES_SUPPORTED_SUBSET_EN (0X00000800U) #define VHA_CR_CORE_IP_CONFIG_SIGNATURES_SUPPORTED_ALL_SHIFT (10U) #define VHA_CR_CORE_IP_CONFIG_SIGNATURES_SUPPORTED_ALL_CLRMSK (0XFFFFFBFFU) #define VHA_CR_CORE_IP_CONFIG_SIGNATURES_SUPPORTED_ALL_EN (0X00000400U) #define VHA_CR_CORE_IP_CONFIG_RANDOM_STALLERS_SUPPORTED_SHIFT (9U) #define VHA_CR_CORE_IP_CONFIG_RANDOM_STALLERS_SUPPORTED_CLRMSK (0XFFFFFDFFU) #define VHA_CR_CORE_IP_CONFIG_RANDOM_STALLERS_SUPPORTED_EN (0X00000200U) #define VHA_CR_CORE_IP_CONFIG_RTM_SUPPORTED_SHIFT (8U) #define VHA_CR_CORE_IP_CONFIG_RTM_SUPPORTED_CLRMSK (0XFFFFFEFFU) #define VHA_CR_CORE_IP_CONFIG_RTM_SUPPORTED_EN (0X00000100U) #define VHA_CR_CORE_IP_CONFIG_SCL_SUPPORTED_SHIFT (1U) #define VHA_CR_CORE_IP_CONFIG_SCL_SUPPORTED_CLRMSK (0XFFFFFFFDU) #define VHA_CR_CORE_IP_CONFIG_SCL_SUPPORTED_EN (0X00000002U) #define VHA_CR_CORE_IP_CONFIG_CNN_SUPPORTED_SHIFT (0U) #define VHA_CR_CORE_IP_CONFIG_CNN_SUPPORTED_CLRMSK (0XFFFFFFFEU) #define VHA_CR_CORE_IP_CONFIG_CNN_SUPPORTED_EN (0X00000001U) /* Register VHA_CR_VHA_AXI_RESET_CTRL */ #define VHA_CR_VHA_AXI_RESET_CTRL (0x0078U) #define VHA_CR_VHA_AXI_RESET_CTRL_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF)) #define VHA_CR_VHA_AXI_RESET_CTRL_SOFT_RESET_CYCLES_SHIFT (0U) #define VHA_CR_VHA_AXI_RESET_CTRL_SOFT_RESET_CYCLES_CLRMSK (00000000U) /* Register VHA_CR_RESET_CTRL */ #define VHA_CR_RESET_CTRL (0x0080U) #define VHA_CR_RESET_CTRL_MASKFULL (IMG_UINT64_C(0x00000000C0000107)) #define VHA_CR_RESET_CTRL_VHA_SYS_SOFT_RESET_SHIFT (31U) #define VHA_CR_RESET_CTRL_VHA_SYS_SOFT_RESET_CLRMSK (0X7FFFFFFFU) #define VHA_CR_RESET_CTRL_VHA_SYS_SOFT_RESET_EN (0X80000000U) #define VHA_CR_RESET_CTRL_VHA_AXI_SOFT_RESET_SHIFT (30U) #define VHA_CR_RESET_CTRL_VHA_AXI_SOFT_RESET_CLRMSK (0XBFFFFFFFU) #define VHA_CR_RESET_CTRL_VHA_AXI_SOFT_RESET_EN (0X40000000U) #define VHA_CR_RESET_CTRL_VHA_CNN0_SOFT_RESET_SHIFT (8U) #define VHA_CR_RESET_CTRL_VHA_CNN0_SOFT_RESET_CLRMSK (0XFFFFFEFFU) #define VHA_CR_RESET_CTRL_VHA_CNN0_SOFT_RESET_EN (0X00000100U) #define VHA_CR_RESET_CTRL_VHA_SLC_SOFT_RESET_SHIFT (2U) #define VHA_CR_RESET_CTRL_VHA_SLC_SOFT_RESET_CLRMSK (0XFFFFFFFBU) #define VHA_CR_RESET_CTRL_VHA_SLC_SOFT_RESET_EN (0X00000004U) #define VHA_CR_RESET_CTRL_VHA_BIF_SOFT_RESET_SHIFT (1U) #define VHA_CR_RESET_CTRL_VHA_BIF_SOFT_RESET_CLRMSK (0XFFFFFFFDU) #define VHA_CR_RESET_CTRL_VHA_BIF_SOFT_RESET_EN (0X00000002U) #define VHA_CR_RESET_CTRL_VHA_SOFT_RESET_SHIFT (0U) #define VHA_CR_RESET_CTRL_VHA_SOFT_RESET_CLRMSK (0XFFFFFFFEU) #define VHA_CR_RESET_CTRL_VHA_SOFT_RESET_EN (0X00000001U) #define VHA_CR_VHA_EVENT_TYPE_VHA_AXI_ERROR_SHIFT (18U) #define VHA_CR_VHA_EVENT_TYPE_VHA_AXI_ERROR_CLRMSK (0XFFFBFFFFU) #define VHA_CR_VHA_EVENT_TYPE_VHA_AXI_ERROR_EN (0X00040000U) #define VHA_CR_VHA_EVENT_TYPE_VHA_MMU_PAGE_FAULT_SHIFT (16U) #define VHA_CR_VHA_EVENT_TYPE_VHA_MMU_PAGE_FAULT_CLRMSK (0XFFFEFFFFU) #define VHA_CR_VHA_EVENT_TYPE_VHA_MMU_PAGE_FAULT_EN (0X00010000U) #define VHA_CR_VHA_EVENT_TYPE_VHA_CNN0_MEM_WDT_SHIFT (3U) #define VHA_CR_VHA_EVENT_TYPE_VHA_CNN0_MEM_WDT_CLRMSK (0XFFFFFFF7U) #define VHA_CR_VHA_EVENT_TYPE_VHA_CNN0_MEM_WDT_EN (0X00000008U) #define VHA_CR_VHA_EVENT_TYPE_VHA_CNN0_WDT_SHIFT (2U) #define VHA_CR_VHA_EVENT_TYPE_VHA_CNN0_WDT_CLRMSK (0XFFFFFFFBU) #define VHA_CR_VHA_EVENT_TYPE_VHA_CNN0_WDT_EN (0X00000004U) #define VHA_CR_VHA_EVENT_TYPE_VHA_CNN0_ERROR_SHIFT (1U) #define VHA_CR_VHA_EVENT_TYPE_VHA_CNN0_ERROR_CLRMSK (0XFFFFFFFDU) #define VHA_CR_VHA_EVENT_TYPE_VHA_CNN0_ERROR_EN (0X00000002U) #define VHA_CR_VHA_EVENT_TYPE_VHA_CNN0_COMPLETE_SHIFT (0U) #define VHA_CR_VHA_EVENT_TYPE_VHA_CNN0_COMPLETE_CLRMSK (0XFFFFFFFEU) #define VHA_CR_VHA_EVENT_TYPE_VHA_CNN0_COMPLETE_EN (0X00000001U) /* Register VHA_CR_OS0_VHA_EVENT_ENABLE */ #define VHA_CR_OS0_VHA_EVENT_ENABLE (0x0088U) #define VHA_CR_OS0_VHA_EVENT_ENABLE_MASKFULL (IMG_UINT64_C(0x000000000005000F)) #define VHA_CR_OS0_VHA_EVENT_ENABLE_VHA_AXI_ERROR_SHIFT (18U) #define VHA_CR_OS0_VHA_EVENT_ENABLE_VHA_AXI_ERROR_CLRMSK (0XFFFBFFFFU) #define VHA_CR_OS0_VHA_EVENT_ENABLE_VHA_AXI_ERROR_EN (0X00040000U) #define VHA_CR_OS0_VHA_EVENT_ENABLE_VHA_MMU_PAGE_FAULT_SHIFT (16U) #define VHA_CR_OS0_VHA_EVENT_ENABLE_VHA_MMU_PAGE_FAULT_CLRMSK (0XFFFEFFFFU) #define VHA_CR_OS0_VHA_EVENT_ENABLE_VHA_MMU_PAGE_FAULT_EN (0X00010000U) #define VHA_CR_OS0_VHA_EVENT_ENABLE_VHA_CNN0_MEM_WDT_SHIFT (3U) #define VHA_CR_OS0_VHA_EVENT_ENABLE_VHA_CNN0_MEM_WDT_CLRMSK (0XFFFFFFF7U) #define VHA_CR_OS0_VHA_EVENT_ENABLE_VHA_CNN0_MEM_WDT_EN (0X00000008U) #define VHA_CR_OS0_VHA_EVENT_ENABLE_VHA_CNN0_WDT_SHIFT (2U) #define VHA_CR_OS0_VHA_EVENT_ENABLE_VHA_CNN0_WDT_CLRMSK (0XFFFFFFFBU) #define VHA_CR_OS0_VHA_EVENT_ENABLE_VHA_CNN0_WDT_EN (0X00000004U) #define VHA_CR_OS0_VHA_EVENT_ENABLE_VHA_CNN0_ERROR_SHIFT (1U) #define VHA_CR_OS0_VHA_EVENT_ENABLE_VHA_CNN0_ERROR_CLRMSK (0XFFFFFFFDU) #define VHA_CR_OS0_VHA_EVENT_ENABLE_VHA_CNN0_ERROR_EN (0X00000002U) #define VHA_CR_OS0_VHA_EVENT_ENABLE_VHA_CNN0_COMPLETE_SHIFT (0U) #define VHA_CR_OS0_VHA_EVENT_ENABLE_VHA_CNN0_COMPLETE_CLRMSK (0XFFFFFFFEU) #define VHA_CR_OS0_VHA_EVENT_ENABLE_VHA_CNN0_COMPLETE_EN (0X00000001U) /* Register VHA_CR_OS0_VHA_EVENT_STATUS */ #define VHA_CR_OS0_VHA_EVENT_STATUS (0x0090U) #define VHA_CR_OS0_VHA_EVENT_STATUS_MASKFULL (IMG_UINT64_C(0x000000000005000F)) #define VHA_CR_OS0_VHA_EVENT_STATUS_VHA_AXI_ERROR_SHIFT (18U) #define VHA_CR_OS0_VHA_EVENT_STATUS_VHA_AXI_ERROR_CLRMSK (0XFFFBFFFFU) #define VHA_CR_OS0_VHA_EVENT_STATUS_VHA_AXI_ERROR_EN (0X00040000U) #define VHA_CR_OS0_VHA_EVENT_STATUS_VHA_MMU_PAGE_FAULT_SHIFT (16U) #define VHA_CR_OS0_VHA_EVENT_STATUS_VHA_MMU_PAGE_FAULT_CLRMSK (0XFFFEFFFFU) #define VHA_CR_OS0_VHA_EVENT_STATUS_VHA_MMU_PAGE_FAULT_EN (0X00010000U) #define VHA_CR_OS0_VHA_EVENT_STATUS_VHA_CNN0_MEM_WDT_SHIFT (3U) #define VHA_CR_OS0_VHA_EVENT_STATUS_VHA_CNN0_MEM_WDT_CLRMSK (0XFFFFFFF7U) #define VHA_CR_OS0_VHA_EVENT_STATUS_VHA_CNN0_MEM_WDT_EN (0X00000008U) #define VHA_CR_OS0_VHA_EVENT_STATUS_VHA_CNN0_WDT_SHIFT (2U) #define VHA_CR_OS0_VHA_EVENT_STATUS_VHA_CNN0_WDT_CLRMSK (0XFFFFFFFBU) #define VHA_CR_OS0_VHA_EVENT_STATUS_VHA_CNN0_WDT_EN (0X00000004U) #define VHA_CR_OS0_VHA_EVENT_STATUS_VHA_CNN0_ERROR_SHIFT (1U) #define VHA_CR_OS0_VHA_EVENT_STATUS_VHA_CNN0_ERROR_CLRMSK (0XFFFFFFFDU) #define VHA_CR_OS0_VHA_EVENT_STATUS_VHA_CNN0_ERROR_EN (0X00000002U) #define VHA_CR_OS0_VHA_EVENT_STATUS_VHA_CNN0_COMPLETE_SHIFT (0U) #define VHA_CR_OS0_VHA_EVENT_STATUS_VHA_CNN0_COMPLETE_CLRMSK (0XFFFFFFFEU) #define VHA_CR_OS0_VHA_EVENT_STATUS_VHA_CNN0_COMPLETE_EN (0X00000001U) /* Register VHA_CR_OS0_VHA_EVENT_CLEAR */ #define VHA_CR_OS0_VHA_EVENT_CLEAR (0x0098U) #define VHA_CR_OS0_VHA_EVENT_CLEAR_MASKFULL (IMG_UINT64_C(0x000000000005000F)) #define VHA_CR_OS0_VHA_EVENT_CLEAR_VHA_AXI_ERROR_SHIFT (18U) #define VHA_CR_OS0_VHA_EVENT_CLEAR_VHA_AXI_ERROR_CLRMSK (0XFFFBFFFFU) #define VHA_CR_OS0_VHA_EVENT_CLEAR_VHA_AXI_ERROR_EN (0X00040000U) #define VHA_CR_OS0_VHA_EVENT_CLEAR_VHA_MMU_PAGE_FAULT_SHIFT (16U) #define VHA_CR_OS0_VHA_EVENT_CLEAR_VHA_MMU_PAGE_FAULT_CLRMSK (0XFFFEFFFFU) #define VHA_CR_OS0_VHA_EVENT_CLEAR_VHA_MMU_PAGE_FAULT_EN (0X00010000U) #define VHA_CR_OS0_VHA_EVENT_CLEAR_VHA_CNN0_MEM_WDT_SHIFT (3U) #define VHA_CR_OS0_VHA_EVENT_CLEAR_VHA_CNN0_MEM_WDT_CLRMSK (0XFFFFFFF7U) #define VHA_CR_OS0_VHA_EVENT_CLEAR_VHA_CNN0_MEM_WDT_EN (0X00000008U) #define VHA_CR_OS0_VHA_EVENT_CLEAR_VHA_CNN0_WDT_SHIFT (2U) #define VHA_CR_OS0_VHA_EVENT_CLEAR_VHA_CNN0_WDT_CLRMSK (0XFFFFFFFBU) #define VHA_CR_OS0_VHA_EVENT_CLEAR_VHA_CNN0_WDT_EN (0X00000004U) #define VHA_CR_OS0_VHA_EVENT_CLEAR_VHA_CNN0_ERROR_SHIFT (1U) #define VHA_CR_OS0_VHA_EVENT_CLEAR_VHA_CNN0_ERROR_CLRMSK (0XFFFFFFFDU) #define VHA_CR_OS0_VHA_EVENT_CLEAR_VHA_CNN0_ERROR_EN (0X00000002U) #define VHA_CR_OS0_VHA_EVENT_CLEAR_VHA_CNN0_COMPLETE_SHIFT (0U) #define VHA_CR_OS0_VHA_EVENT_CLEAR_VHA_CNN0_COMPLETE_CLRMSK (0XFFFFFFFEU) #define VHA_CR_OS0_VHA_EVENT_CLEAR_VHA_CNN0_COMPLETE_EN (0X00000001U) #define VHA_CR_SYS_CLK_CTRL0_MODE_MASK (0x00000003U) /* The domain clock is forced off */ #define VHA_CR_SYS_CLK_CTRL0_MODE_OFF (0x00000000U) /* The domain clock is forced on */ #define VHA_CR_SYS_CLK_CTRL0_MODE_ON (0x00000001U) /* Automatic clock gating is active, the domain clock is only on whilst data is being processed */ #define VHA_CR_SYS_CLK_CTRL0_MODE_AUTO (0x00000002U) /* Register VHA_CR_SYS_CLK_CTRL0 */ #define VHA_CR_SYS_CLK_CTRL0 (0x2000U) #define VHA_CR_SYS_CLK_CTRL0_MASKFULL (IMG_UINT64_C(0x0000000000000030)) #define VHA_CR_SYS_CLK_CTRL0_SLC_SHIFT (4U) #define VHA_CR_SYS_CLK_CTRL0_SLC_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFCF)) #define VHA_CR_SYS_CLK_CTRL0_SLC_OFF (IMG_UINT64_C(0000000000000000)) #define VHA_CR_SYS_CLK_CTRL0_SLC_ON (IMG_UINT64_C(0x0000000000000010)) #define VHA_CR_SYS_CLK_CTRL0_SLC_AUTO (IMG_UINT64_C(0x0000000000000020)) /* Clock is gated and the module is inactive */ #define VHA_CR_SYS_CLK_STATUS0_MODE_GATED (0x00000000U) /* Clock is running */ #define VHA_CR_SYS_CLK_STATUS0_MODE_RUNNING (0x00000001U) /* Register VHA_CR_SYS_CLK_STATUS0 */ #define VHA_CR_SYS_CLK_STATUS0 (0x2008U) #define VHA_CR_SYS_CLK_STATUS0_MASKFULL (IMG_UINT64_C(0x0000000000000004)) #define VHA_CR_SYS_CLK_STATUS0_SLC_SHIFT (2U) #define VHA_CR_SYS_CLK_STATUS0_SLC_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFB)) #define VHA_CR_SYS_CLK_STATUS0_SLC_GATED (IMG_UINT64_C(0000000000000000)) #define VHA_CR_SYS_CLK_STATUS0_SLC_RUNNING (IMG_UINT64_C(0x0000000000000004)) /* Register VHA_CR_AXI_EXACCESS */ #define VHA_CR_AXI_EXACCESS (0x2168U) #define VHA_CR_AXI_EXACCESS_MASKFULL (IMG_UINT64_C(0x0000000000000001)) #define VHA_CR_AXI_EXACCESS_SOCIF_ENABLE_SHIFT (0U) #define VHA_CR_AXI_EXACCESS_SOCIF_ENABLE_CLRMSK (0XFFFFFFFEU) #define VHA_CR_AXI_EXACCESS_SOCIF_ENABLE_EN (0X00000001U) /* Register VHA_CR_MMU_HOST_IRQ_ENABLE */ #define VHA_CR_MMU_HOST_IRQ_ENABLE (0xE1A0U) #define VHA_CR_MMU_HOST_IRQ_ENABLE_MASKFULL (IMG_UINT64_C(0x0000000000000001)) #define VHA_CR_MMU_HOST_IRQ_ENABLE_FAULT_PM_SHIFT (0U) #define VHA_CR_MMU_HOST_IRQ_ENABLE_FAULT_PM_CLRMSK (0XFFFFFFFEU) #define VHA_CR_MMU_HOST_IRQ_ENABLE_FAULT_PM_EN (0X00000001U) /* Register VHA_CR_OS0_CNN_CONTROL */ #define VHA_CR_OS0_CNN_CONTROL (0x0100U) #define VHA_CR_OS0_CNN_CONTROL_MASKFULL (IMG_UINT64_C(0x000000000000007F)) #define VHA_CR_OS0_CNN_CONTROL_CMD_SIZE_MIN1_SHIFT (1U) #define VHA_CR_OS0_CNN_CONTROL_CMD_SIZE_MIN1_CLRMSK (0XFFFFFF81U) #define VHA_CR_OS0_CNN_CONTROL_START_SHIFT (0U) #define VHA_CR_OS0_CNN_CONTROL_START_CLRMSK (0XFFFFFFFEU) #define VHA_CR_OS0_CNN_CONTROL_START_EN (0X00000001U) /* Register VHA_CR_OS0_CNN_STATUS */ #define VHA_CR_OS0_CNN_STATUS (0x0108U) #define VHA_CR_OS0_CNN_STATUS_MASKFULL (IMG_UINT64_C(0x0000000000FFFFFF)) #define VHA_CR_OS0_CNN_STATUS_PASS_COUNT_SHIFT (16U) #define VHA_CR_OS0_CNN_STATUS_PASS_COUNT_CLRMSK (0XFF00FFFFU) #define VHA_CR_OS0_CNN_STATUS_LAYER_COUNT_SHIFT (8U) #define VHA_CR_OS0_CNN_STATUS_LAYER_COUNT_CLRMSK (0XFFFF00FFU) #define VHA_CR_OS0_CNN_STATUS_STREAM_COUNT_SHIFT (0U) #define VHA_CR_OS0_CNN_STATUS_STREAM_COUNT_CLRMSK (0XFFFFFF00U) /* Register VHA_CR_OS0_CNN_CMD_BASE_ADDRESS */ #define VHA_CR_OS0_CNN_CMD_BASE_ADDRESS (0x0120U) #define VHA_CR_OS0_CNN_CMD_BASE_ADDRESS_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFF00)) #define VHA_CR_OS0_CNN_CMD_BASE_ADDRESS_BASE_ADDR_SHIFT (8U) #define VHA_CR_OS0_CNN_CMD_BASE_ADDRESS_BASE_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF00000000FF)) /* Register VHA_CR_OS0_CNN_ALT_ADDRESS_USED */ #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED (0x0138U) #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_MASKFULL (IMG_UINT64_C(0x00000000000000FF)) #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR7_USED_SHIFT (7U) #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR7_USED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFF7F)) #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR7_USED_EN (IMG_UINT64_C(0X0000000000000080)) #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR6_USED_SHIFT (6U) #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR6_USED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFBF)) #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR6_USED_EN (IMG_UINT64_C(0X0000000000000040)) #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR5_USED_SHIFT (5U) #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR5_USED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFDF)) #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR5_USED_EN (IMG_UINT64_C(0X0000000000000020)) #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR4_USED_SHIFT (4U) #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR4_USED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFEF)) #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR4_USED_EN (IMG_UINT64_C(0X0000000000000010)) #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR3_USED_SHIFT (3U) #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR3_USED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFF7)) #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR3_USED_EN (IMG_UINT64_C(0X0000000000000008)) #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR2_USED_SHIFT (2U) #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR2_USED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFB)) #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR2_USED_EN (IMG_UINT64_C(0X0000000000000004)) #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR1_USED_SHIFT (1U) #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR1_USED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFD)) #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR1_USED_EN (IMG_UINT64_C(0X0000000000000002)) #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR0_USED_SHIFT (0U) #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR0_USED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFE)) #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR0_USED_EN (IMG_UINT64_C(0X0000000000000001)) /* Register VHA_CR_OS0_CNN_ALT_ADDRESS0 */ #define VHA_CR_OS0_CNN_ALT_ADDRESS0 (0x0140U) #define VHA_CR_OS0_CNN_ALT_ADDRESS0_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFF00)) #define VHA_CR_OS0_CNN_ALT_ADDRESS0_ALT_ADDR_SHIFT (8U) #define VHA_CR_OS0_CNN_ALT_ADDRESS0_ALT_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF00000000FF)) /* Register VHA_CR_OS0_CNN_ALT_ADDRESS1 */ #define VHA_CR_OS0_CNN_ALT_ADDRESS1 (0x0148U) #define VHA_CR_OS0_CNN_ALT_ADDRESS1_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFF00)) #define VHA_CR_OS0_CNN_ALT_ADDRESS1_ALT_ADDR_SHIFT (8U) #define VHA_CR_OS0_CNN_ALT_ADDRESS1_ALT_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF00000000FF)) /* Register VHA_CR_OS0_CNN_ALT_ADDRESS2 */ #define VHA_CR_OS0_CNN_ALT_ADDRESS2 (0x0150U) #define VHA_CR_OS0_CNN_ALT_ADDRESS2_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFF00)) #define VHA_CR_OS0_CNN_ALT_ADDRESS2_ALT_ADDR_SHIFT (8U) #define VHA_CR_OS0_CNN_ALT_ADDRESS2_ALT_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF00000000FF)) /* Register VHA_CR_OS0_CNN_ALT_ADDRESS3 */ #define VHA_CR_OS0_CNN_ALT_ADDRESS3 (0x0158U) #define VHA_CR_OS0_CNN_ALT_ADDRESS3_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFF00)) #define VHA_CR_OS0_CNN_ALT_ADDRESS3_ALT_ADDR_SHIFT (8U) #define VHA_CR_OS0_CNN_ALT_ADDRESS3_ALT_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF00000000FF)) /* Register VHA_CR_OS0_CNN_ALT_ADDRESS4 */ #define VHA_CR_OS0_CNN_ALT_ADDRESS4 (0x0160U) #define VHA_CR_OS0_CNN_ALT_ADDRESS4_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFF00)) #define VHA_CR_OS0_CNN_ALT_ADDRESS4_ALT_ADDR_SHIFT (8U) #define VHA_CR_OS0_CNN_ALT_ADDRESS4_ALT_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF00000000FF)) /* Register VHA_CR_OS0_CNN_ALT_ADDRESS5 */ #define VHA_CR_OS0_CNN_ALT_ADDRESS5 (0x0168U) #define VHA_CR_OS0_CNN_ALT_ADDRESS5_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFF00)) #define VHA_CR_OS0_CNN_ALT_ADDRESS5_ALT_ADDR_SHIFT (8U) #define VHA_CR_OS0_CNN_ALT_ADDRESS5_ALT_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF00000000FF)) /* Register VHA_CR_OS0_CNN_ALT_ADDRESS6 */ #define VHA_CR_OS0_CNN_ALT_ADDRESS6 (0x0170U) #define VHA_CR_OS0_CNN_ALT_ADDRESS6_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFF00)) #define VHA_CR_OS0_CNN_ALT_ADDRESS6_ALT_ADDR_SHIFT (8U) #define VHA_CR_OS0_CNN_ALT_ADDRESS6_ALT_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF00000000FF)) /* Register VHA_CR_OS0_CNN_ALT_ADDRESS7 */ #define VHA_CR_OS0_CNN_ALT_ADDRESS7 (0x0178U) #define VHA_CR_OS0_CNN_ALT_ADDRESS7_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFF00)) #define VHA_CR_OS0_CNN_ALT_ADDRESS7_ALT_ADDR_SHIFT (8U) #define VHA_CR_OS0_CNN_ALT_ADDRESS7_ALT_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF00000000FF)) /* Register VHA_CR_OS0_CNN_WRITEBACK_CONTROL */ #define VHA_CR_OS0_CNN_WRITEBACK_CONTROL (0x0180U) #define VHA_CR_OS0_CNN_WRITEBACK_CONTROL_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF)) #define VHA_CR_OS0_CNN_WRITEBACK_CONTROL_WRITE_BACK_VALUE_SHIFT (0U) #define VHA_CR_OS0_CNN_WRITEBACK_CONTROL_WRITE_BACK_VALUE_CLRMSK (00000000U) /* Register VHA_CR_CNN_CMD_MH_CONTROL */ #define VHA_CR_CNN_CMD_MH_CONTROL (0x0200U) #define VHA_CR_CNN_CMD_MH_CONTROL_MASKFULL (IMG_UINT64_C(0x0000000000001F3F)) #define VHA_CR_CNN_CMD_MH_CONTROL_CTXT_PASID_SHIFT (8U) #define VHA_CR_CNN_CMD_MH_CONTROL_CTXT_PASID_CLRMSK (0XFFFFE0FFU) #define VHA_CR_CNN_CMD_MH_CONTROL_MAX_BURST_LENGTH_SHIFT (4U) #define VHA_CR_CNN_CMD_MH_CONTROL_MAX_BURST_LENGTH_CLRMSK (0XFFFFFFCFU) #define VHA_CR_CNN_CMD_MH_CONTROL_GPU_PIPE_COHERENT_SHIFT (3U) #define VHA_CR_CNN_CMD_MH_CONTROL_GPU_PIPE_COHERENT_CLRMSK (0XFFFFFFF7U) #define VHA_CR_CNN_CMD_MH_CONTROL_GPU_PIPE_COHERENT_EN (0X00000008U) #define VHA_CR_CNN_CMD_MH_CONTROL_SLC_CACHE_POLICY_SHIFT (2U) #define VHA_CR_CNN_CMD_MH_CONTROL_SLC_CACHE_POLICY_CLRMSK (0XFFFFFFFBU) #define VHA_CR_CNN_CMD_MH_CONTROL_SLC_CACHE_POLICY_EN (0X00000004U) #define VHA_CR_CNN_CMD_MH_CONTROL_PERSISTENCE_SHIFT (0U) #define VHA_CR_CNN_CMD_MH_CONTROL_PERSISTENCE_CLRMSK (0XFFFFFFFCU) /* Register VHA_CR_CNN_IBUF_MH_CONTROL */ #define VHA_CR_CNN_IBUF_MH_CONTROL (0x0208U) #define VHA_CR_CNN_IBUF_MH_CONTROL_MASKFULL (IMG_UINT64_C(0x000000000000001F)) #define VHA_CR_CNN_IBUF_MH_CONTROL_MAX_BURST_LENGTH_SHIFT (3U) #define VHA_CR_CNN_IBUF_MH_CONTROL_MAX_BURST_LENGTH_CLRMSK (0XFFFFFFE7U) #define VHA_CR_CNN_IBUF_MH_CONTROL_GPU_PIPE_COHERENT_SHIFT (2U) #define VHA_CR_CNN_IBUF_MH_CONTROL_GPU_PIPE_COHERENT_CLRMSK (0XFFFFFFFBU) #define VHA_CR_CNN_IBUF_MH_CONTROL_GPU_PIPE_COHERENT_EN (0X00000004U) #define VHA_CR_CNN_IBUF_MH_CONTROL_PERSISTENCE_SHIFT (0U) #define VHA_CR_CNN_IBUF_MH_CONTROL_PERSISTENCE_CLRMSK (0XFFFFFFFCU) /* Register VHA_CR_CNN_CBUF_MH_CONTROL */ #define VHA_CR_CNN_CBUF_MH_CONTROL (0x0210U) #define VHA_CR_CNN_CBUF_MH_CONTROL_MASKFULL (IMG_UINT64_C(0x000000000000001F)) #define VHA_CR_CNN_CBUF_MH_CONTROL_MAX_BURST_LENGTH_SHIFT (3U) #define VHA_CR_CNN_CBUF_MH_CONTROL_MAX_BURST_LENGTH_CLRMSK (0XFFFFFFE7U) #define VHA_CR_CNN_CBUF_MH_CONTROL_GPU_PIPE_COHERENT_SHIFT (2U) #define VHA_CR_CNN_CBUF_MH_CONTROL_GPU_PIPE_COHERENT_CLRMSK (0XFFFFFFFBU) #define VHA_CR_CNN_CBUF_MH_CONTROL_GPU_PIPE_COHERENT_EN (0X00000004U) #define VHA_CR_CNN_CBUF_MH_CONTROL_PERSISTENCE_SHIFT (0U) #define VHA_CR_CNN_CBUF_MH_CONTROL_PERSISTENCE_CLRMSK (0XFFFFFFFCU) /* Register VHA_CR_CNN_ABUF_MH_CONTROL */ #define VHA_CR_CNN_ABUF_MH_CONTROL (0x0218U) #define VHA_CR_CNN_ABUF_MH_CONTROL_MASKFULL (IMG_UINT64_C(0x000000000000001F)) #define VHA_CR_CNN_ABUF_MH_CONTROL_MAX_BURST_LENGTH_SHIFT (3U) #define VHA_CR_CNN_ABUF_MH_CONTROL_MAX_BURST_LENGTH_CLRMSK (0XFFFFFFE7U) #define VHA_CR_CNN_ABUF_MH_CONTROL_GPU_PIPE_COHERENT_SHIFT (2U) #define VHA_CR_CNN_ABUF_MH_CONTROL_GPU_PIPE_COHERENT_CLRMSK (0XFFFFFFFBU) #define VHA_CR_CNN_ABUF_MH_CONTROL_GPU_PIPE_COHERENT_EN (0X00000004U) #define VHA_CR_CNN_ABUF_MH_CONTROL_PERSISTENCE_SHIFT (0U) #define VHA_CR_CNN_ABUF_MH_CONTROL_PERSISTENCE_CLRMSK (0XFFFFFFFCU) /* Register VHA_CR_CNN_OUTPACK_MH_CONTROL */ #define VHA_CR_CNN_OUTPACK_MH_CONTROL (0x0220U) #define VHA_CR_CNN_OUTPACK_MH_CONTROL_MASKFULL (IMG_UINT64_C(0x000000000000001F)) #define VHA_CR_CNN_OUTPACK_MH_CONTROL_MAX_BURST_LENGTH_SHIFT (3U) #define VHA_CR_CNN_OUTPACK_MH_CONTROL_MAX_BURST_LENGTH_CLRMSK (0XFFFFFFE7U) #define VHA_CR_CNN_OUTPACK_MH_CONTROL_GPU_PIPE_COHERENT_SHIFT (2U) #define VHA_CR_CNN_OUTPACK_MH_CONTROL_GPU_PIPE_COHERENT_CLRMSK (0XFFFFFFFBU) #define VHA_CR_CNN_OUTPACK_MH_CONTROL_GPU_PIPE_COHERENT_EN (0X00000004U) #define VHA_CR_CNN_OUTPACK_MH_CONTROL_PERSISTENCE_SHIFT (0U) #define VHA_CR_CNN_OUTPACK_MH_CONTROL_PERSISTENCE_CLRMSK (0XFFFFFFFCU) /* Register VHA_CR_CNN_ELEMENTOPS_MH_CONTROL */ #define VHA_CR_CNN_ELEMENTOPS_MH_CONTROL (0x0228U) #define VHA_CR_CNN_ELEMENTOPS_MH_CONTROL_MASKFULL (IMG_UINT64_C(0x000000000000001F)) #define VHA_CR_CNN_ELEMENTOPS_MH_CONTROL_MAX_BURST_LENGTH_SHIFT (3U) #define VHA_CR_CNN_ELEMENTOPS_MH_CONTROL_MAX_BURST_LENGTH_CLRMSK (0XFFFFFFE7U) #define VHA_CR_CNN_ELEMENTOPS_MH_CONTROL_GPU_PIPE_COHERENT_SHIFT (2U) #define VHA_CR_CNN_ELEMENTOPS_MH_CONTROL_GPU_PIPE_COHERENT_CLRMSK (0XFFFFFFFBU) #define VHA_CR_CNN_ELEMENTOPS_MH_CONTROL_GPU_PIPE_COHERENT_EN (0X00000004U) #define VHA_CR_CNN_ELEMENTOPS_MH_CONTROL_PERSISTENCE_SHIFT (0U) #define VHA_CR_CNN_ELEMENTOPS_MH_CONTROL_PERSISTENCE_CLRMSK (0XFFFFFFFCU) #define VHA_CR_CNN_DEBUG_CTRL_MASK (0x00000003U) /* Debug is switched off */ #define VHA_CR_CNN_DEBUG_CTRL_DISABLE (0x00000000U) /* Debug is output at the end of each stream */ #define VHA_CR_CNN_DEBUG_CTRL_STREAM (0x00000001U) /* Debug is output at the end of each layer */ #define VHA_CR_CNN_DEBUG_CTRL_LAYER (0x00000002U) /* Debug is output at the end of each pass */ #define VHA_CR_CNN_DEBUG_CTRL_PASS (0x00000003U) /* Register VHA_CR_OS0_CNN_CRC_CONTROL */ #define VHA_CR_OS0_CNN_CRC_CONTROL (0x0300U) #define VHA_CR_OS0_CNN_CRC_CONTROL_MASKFULL (IMG_UINT64_C(0x0000000000000003)) #define VHA_CR_OS0_CNN_CRC_CONTROL_CNN_CRC_ENABLE_SHIFT (0U) #define VHA_CR_OS0_CNN_CRC_CONTROL_CNN_CRC_ENABLE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFC)) #define VHA_CR_OS0_CNN_CRC_CONTROL_CNN_CRC_ENABLE_DISABLE (IMG_UINT64_C(0000000000000000)) #define VHA_CR_OS0_CNN_CRC_CONTROL_CNN_CRC_ENABLE_STREAM (IMG_UINT64_C(0x0000000000000001)) #define VHA_CR_OS0_CNN_CRC_CONTROL_CNN_CRC_ENABLE_LAYER (IMG_UINT64_C(0x0000000000000002)) #define VHA_CR_OS0_CNN_CRC_CONTROL_CNN_CRC_ENABLE_PASS (IMG_UINT64_C(0x0000000000000003)) /* Register VHA_CR_OS0_CNN_CRC_ADDRESS */ #define VHA_CR_OS0_CNN_CRC_ADDRESS (0x0308U) #define VHA_CR_OS0_CNN_CRC_ADDRESS_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFF00)) #define VHA_CR_OS0_CNN_CRC_ADDRESS_CNN_CRC_ADDR_SHIFT (8U) #define VHA_CR_OS0_CNN_CRC_ADDRESS_CNN_CRC_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF00000000FF)) #define VHA_CR_OS0_CNN_CRC_ADDRESS_CNN_CRC_ADDR_ALIGNSHIFT (8U) #define VHA_CR_OS0_CNN_CRC_ADDRESS_CNN_CRC_ADDR_ALIGNSIZE (256U) /* Register VHA_CR_OS0_CNN_DEBUG_ADDRESS */ #define VHA_CR_OS0_CNN_DEBUG_ADDRESS (0x0310U) #define VHA_CR_OS0_CNN_DEBUG_ADDRESS_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFF00)) #define VHA_CR_OS0_CNN_DEBUG_ADDRESS_CNN_DEBUG_ADDR_SHIFT (8U) #define VHA_CR_OS0_CNN_DEBUG_ADDRESS_CNN_DEBUG_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF00000000FF)) #define VHA_CR_OS0_CNN_DEBUG_ADDRESS_CNN_DEBUG_ADDR_ALIGNSHIFT (8U) #define VHA_CR_OS0_CNN_DEBUG_ADDRESS_CNN_DEBUG_ADDR_ALIGNSIZE (256U) /* Register VHA_CR_OS0_CNN_DEBUG_SIZE */ #define VHA_CR_OS0_CNN_DEBUG_SIZE (0x0318U) #define VHA_CR_OS0_CNN_DEBUG_SIZE_MASKFULL (IMG_UINT64_C(0x0000000000FFFF00)) #define VHA_CR_OS0_CNN_DEBUG_SIZE_CNN_DEBUG_SIZE_SHIFT (8U) #define VHA_CR_OS0_CNN_DEBUG_SIZE_CNN_DEBUG_SIZE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFF0000FF)) #define VHA_CR_OS0_CNN_DEBUG_SIZE_CNN_DEBUG_SIZE_ALIGNSHIFT (8U) #define VHA_CR_OS0_CNN_DEBUG_SIZE_CNN_DEBUG_SIZE_ALIGNSIZE (256U) /* Register VHA_CR_OS0_CNN_DEBUG_CONTROL */ #define VHA_CR_OS0_CNN_DEBUG_CONTROL (0x0320U) #define VHA_CR_OS0_CNN_DEBUG_CONTROL_MASKFULL (IMG_UINT64_C(0x000000000000000F)) #define VHA_CR_OS0_CNN_DEBUG_CONTROL_CNN_PERF_ENABLE_SHIFT (2U) #define VHA_CR_OS0_CNN_DEBUG_CONTROL_CNN_PERF_ENABLE_CLRMSK (0XFFFFFFF3U) #define VHA_CR_OS0_CNN_DEBUG_CONTROL_CNN_PERF_ENABLE_DISABLE (00000000U) #define VHA_CR_OS0_CNN_DEBUG_CONTROL_CNN_PERF_ENABLE_STREAM (0X00000004U) #define VHA_CR_OS0_CNN_DEBUG_CONTROL_CNN_PERF_ENABLE_LAYER (0X00000008U) #define VHA_CR_OS0_CNN_DEBUG_CONTROL_CNN_PERF_ENABLE_PASS (0X0000000CU) #define VHA_CR_OS0_CNN_DEBUG_CONTROL_CNN_BAND_ENABLE_SHIFT (0U) #define VHA_CR_OS0_CNN_DEBUG_CONTROL_CNN_BAND_ENABLE_CLRMSK (0XFFFFFFFCU) #define VHA_CR_OS0_CNN_DEBUG_CONTROL_CNN_BAND_ENABLE_DISABLE (00000000U) #define VHA_CR_OS0_CNN_DEBUG_CONTROL_CNN_BAND_ENABLE_STREAM (0X00000001U) #define VHA_CR_OS0_CNN_DEBUG_CONTROL_CNN_BAND_ENABLE_LAYER (0X00000002U) #define VHA_CR_OS0_CNN_DEBUG_CONTROL_CNN_BAND_ENABLE_PASS (0X00000003U) /* Register VHA_CR_OS0_CNN_DEBUG_STATUS */ #define VHA_CR_OS0_CNN_DEBUG_STATUS (0x0328U) #define VHA_CR_OS0_CNN_DEBUG_STATUS_MASKFULL (IMG_UINT64_C(0x000000000000FFFF)) #define VHA_CR_OS0_CNN_DEBUG_STATUS_CNN_DEBUG_OFFSET_SHIFT (0U) #define VHA_CR_OS0_CNN_DEBUG_STATUS_CNN_DEBUG_OFFSET_CLRMSK (0XFFFF0000U) /* Register VHA_CR_CNN_WDT_COMPAREMATCH */ #define VHA_CR_CNN_WDT_COMPAREMATCH (0x0330U) #define VHA_CR_CNN_WDT_COMPAREMATCH_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF)) #define VHA_CR_CNN_WDT_COMPAREMATCH_REG_SHIFT (0U) #define VHA_CR_CNN_WDT_COMPAREMATCH_REG_CLRMSK (00000000U) /* Register VHA_CR_CNN_WDT_TIMER */ #define VHA_CR_CNN_WDT_TIMER (0x0338U) #define VHA_CR_CNN_WDT_TIMER_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF)) #define VHA_CR_CNN_WDT_TIMER_VALUE_SHIFT (0U) #define VHA_CR_CNN_WDT_TIMER_VALUE_CLRMSK (00000000U) #define VHA_CR_CNN_WDT_CTRL_CNN_WDT_CTRL_MASK (0x00000003U) /* WDT is Disabled */ #define VHA_CR_CNN_WDT_CTRL_CNN_WDT_CTRL_NONE (0x00000000U) /* WDT is Cleared when CMD Parser starts a pass or CMD parser is kicked*/ #define VHA_CR_CNN_WDT_CTRL_CNN_WDT_CTRL_KICK_PASS (0x00000001U) /* WDT is Cleared when CMD Parser is kicked */ #define VHA_CR_CNN_WDT_CTRL_CNN_WDT_CTRL_KICK (0x00000002U) /* Register VHA_CR_CNN_WDT_CTRL */ #define VHA_CR_CNN_WDT_CTRL (0x0340U) #define VHA_CR_CNN_WDT_CTRL_MASKFULL (IMG_UINT64_C(0x0000000000000003)) #define VHA_CR_CNN_WDT_CTRL_MODE_SHIFT (0U) #define VHA_CR_CNN_WDT_CTRL_MODE_CLRMSK (0XFFFFFFFCU) #define VHA_CR_CNN_WDT_CTRL_MODE_NONE (00000000U) #define VHA_CR_CNN_WDT_CTRL_MODE_KICK_PASS (0X00000001U) #define VHA_CR_CNN_WDT_CTRL_MODE_KICK (0X00000002U) /* Register VHA_CR_CNN_MEM_WDT_COMPAREMATCH */ #define VHA_CR_CNN_MEM_WDT_COMPAREMATCH (0x0348U) #define VHA_CR_CNN_MEM_WDT_COMPAREMATCH_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF)) #define VHA_CR_CNN_MEM_WDT_COMPAREMATCH_REG_SHIFT (0U) #define VHA_CR_CNN_MEM_WDT_COMPAREMATCH_REG_CLRMSK (00000000U) /* Register VHA_CR_CNN_ARB_STALL_RATIO */ #define VHA_CR_CNN_ARB_STALL_RATIO (0x0350U) #define VHA_CR_CNN_ARB_STALL_RATIO_MASKFULL (IMG_UINT64_C(0x000000000FFFFFFF)) #define VHA_CR_CNN_ARB_STALL_RATIO_OUTPUT_SHIFT (24U) #define VHA_CR_CNN_ARB_STALL_RATIO_OUTPUT_CLRMSK (0XF0FFFFFFU) #define VHA_CR_CNN_ARB_STALL_RATIO_REQUESTER_6_SHIFT (20U) #define VHA_CR_CNN_ARB_STALL_RATIO_REQUESTER_6_CLRMSK (0XFF0FFFFFU) #define VHA_CR_CNN_ARB_STALL_RATIO_REQUESTER_5_SHIFT (16U) #define VHA_CR_CNN_ARB_STALL_RATIO_REQUESTER_5_CLRMSK (0XFFF0FFFFU) #define VHA_CR_CNN_ARB_STALL_RATIO_REQUESTER_4_SHIFT (12U) #define VHA_CR_CNN_ARB_STALL_RATIO_REQUESTER_4_CLRMSK (0XFFFF0FFFU) #define VHA_CR_CNN_ARB_STALL_RATIO_REQUESTER_3_SHIFT (8U) #define VHA_CR_CNN_ARB_STALL_RATIO_REQUESTER_3_CLRMSK (0XFFFFF0FFU) #define VHA_CR_CNN_ARB_STALL_RATIO_REQUESTER_2_SHIFT (4U) #define VHA_CR_CNN_ARB_STALL_RATIO_REQUESTER_2_CLRMSK (0XFFFFFF0FU) #define VHA_CR_CNN_ARB_STALL_RATIO_REQUESTER_1_SHIFT (0U) #define VHA_CR_CNN_ARB_STALL_RATIO_REQUESTER_1_CLRMSK (0XFFFFFFF0U) /* Register VHA_CR_CNN_MEM_WDT_TIMER */ #define VHA_CR_CNN_MEM_WDT_TIMER (0x0358U) #define VHA_CR_CNN_MEM_WDT_TIMER_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF)) #define VHA_CR_CNN_MEM_WDT_TIMER_VALUE_SHIFT (0U) #define VHA_CR_CNN_MEM_WDT_TIMER_VALUE_CLRMSK (00000000U) #define VHA_CR_CNN_MEM_WDT_CTRL_CNN_MEM_WDT_CTRL_MASK (0x00000003U) /* WDT is Disabled */ #define VHA_CR_CNN_MEM_WDT_CTRL_CNN_MEM_WDT_CTRL_NONE (0x00000000U) /* WDT is Cleared when CMD Parser starts a pass or CMD parser is kicked*/ #define VHA_CR_CNN_MEM_WDT_CTRL_CNN_MEM_WDT_CTRL_KICK_PASS (0x00000001U) /* WDT is Cleared when CMD Parser is kicked */ #define VHA_CR_CNN_MEM_WDT_CTRL_CNN_MEM_WDT_CTRL_KICK (0x00000002U) /* Register VHA_CR_CNN_MEM_WDT_CTRL */ #define VHA_CR_CNN_MEM_WDT_CTRL (0x0360U) #define VHA_CR_CNN_MEM_WDT_CTRL_MASKFULL (IMG_UINT64_C(0x0000000000000003)) #define VHA_CR_CNN_MEM_WDT_CTRL_MODE_SHIFT (0U) #define VHA_CR_CNN_MEM_WDT_CTRL_MODE_CLRMSK (0XFFFFFFFCU) #define VHA_CR_CNN_MEM_WDT_CTRL_MODE_NONE (00000000U) #define VHA_CR_CNN_MEM_WDT_CTRL_MODE_KICK_PASS (0X00000001U) #define VHA_CR_CNN_MEM_WDT_CTRL_MODE_KICK (0X00000002U) /* Register VHA_CR_CNN_DATAPATH_STALL_RATIO_FE */ #define VHA_CR_CNN_DATAPATH_STALL_RATIO_FE (0x0368U) #define VHA_CR_CNN_DATAPATH_STALL_RATIO_FE_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF)) #define VHA_CR_CNN_DATAPATH_STALL_RATIO_FE_CNV_ABUF_SHIFT (28U) #define VHA_CR_CNN_DATAPATH_STALL_RATIO_FE_CNV_ABUF_CLRMSK (0X0FFFFFFFU) #define VHA_CR_CNN_DATAPATH_STALL_RATIO_FE_IBUF_CNV_SHIFT (24U) #define VHA_CR_CNN_DATAPATH_STALL_RATIO_FE_IBUF_CNV_CLRMSK (0XF0FFFFFFU) #define VHA_CR_CNN_DATAPATH_STALL_RATIO_FE_ABUF_ACT_SHIFT (20U) #define VHA_CR_CNN_DATAPATH_STALL_RATIO_FE_ABUF_ACT_CLRMSK (0XFF0FFFFFU) #define VHA_CR_CNN_DATAPATH_STALL_RATIO_FE_ACT_NORM_SHIFT (16U) #define VHA_CR_CNN_DATAPATH_STALL_RATIO_FE_ACT_NORM_CLRMSK (0XFFF0FFFFU) #define VHA_CR_CNN_DATAPATH_STALL_RATIO_FE_IBUF_NORM_SHIFT (12U) #define VHA_CR_CNN_DATAPATH_STALL_RATIO_FE_IBUF_NORM_CLRMSK (0XFFFF0FFFU) #define VHA_CR_CNN_DATAPATH_STALL_RATIO_FE_CBUF_CNV_SHIFT (8U) #define VHA_CR_CNN_DATAPATH_STALL_RATIO_FE_CBUF_CNV_CLRMSK (0XFFFFF0FFU) #define VHA_CR_CNN_DATAPATH_STALL_RATIO_FE_ABUF_OUTPACK_SHIFT (4U) #define VHA_CR_CNN_DATAPATH_STALL_RATIO_FE_ABUF_OUTPACK_CLRMSK (0XFFFFFF0FU) #define VHA_CR_CNN_DATAPATH_STALL_RATIO_FE_CBUF_ABUF_SHIFT (0U) #define VHA_CR_CNN_DATAPATH_STALL_RATIO_FE_CBUF_ABUF_CLRMSK (0XFFFFFFF0U) /* Register VHA_CR_CNN_DATAPATH_STALL_RATIO_BE */ #define VHA_CR_CNN_DATAPATH_STALL_RATIO_BE (0x0370U) #define VHA_CR_CNN_DATAPATH_STALL_RATIO_BE_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF)) #define VHA_CR_CNN_DATAPATH_STALL_RATIO_BE_NORM_XBAR_SHIFT (28U) #define VHA_CR_CNN_DATAPATH_STALL_RATIO_BE_NORM_XBAR_CLRMSK (0X0FFFFFFFU) #define VHA_CR_CNN_DATAPATH_STALL_RATIO_BE_XBAR_OIN_SHIFT (24U) #define VHA_CR_CNN_DATAPATH_STALL_RATIO_BE_XBAR_OIN_CLRMSK (0XF0FFFFFFU) #define VHA_CR_CNN_DATAPATH_STALL_RATIO_BE_OIN_OUTPACK_SHIFT (20U) #define VHA_CR_CNN_DATAPATH_STALL_RATIO_BE_OIN_OUTPACK_CLRMSK (0XFF0FFFFFU) #define VHA_CR_CNN_DATAPATH_STALL_RATIO_BE_POOL_XBAR_SHIFT (16U) #define VHA_CR_CNN_DATAPATH_STALL_RATIO_BE_POOL_XBAR_CLRMSK (0XFFF0FFFFU) #define VHA_CR_CNN_DATAPATH_STALL_RATIO_BE_XBAR_POOL_SHIFT (12U) #define VHA_CR_CNN_DATAPATH_STALL_RATIO_BE_XBAR_POOL_CLRMSK (0XFFFF0FFFU) #define VHA_CR_CNN_DATAPATH_STALL_RATIO_BE_NORM_SB_SHIFT (8U) #define VHA_CR_CNN_DATAPATH_STALL_RATIO_BE_NORM_SB_CLRMSK (0XFFFFF0FFU) #define VHA_CR_CNN_DATAPATH_STALL_RATIO_BE_POOL_SB_SHIFT (4U) #define VHA_CR_CNN_DATAPATH_STALL_RATIO_BE_POOL_SB_CLRMSK (0XFFFFFF0FU) #define VHA_CR_CNN_DATAPATH_STALL_RATIO_BE_OIN_SB_SHIFT (0U) #define VHA_CR_CNN_DATAPATH_STALL_RATIO_BE_OIN_SB_CLRMSK (0XFFFFFFF0U) /* Register VHA_CR_RTM_CTRL */ #define VHA_CR_RTM_CTRL (0x0380U) #define VHA_CR_RTM_CTRL_MASKFULL (IMG_UINT64_C(0x000000008FFFFFF8)) #define VHA_CR_RTM_CTRL_RTM_ENABLE_SHIFT (31U) #define VHA_CR_RTM_CTRL_RTM_ENABLE_CLRMSK (0X7FFFFFFFU) #define VHA_CR_RTM_CTRL_RTM_ENABLE_EN (0X80000000U) #define VHA_CR_RTM_CTRL_RTM_SELECTOR_SHIFT (3U) #define VHA_CR_RTM_CTRL_RTM_SELECTOR_CLRMSK (0XF0000007U) /* Register VHA_CR_RTM_DATA */ #define VHA_CR_RTM_DATA (0x0388U) #define VHA_CR_RTM_DATA_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF)) #define VHA_CR_RTM_DATA_RTM_DATA_SHIFT (0U) #define VHA_CR_RTM_DATA_RTM_DATA_CLRMSK (00000000U) /* Register VHA_CR_CNN_IP_CONFIG0 */ #define VHA_CR_CNN_IP_CONFIG0 (0x03A0U) #define VHA_CR_CNN_IP_CONFIG0_MASKFULL (IMG_UINT64_C(0x0000000000003FFF)) #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_OUTPUT_FIXTOFIX_SUPPORTED_SHIFT (13U) #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_OUTPUT_FIXTOFIX_SUPPORTED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFDFFF)) #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_OUTPUT_FIXTOFIX_SUPPORTED_EN (IMG_UINT64_C(0X0000000000002000)) #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_DUAL_8BIT_CONV_SUPPORTED_SHIFT (12U) #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_DUAL_8BIT_CONV_SUPPORTED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFEFFF)) #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_DUAL_8BIT_CONV_SUPPORTED_EN (IMG_UINT64_C(0X0000000000001000)) #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_DATA_DECOMPRESSION_SUPPORTED_SHIFT (11U) #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_DATA_DECOMPRESSION_SUPPORTED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFF7FF)) #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_DATA_DECOMPRESSION_SUPPORTED_EN (IMG_UINT64_C(0X0000000000000800)) #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_DATA_COMPRESSION_SUPPORTED_SHIFT (10U) #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_DATA_COMPRESSION_SUPPORTED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFBFF)) #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_DATA_COMPRESSION_SUPPORTED_EN (IMG_UINT64_C(0X0000000000000400)) #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_ELEMENT_OPS_CALC_SUPPORTED_SHIFT (9U) #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_ELEMENT_OPS_CALC_SUPPORTED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFDFF)) #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_ELEMENT_OPS_CALC_SUPPORTED_EN (IMG_UINT64_C(0X0000000000000200)) #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_ELEMENT_OPS_FETCH_SUPPORTED_SHIFT (8U) #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_ELEMENT_OPS_FETCH_SUPPORTED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFEFF)) #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_ELEMENT_OPS_FETCH_SUPPORTED_EN (IMG_UINT64_C(0X0000000000000100)) #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_ELEMENT_OPS_SUPPORTED_SHIFT (7U) #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_ELEMENT_OPS_SUPPORTED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFF7F)) #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_ELEMENT_OPS_SUPPORTED_EN (IMG_UINT64_C(0X0000000000000080)) #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_POOL_AVG_SUPPORTED_SHIFT (6U) #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_POOL_AVG_SUPPORTED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFBF)) #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_POOL_AVG_SUPPORTED_EN (IMG_UINT64_C(0X0000000000000040)) #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_POOL_MAX_SUPPORTED_SHIFT (5U) #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_POOL_MAX_SUPPORTED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFDF)) #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_POOL_MAX_SUPPORTED_EN (IMG_UINT64_C(0X0000000000000020)) #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_NORM_ICN_SUPPORTED_SHIFT (4U) #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_NORM_ICN_SUPPORTED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFEF)) #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_NORM_ICN_SUPPORTED_EN (IMG_UINT64_C(0X0000000000000010)) #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_NORM_ACN_SUPPORTED_SHIFT (3U) #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_NORM_ACN_SUPPORTED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFF7)) #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_NORM_ACN_SUPPORTED_EN (IMG_UINT64_C(0X0000000000000008)) #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_ACT_LUT_SUPPORTED_SHIFT (2U) #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_ACT_LUT_SUPPORTED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFB)) #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_ACT_LUT_SUPPORTED_EN (IMG_UINT64_C(0X0000000000000004)) #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_DECONV_SUPPORTED_SHIFT (1U) #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_DECONV_SUPPORTED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFD)) #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_DECONV_SUPPORTED_EN (IMG_UINT64_C(0X0000000000000002)) #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_CONV_SUPPORTED_SHIFT (0U) #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_CONV_SUPPORTED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFE)) #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_CONV_SUPPORTED_EN (IMG_UINT64_C(0X0000000000000001)) /* Register VHA_CR_CNN_IP_CONFIG1 */ #define VHA_CR_CNN_IP_CONFIG1 (0x03A8U) #define VHA_CR_CNN_IP_CONFIG1_MASKFULL (IMG_UINT64_C(0x000000003F0FFFFF)) #define VHA_CR_CNN_IP_CONFIG1_VHA_CNN_WEIGHT_DATA_WIDTH_MIN1_SHIFT (24U) #define VHA_CR_CNN_IP_CONFIG1_VHA_CNN_WEIGHT_DATA_WIDTH_MIN1_CLRMSK (IMG_UINT64_C(0XFFFFFFFFC0FFFFFF)) #define VHA_CR_CNN_IP_CONFIG1_VHA_CNN_ACTIVATION_DATA_WIDTH_MIN1_SHIFT (16U) #define VHA_CR_CNN_IP_CONFIG1_VHA_CNN_ACTIVATION_DATA_WIDTH_MIN1_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFF0FFFF)) #define VHA_CR_CNN_IP_CONFIG1_VHA_CNN_CONV_ENGINE_NUM_FILTERS_MIN1_SHIFT (12U) #define VHA_CR_CNN_IP_CONFIG1_VHA_CNN_CONV_ENGINE_NUM_FILTERS_MIN1_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFF0FFF)) #define VHA_CR_CNN_IP_CONFIG1_VHA_CNN_CONV_ENGINE_NUM_COEFFS_MIN1_SHIFT (4U) #define VHA_CR_CNN_IP_CONFIG1_VHA_CNN_CONV_ENGINE_NUM_COEFFS_MIN1_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFF00F)) #define VHA_CR_CNN_IP_CONFIG1_VHA_CNN_CONV_ENGINE_CALC_BLOCKS_MIN1_SHIFT (0U) #define VHA_CR_CNN_IP_CONFIG1_VHA_CNN_CONV_ENGINE_CALC_BLOCKS_MIN1_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFF0)) /* Register VHA_CR_CNN_IP_CONFIG2 */ #define VHA_CR_CNN_IP_CONFIG2 (0x03B0U) #define VHA_CR_CNN_IP_CONFIG2_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF)) #define VHA_CR_CNN_IP_CONFIG2_VHA_CNN_NORM_UNITS_MIN1_SHIFT (28U) #define VHA_CR_CNN_IP_CONFIG2_VHA_CNN_NORM_UNITS_MIN1_CLRMSK (IMG_UINT64_C(0XFFFFFFFF0FFFFFFF)) #define VHA_CR_CNN_IP_CONFIG2_VHA_CNN_SHARED_BUFFER_SIZE_MIN1_SHIFT (20U) #define VHA_CR_CNN_IP_CONFIG2_VHA_CNN_SHARED_BUFFER_SIZE_MIN1_CLRMSK (IMG_UINT64_C(0XFFFFFFFFF00FFFFF)) #define VHA_CR_CNN_IP_CONFIG2_VHA_CNN_COEFF_BUFFER_SIZE_MIN1_SHIFT (4U) #define VHA_CR_CNN_IP_CONFIG2_VHA_CNN_COEFF_BUFFER_SIZE_MIN1_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFF0000F)) #define VHA_CR_CNN_IP_CONFIG2_VHA_CNN_COEFF_BUFFER_BANKS_MIN1_SHIFT (0U) #define VHA_CR_CNN_IP_CONFIG2_VHA_CNN_COEFF_BUFFER_BANKS_MIN1_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFF0)) /* Register VHA_CR_CNN_IP_CONFIG3 */ #define VHA_CR_CNN_IP_CONFIG3 (0x03B8U) #define VHA_CR_CNN_IP_CONFIG3_MASKFULL (IMG_UINT64_C(0x0000000000FFFFFF)) #define VHA_CR_CNN_IP_CONFIG3_VHA_CNN_ACT_LUT_SIZE_MIN1_SHIFT (16U) #define VHA_CR_CNN_IP_CONFIG3_VHA_CNN_ACT_LUT_SIZE_MIN1_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFF00FFFF)) #define VHA_CR_CNN_IP_CONFIG3_VHA_CNN_INPUT_BUFFER_SIZE_MIN1_SHIFT (8U) #define VHA_CR_CNN_IP_CONFIG3_VHA_CNN_INPUT_BUFFER_SIZE_MIN1_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFF00FF)) #define VHA_CR_CNN_IP_CONFIG3_VHA_CNN_INPUT_BUFFER_BANKS_MIN1_SHIFT (0U) #define VHA_CR_CNN_IP_CONFIG3_VHA_CNN_INPUT_BUFFER_BANKS_MIN1_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFF00)) /* Register VHA_CR_BIF_OUTSTANDING_READ */ #define VHA_CR_BIF_OUTSTANDING_READ (0xF098U) #define VHA_CR_BIF_OUTSTANDING_READ_MASKFULL (IMG_UINT64_C(0x000000000000FFFF)) #define VHA_CR_BIF_OUTSTANDING_READ_COUNTER_SHIFT (0U) #define VHA_CR_BIF_OUTSTANDING_READ_COUNTER_CLRMSK (0XFFFF0000U) /* Register VHA_CR_BIF_PAGE_FAULT_STALL */ #define VHA_CR_BIF_PAGE_FAULT_STALL (0xF0B0U) #define VHA_CR_BIF_PAGE_FAULT_STALL_MASKFULL (IMG_UINT64_C(0x0000000000000001)) #define VHA_CR_BIF_PAGE_FAULT_STALL_STATUS_SHIFT (0U) #define VHA_CR_BIF_PAGE_FAULT_STALL_STATUS_CLRMSK (0XFFFFFFFEU) #define VHA_CR_BIF_PAGE_FAULT_STALL_STATUS_EN (0X00000001U) /* Register VHA_CR_BIF_RTN_FIFO_WORD_COUNT */ #define VHA_CR_BIF_RTN_FIFO_WORD_COUNT (0xF230U) #define VHA_CR_BIF_RTN_FIFO_WORD_COUNT_MASKFULL (IMG_UINT64_C(0x00000000000001FF)) #define VHA_CR_BIF_RTN_FIFO_WORD_COUNT_COUNTER_SHIFT (0U) #define VHA_CR_BIF_RTN_FIFO_WORD_COUNT_COUNTER_CLRMSK (0XFFFFFE00U) /* Register VHA_CR_IDLE_HYSTERESIS_COUNT */ #define VHA_CR_IDLE_HYSTERESIS_COUNT (0x1000U) #define VHA_CR_IDLE_HYSTERESIS_COUNT_MASKFULL (IMG_UINT64_C(0x0000001F1F1F1F1F)) #define VHA_CR_IDLE_HYSTERESIS_COUNT_VHA_SYS_SHIFT (32U) #define VHA_CR_IDLE_HYSTERESIS_COUNT_VHA_SYS_CLRMSK (IMG_UINT64_C(0XFFFFFFE0FFFFFFFF)) #define VHA_CR_IDLE_HYSTERESIS_COUNT_CNN_FE_SHIFT (24U) #define VHA_CR_IDLE_HYSTERESIS_COUNT_CNN_FE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFE0FFFFFF)) #define VHA_CR_IDLE_HYSTERESIS_COUNT_CNN_BE_SHIFT (16U) #define VHA_CR_IDLE_HYSTERESIS_COUNT_CNN_BE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFE0FFFF)) #define VHA_CR_IDLE_HYSTERESIS_COUNT_CNN_TOP_SHIFT (8U) #define VHA_CR_IDLE_HYSTERESIS_COUNT_CNN_TOP_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFE0FF)) #define VHA_CR_IDLE_HYSTERESIS_COUNT_VHA_CTRL_SHIFT (0U) #define VHA_CR_IDLE_HYSTERESIS_COUNT_VHA_CTRL_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFE0)) /* Register VHA_CR_SOCIF_WAKEUP_ENABLE */ #define VHA_CR_SOCIF_WAKEUP_ENABLE (0x1008U) #define VHA_CR_SOCIF_WAKEUP_ENABLE_MASKFULL (IMG_UINT64_C(0x0000000000000001)) #define VHA_CR_SOCIF_WAKEUP_ENABLE_ALWAYS_SHIFT (0U) #define VHA_CR_SOCIF_WAKEUP_ENABLE_ALWAYS_CLRMSK (0XFFFFFFFEU) #define VHA_CR_SOCIF_WAKEUP_ENABLE_ALWAYS_EN (0X00000001U) /* Register VHA_CR_REGBANK_REQUEST_INVALID */ #define VHA_CR_REGBANK_REQUEST_INVALID (0x1018U) #define VHA_CR_REGBANK_REQUEST_INVALID_MASKFULL (IMG_UINT64_C(0x0000000000000001)) #define VHA_CR_REGBANK_REQUEST_INVALID_FLAG_SHIFT (0U) #define VHA_CR_REGBANK_REQUEST_INVALID_FLAG_CLRMSK (0XFFFFFFFEU) #define VHA_CR_REGBANK_REQUEST_INVALID_FLAG_EN (0X00000001U) /* Register VHA_CR_RESET_CLK_CTRL */ #define VHA_CR_RESET_CLK_CTRL (0x1020U) #define VHA_CR_RESET_CLK_CTRL_MASKFULL (IMG_UINT64_C(0x00000000000003FF)) #define VHA_CR_RESET_CLK_CTRL_VHA_SYS_SHIFT (8U) #define VHA_CR_RESET_CLK_CTRL_VHA_SYS_CLRMSK (0XFFFFFCFFU) #define VHA_CR_RESET_CLK_CTRL_CNN_FE_SHIFT (6U) #define VHA_CR_RESET_CLK_CTRL_CNN_FE_CLRMSK (0XFFFFFF3FU) #define VHA_CR_RESET_CLK_CTRL_CNN_BE_SHIFT (4U) #define VHA_CR_RESET_CLK_CTRL_CNN_BE_CLRMSK (0XFFFFFFCFU) #define VHA_CR_RESET_CLK_CTRL_CNN_TOP_SHIFT (2U) #define VHA_CR_RESET_CLK_CTRL_CNN_TOP_CLRMSK (0XFFFFFFF3U) #define VHA_CR_RESET_CLK_CTRL_VHA_CTRL_SHIFT (0U) #define VHA_CR_RESET_CLK_CTRL_VHA_CTRL_CLRMSK (0XFFFFFFFCU) /* Register VHA_CR_PM_VFP_TRAN_EN */ #define VHA_CR_PM_VFP_TRAN_EN (0x2100U) #define VHA_CR_PM_VFP_TRAN_EN_MASKFULL (IMG_UINT64_C(0x0000000000000001)) #define VHA_CR_PM_VFP_TRAN_EN_OP_SHIFT (0U) #define VHA_CR_PM_VFP_TRAN_EN_OP_CLRMSK (0XFFFFFFFEU) #define VHA_CR_PM_VFP_TRAN_EN_OP_EN (0X00000001U) /* Register VHA_CR_PERF_SLC0_READ */ #define VHA_CR_PERF_SLC0_READ (0x60A0U) #define VHA_CR_PERF_SLC0_READ_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF)) #define VHA_CR_PERF_SLC0_READ_COUNT_SHIFT (0U) #define VHA_CR_PERF_SLC0_READ_COUNT_CLRMSK (00000000U) /* Register VHA_CR_PERF_SLC0_WRITE */ #define VHA_CR_PERF_SLC0_WRITE (0x60A8U) #define VHA_CR_PERF_SLC0_WRITE_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF)) #define VHA_CR_PERF_SLC0_WRITE_COUNT_SHIFT (0U) #define VHA_CR_PERF_SLC0_WRITE_COUNT_CLRMSK (00000000U) /* Register VHA_CR_PERF_SLC0_WRITE_DATA_STALL */ #define VHA_CR_PERF_SLC0_WRITE_DATA_STALL (0x60B0U) #define VHA_CR_PERF_SLC0_WRITE_DATA_STALL_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF)) #define VHA_CR_PERF_SLC0_WRITE_DATA_STALL_COUNT_SHIFT (0U) #define VHA_CR_PERF_SLC0_WRITE_DATA_STALL_COUNT_CLRMSK (00000000U) /* Register VHA_CR_PERF_SLC0_READ_STALL */ #define VHA_CR_PERF_SLC0_READ_STALL (0x60B8U) #define VHA_CR_PERF_SLC0_READ_STALL_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF)) #define VHA_CR_PERF_SLC0_READ_STALL_COUNT_SHIFT (0U) #define VHA_CR_PERF_SLC0_READ_STALL_COUNT_CLRMSK (00000000U) /* Register VHA_CR_PERF_SLC0_WRITE_STALL */ #define VHA_CR_PERF_SLC0_WRITE_STALL (0x60C0U) #define VHA_CR_PERF_SLC0_WRITE_STALL_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF)) #define VHA_CR_PERF_SLC0_WRITE_STALL_COUNT_SHIFT (0U) #define VHA_CR_PERF_SLC0_WRITE_STALL_COUNT_CLRMSK (00000000U) /* Register VHA_CR_PERF_SLC0_READ_ID_STALL */ #define VHA_CR_PERF_SLC0_READ_ID_STALL (0x60F0U) #define VHA_CR_PERF_SLC0_READ_ID_STALL_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF)) #define VHA_CR_PERF_SLC0_READ_ID_STALL_COUNT_SHIFT (0U) #define VHA_CR_PERF_SLC0_READ_ID_STALL_COUNT_CLRMSK (00000000U) /* Register VHA_CR_PERF_SLC0_WRITE_ID_STALL */ #define VHA_CR_PERF_SLC0_WRITE_ID_STALL (0x60F8U) #define VHA_CR_PERF_SLC0_WRITE_ID_STALL_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF)) #define VHA_CR_PERF_SLC0_WRITE_ID_STALL_COUNT_SHIFT (0U) #define VHA_CR_PERF_SLC0_WRITE_ID_STALL_COUNT_CLRMSK (00000000U) /* Register VHA_CR_PERF_SLC0_RD_BURST_SIZE1 */ #define VHA_CR_PERF_SLC0_RD_BURST_SIZE1 (0x6130U) #define VHA_CR_PERF_SLC0_RD_BURST_SIZE1_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF)) #define VHA_CR_PERF_SLC0_RD_BURST_SIZE1_COUNT_SHIFT (0U) #define VHA_CR_PERF_SLC0_RD_BURST_SIZE1_COUNT_CLRMSK (00000000U) /* Register VHA_CR_PERF_SLC0_WR_BURST_SIZE1 */ #define VHA_CR_PERF_SLC0_WR_BURST_SIZE1 (0x6138U) #define VHA_CR_PERF_SLC0_WR_BURST_SIZE1_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF)) #define VHA_CR_PERF_SLC0_WR_BURST_SIZE1_COUNT_SHIFT (0U) #define VHA_CR_PERF_SLC0_WR_BURST_SIZE1_COUNT_CLRMSK (00000000U) /* Register VHA_CR_PERF_SLC0_RD_BURST_SIZE2 */ #define VHA_CR_PERF_SLC0_RD_BURST_SIZE2 (0x6190U) #define VHA_CR_PERF_SLC0_RD_BURST_SIZE2_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF)) #define VHA_CR_PERF_SLC0_RD_BURST_SIZE2_COUNT_SHIFT (0U) #define VHA_CR_PERF_SLC0_RD_BURST_SIZE2_COUNT_CLRMSK (00000000U) /* Register VHA_CR_PERF_SLC0_WR_BURST_SIZE2 */ #define VHA_CR_PERF_SLC0_WR_BURST_SIZE2 (0x6198U) #define VHA_CR_PERF_SLC0_WR_BURST_SIZE2_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF)) #define VHA_CR_PERF_SLC0_WR_BURST_SIZE2_COUNT_SHIFT (0U) #define VHA_CR_PERF_SLC0_WR_BURST_SIZE2_COUNT_CLRMSK (00000000U) /* Register VHA_CR_PERF_SLC0_RD_BURST_SIZE3 */ #define VHA_CR_PERF_SLC0_RD_BURST_SIZE3 (0x61B0U) #define VHA_CR_PERF_SLC0_RD_BURST_SIZE3_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF)) #define VHA_CR_PERF_SLC0_RD_BURST_SIZE3_COUNT_SHIFT (0U) #define VHA_CR_PERF_SLC0_RD_BURST_SIZE3_COUNT_CLRMSK (00000000U) /* Register VHA_CR_PERF_SLC0_WR_BURST_SIZE3 */ #define VHA_CR_PERF_SLC0_WR_BURST_SIZE3 (0x61B8U) #define VHA_CR_PERF_SLC0_WR_BURST_SIZE3_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF)) #define VHA_CR_PERF_SLC0_WR_BURST_SIZE3_COUNT_SHIFT (0U) #define VHA_CR_PERF_SLC0_WR_BURST_SIZE3_COUNT_CLRMSK (00000000U) /* Register VHA_CR_PERF_SLC0_RD_BURST_SIZE4 */ #define VHA_CR_PERF_SLC0_RD_BURST_SIZE4 (0x61C0U) #define VHA_CR_PERF_SLC0_RD_BURST_SIZE4_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF)) #define VHA_CR_PERF_SLC0_RD_BURST_SIZE4_COUNT_SHIFT (0U) #define VHA_CR_PERF_SLC0_RD_BURST_SIZE4_COUNT_CLRMSK (00000000U) /* Register VHA_CR_PERF_SLC0_WR_BURST_SIZE4 */ #define VHA_CR_PERF_SLC0_WR_BURST_SIZE4 (0x61C8U) #define VHA_CR_PERF_SLC0_WR_BURST_SIZE4_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF)) #define VHA_CR_PERF_SLC0_WR_BURST_SIZE4_COUNT_SHIFT (0U) #define VHA_CR_PERF_SLC0_WR_BURST_SIZE4_COUNT_CLRMSK (00000000U) /* Register VHA_CR_PERF_SLC_SNOOP_HITS */ #define VHA_CR_PERF_SLC_SNOOP_HITS (0x61A0U) #define VHA_CR_PERF_SLC_SNOOP_HITS_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF)) #define VHA_CR_PERF_SLC_SNOOP_HITS_COUNT_SHIFT (0U) #define VHA_CR_PERF_SLC_SNOOP_HITS_COUNT_CLRMSK (00000000U) /* Register VHA_CR_PERF_SLC_SNOOP_MISSES */ #define VHA_CR_PERF_SLC_SNOOP_MISSES (0x61A8U) #define VHA_CR_PERF_SLC_SNOOP_MISSES_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF)) #define VHA_CR_PERF_SLC_SNOOP_MISSES_COUNT_SHIFT (0U) #define VHA_CR_PERF_SLC_SNOOP_MISSES_COUNT_CLRMSK (00000000U) /* Register VHA_CR_PERF_RESET_FULL */ #define VHA_CR_PERF_RESET_FULL (0x3990U) #define VHA_CR_PERF_RESET_FULL_MASKFULL (IMG_UINT64_C(0x0000000000000001)) #define VHA_CR_PERF_RESET_FULL_RANGE_SHIFT (0U) #define VHA_CR_PERF_RESET_FULL_RANGE_CLRMSK (0XFFFFFFFEU) #define VHA_CR_PERF_RESET_FULL_RANGE_EN (0X00000001U) /* Register VHA_CR_PERF_ENABLE_FULL */ #define VHA_CR_PERF_ENABLE_FULL (0x3998U) #define VHA_CR_PERF_ENABLE_FULL_MASKFULL (IMG_UINT64_C(0x0000000000000001)) #define VHA_CR_PERF_ENABLE_FULL_RANGE_SHIFT (0U) #define VHA_CR_PERF_ENABLE_FULL_RANGE_CLRMSK (0XFFFFFFFEU) #define VHA_CR_PERF_ENABLE_FULL_RANGE_EN (0X00000001U) /* Register VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE0 */ #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE0 (0xE008U) #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE0_MASKFULL (IMG_UINT64_C(0x0FFFFFFFFFFFF003)) #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE0_INIT_PAGE_SHIFT (40U) #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE0_INIT_PAGE_CLRMSK (IMG_UINT64_C(0XF00000FFFFFFFFFF)) #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE0_ADDR_SHIFT (12U) #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE0_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF0000000FFF)) #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE0_WRAP_SHIFT (1U) #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE0_WRAP_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFD)) #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE0_WRAP_EN (IMG_UINT64_C(0X0000000000000002)) #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE0_VALID_SHIFT (0U) #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE0_VALID_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFE)) #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE0_VALID_EN (IMG_UINT64_C(0X0000000000000001)) /* Register VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE1 */ #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE1 (0xE010U) #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE1_MASKFULL (IMG_UINT64_C(0x00000003FFFFC003)) #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE1_INIT_PAGE_SHIFT (14U) #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE1_INIT_PAGE_CLRMSK (IMG_UINT64_C(0XFFFFFFFC00003FFF)) #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE1_WRAP_SHIFT (1U) #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE1_WRAP_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFD)) #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE1_WRAP_EN (IMG_UINT64_C(0X0000000000000002)) #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE1_VALID_SHIFT (0U) #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE1_VALID_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFE)) #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE1_VALID_EN (IMG_UINT64_C(0X0000000000000001)) /* Register VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE2 */ #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE2 (0xE018U) #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE2_MASKFULL (IMG_UINT64_C(0x00000003FFFFC003)) #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE2_INIT_PAGE_SHIFT (14U) #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE2_INIT_PAGE_CLRMSK (IMG_UINT64_C(0XFFFFFFFC00003FFF)) #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE2_WRAP_SHIFT (1U) #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE2_WRAP_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFD)) #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE2_WRAP_EN (IMG_UINT64_C(0X0000000000000002)) #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE2_VALID_SHIFT (0U) #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE2_VALID_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFE)) #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE2_VALID_EN (IMG_UINT64_C(0X0000000000000001)) /* Register VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE3 */ #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE3 (0xE020U) #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE3_MASKFULL (IMG_UINT64_C(0x00000003FFFFC003)) #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE3_INIT_PAGE_SHIFT (14U) #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE3_INIT_PAGE_CLRMSK (IMG_UINT64_C(0XFFFFFFFC00003FFF)) #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE3_WRAP_SHIFT (1U) #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE3_WRAP_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFD)) #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE3_WRAP_EN (IMG_UINT64_C(0X0000000000000002)) #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE3_VALID_SHIFT (0U) #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE3_VALID_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFE)) #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE3_VALID_EN (IMG_UINT64_C(0X0000000000000001)) /* Register VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE0 */ #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE0 (0xE028U) #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE0_MASKFULL (IMG_UINT64_C(0x0FFFFFFFFFFFF003)) #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE0_INIT_PAGE_SHIFT (40U) #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE0_INIT_PAGE_CLRMSK (IMG_UINT64_C(0XF00000FFFFFFFFFF)) #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE0_ADDR_SHIFT (12U) #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE0_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF0000000FFF)) #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE0_WRAP_SHIFT (1U) #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE0_WRAP_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFD)) #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE0_WRAP_EN (IMG_UINT64_C(0X0000000000000002)) #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE0_VALID_SHIFT (0U) #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE0_VALID_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFE)) #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE0_VALID_EN (IMG_UINT64_C(0X0000000000000001)) /* Register VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE1 */ #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE1 (0xE030U) #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE1_MASKFULL (IMG_UINT64_C(0x00000003FFFFC003)) #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE1_INIT_PAGE_SHIFT (14U) #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE1_INIT_PAGE_CLRMSK (IMG_UINT64_C(0XFFFFFFFC00003FFF)) #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE1_WRAP_SHIFT (1U) #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE1_WRAP_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFD)) #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE1_WRAP_EN (IMG_UINT64_C(0X0000000000000002)) #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE1_VALID_SHIFT (0U) #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE1_VALID_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFE)) #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE1_VALID_EN (IMG_UINT64_C(0X0000000000000001)) /* Register VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE2 */ #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE2 (0xE038U) #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE2_MASKFULL (IMG_UINT64_C(0x00000003FFFFC003)) #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE2_INIT_PAGE_SHIFT (14U) #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE2_INIT_PAGE_CLRMSK (IMG_UINT64_C(0XFFFFFFFC00003FFF)) #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE2_WRAP_SHIFT (1U) #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE2_WRAP_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFD)) #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE2_WRAP_EN (IMG_UINT64_C(0X0000000000000002)) #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE2_VALID_SHIFT (0U) #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE2_VALID_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFE)) #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE2_VALID_EN (IMG_UINT64_C(0X0000000000000001)) /* Register VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE3 */ #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE3 (0xE040U) #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE3_MASKFULL (IMG_UINT64_C(0x00000003FFFFC003)) #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE3_INIT_PAGE_SHIFT (14U) #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE3_INIT_PAGE_CLRMSK (IMG_UINT64_C(0XFFFFFFFC00003FFF)) #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE3_WRAP_SHIFT (1U) #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE3_WRAP_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFD)) #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE3_WRAP_EN (IMG_UINT64_C(0X0000000000000002)) #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE3_VALID_SHIFT (0U) #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE3_VALID_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFE)) #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE3_VALID_EN (IMG_UINT64_C(0X0000000000000001)) /* Register VHA_CR_MMU_PM_CAT_BASE_ALIST0 */ #define VHA_CR_MMU_PM_CAT_BASE_ALIST0 (0xE048U) #define VHA_CR_MMU_PM_CAT_BASE_ALIST0_MASKFULL (IMG_UINT64_C(0x0FFFFFFFFFFFF003)) #define VHA_CR_MMU_PM_CAT_BASE_ALIST0_INIT_PAGE_SHIFT (40U) #define VHA_CR_MMU_PM_CAT_BASE_ALIST0_INIT_PAGE_CLRMSK (IMG_UINT64_C(0XF00000FFFFFFFFFF)) #define VHA_CR_MMU_PM_CAT_BASE_ALIST0_ADDR_SHIFT (12U) #define VHA_CR_MMU_PM_CAT_BASE_ALIST0_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF0000000FFF)) #define VHA_CR_MMU_PM_CAT_BASE_ALIST0_WRAP_SHIFT (1U) #define VHA_CR_MMU_PM_CAT_BASE_ALIST0_WRAP_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFD)) #define VHA_CR_MMU_PM_CAT_BASE_ALIST0_WRAP_EN (IMG_UINT64_C(0X0000000000000002)) #define VHA_CR_MMU_PM_CAT_BASE_ALIST0_VALID_SHIFT (0U) #define VHA_CR_MMU_PM_CAT_BASE_ALIST0_VALID_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFE)) #define VHA_CR_MMU_PM_CAT_BASE_ALIST0_VALID_EN (IMG_UINT64_C(0X0000000000000001)) /* Register VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE0 */ #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE0 (0xE050U) #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE0_MASKFULL (IMG_UINT64_C(0x0FFFFFFFFFFFF003)) #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE0_INIT_PAGE_SHIFT (40U) #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE0_INIT_PAGE_CLRMSK (IMG_UINT64_C(0XF00000FFFFFFFFFF)) #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE0_ADDR_SHIFT (12U) #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE0_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF0000000FFF)) #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE0_WRAP_SHIFT (1U) #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE0_WRAP_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFD)) #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE0_WRAP_EN (IMG_UINT64_C(0X0000000000000002)) #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE0_VALID_SHIFT (0U) #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE0_VALID_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFE)) #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE0_VALID_EN (IMG_UINT64_C(0X0000000000000001)) /* Register VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE1 */ #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE1 (0xE058U) #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE1_MASKFULL (IMG_UINT64_C(0x00000003FFFFC003)) #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE1_INIT_PAGE_SHIFT (14U) #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE1_INIT_PAGE_CLRMSK (IMG_UINT64_C(0XFFFFFFFC00003FFF)) #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE1_WRAP_SHIFT (1U) #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE1_WRAP_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFD)) #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE1_WRAP_EN (IMG_UINT64_C(0X0000000000000002)) #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE1_VALID_SHIFT (0U) #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE1_VALID_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFE)) #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE1_VALID_EN (IMG_UINT64_C(0X0000000000000001)) /* Register VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE2 */ #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE2 (0xE060U) #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE2_MASKFULL (IMG_UINT64_C(0x00000003FFFFC003)) #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE2_INIT_PAGE_SHIFT (14U) #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE2_INIT_PAGE_CLRMSK (IMG_UINT64_C(0XFFFFFFFC00003FFF)) #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE2_WRAP_SHIFT (1U) #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE2_WRAP_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFD)) #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE2_WRAP_EN (IMG_UINT64_C(0X0000000000000002)) #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE2_VALID_SHIFT (0U) #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE2_VALID_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFE)) #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE2_VALID_EN (IMG_UINT64_C(0X0000000000000001)) /* Register VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE3 */ #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE3 (0xE068U) #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE3_MASKFULL (IMG_UINT64_C(0x00000003FFFFC003)) #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE3_INIT_PAGE_SHIFT (14U) #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE3_INIT_PAGE_CLRMSK (IMG_UINT64_C(0XFFFFFFFC00003FFF)) #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE3_WRAP_SHIFT (1U) #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE3_WRAP_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFD)) #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE3_WRAP_EN (IMG_UINT64_C(0X0000000000000002)) #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE3_VALID_SHIFT (0U) #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE3_VALID_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFE)) #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE3_VALID_EN (IMG_UINT64_C(0X0000000000000001)) /* Register VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE0 */ #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE0 (0xE070U) #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE0_MASKFULL (IMG_UINT64_C(0x0FFFFFFFFFFFF003)) #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE0_INIT_PAGE_SHIFT (40U) #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE0_INIT_PAGE_CLRMSK (IMG_UINT64_C(0XF00000FFFFFFFFFF)) #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE0_ADDR_SHIFT (12U) #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE0_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF0000000FFF)) #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE0_WRAP_SHIFT (1U) #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE0_WRAP_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFD)) #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE0_WRAP_EN (IMG_UINT64_C(0X0000000000000002)) #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE0_VALID_SHIFT (0U) #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE0_VALID_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFE)) #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE0_VALID_EN (IMG_UINT64_C(0X0000000000000001)) /* Register VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE1 */ #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE1 (0xE078U) #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE1_MASKFULL (IMG_UINT64_C(0x00000003FFFFC003)) #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE1_INIT_PAGE_SHIFT (14U) #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE1_INIT_PAGE_CLRMSK (IMG_UINT64_C(0XFFFFFFFC00003FFF)) #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE1_WRAP_SHIFT (1U) #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE1_WRAP_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFD)) #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE1_WRAP_EN (IMG_UINT64_C(0X0000000000000002)) #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE1_VALID_SHIFT (0U) #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE1_VALID_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFE)) #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE1_VALID_EN (IMG_UINT64_C(0X0000000000000001)) /* Register VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE2 */ #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE2 (0xE080U) #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE2_MASKFULL (IMG_UINT64_C(0x00000003FFFFC003)) #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE2_INIT_PAGE_SHIFT (14U) #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE2_INIT_PAGE_CLRMSK (IMG_UINT64_C(0XFFFFFFFC00003FFF)) #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE2_WRAP_SHIFT (1U) #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE2_WRAP_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFD)) #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE2_WRAP_EN (IMG_UINT64_C(0X0000000000000002)) #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE2_VALID_SHIFT (0U) #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE2_VALID_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFE)) #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE2_VALID_EN (IMG_UINT64_C(0X0000000000000001)) /* Register VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE3 */ #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE3 (0xE088U) #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE3_MASKFULL (IMG_UINT64_C(0x00000003FFFFC003)) #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE3_INIT_PAGE_SHIFT (14U) #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE3_INIT_PAGE_CLRMSK (IMG_UINT64_C(0XFFFFFFFC00003FFF)) #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE3_WRAP_SHIFT (1U) #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE3_WRAP_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFD)) #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE3_WRAP_EN (IMG_UINT64_C(0X0000000000000002)) #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE3_VALID_SHIFT (0U) #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE3_VALID_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFE)) #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE3_VALID_EN (IMG_UINT64_C(0X0000000000000001)) /* Register VHA_CR_MMU_PM_CAT_BASE_ALIST1 */ #define VHA_CR_MMU_PM_CAT_BASE_ALIST1 (0xE090U) #define VHA_CR_MMU_PM_CAT_BASE_ALIST1_MASKFULL (IMG_UINT64_C(0x0FFFFFFFFFFFF003)) #define VHA_CR_MMU_PM_CAT_BASE_ALIST1_INIT_PAGE_SHIFT (40U) #define VHA_CR_MMU_PM_CAT_BASE_ALIST1_INIT_PAGE_CLRMSK (IMG_UINT64_C(0XF00000FFFFFFFFFF)) #define VHA_CR_MMU_PM_CAT_BASE_ALIST1_ADDR_SHIFT (12U) #define VHA_CR_MMU_PM_CAT_BASE_ALIST1_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF0000000FFF)) #define VHA_CR_MMU_PM_CAT_BASE_ALIST1_WRAP_SHIFT (1U) #define VHA_CR_MMU_PM_CAT_BASE_ALIST1_WRAP_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFD)) #define VHA_CR_MMU_PM_CAT_BASE_ALIST1_WRAP_EN (IMG_UINT64_C(0X0000000000000002)) #define VHA_CR_MMU_PM_CAT_BASE_ALIST1_VALID_SHIFT (0U) #define VHA_CR_MMU_PM_CAT_BASE_ALIST1_VALID_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFE)) #define VHA_CR_MMU_PM_CAT_BASE_ALIST1_VALID_EN (IMG_UINT64_C(0X0000000000000001)) /* Register VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE0_LAST */ #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE0_LAST (0xE098U) #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE0_LAST_MASKFULL (IMG_UINT64_C(0x00000003FFFFC000)) #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE0_LAST_PAGE_SHIFT (14U) #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE0_LAST_PAGE_CLRMSK (IMG_UINT64_C(0XFFFFFFFC00003FFF)) #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE0_LAST_PAGE_ALIGNSHIFT (14U) #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE0_LAST_PAGE_ALIGNSIZE (16384U) /* Register VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE1_LAST */ #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE1_LAST (0xE0A0U) #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE1_LAST_MASKFULL (IMG_UINT64_C(0x00000003FFFFC000)) #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE1_LAST_PAGE_SHIFT (14U) #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE1_LAST_PAGE_CLRMSK (IMG_UINT64_C(0XFFFFFFFC00003FFF)) #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE1_LAST_PAGE_ALIGNSHIFT (14U) #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE1_LAST_PAGE_ALIGNSIZE (16384U) /* Register VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE2_LAST */ #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE2_LAST (0xE0A8U) #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE2_LAST_MASKFULL (IMG_UINT64_C(0x00000003FFFFC000)) #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE2_LAST_PAGE_SHIFT (14U) #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE2_LAST_PAGE_CLRMSK (IMG_UINT64_C(0XFFFFFFFC00003FFF)) #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE2_LAST_PAGE_ALIGNSHIFT (14U) #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE2_LAST_PAGE_ALIGNSIZE (16384U) /* Register VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE3_LAST */ #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE3_LAST (0xE0B0U) #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE3_LAST_MASKFULL (IMG_UINT64_C(0x00000003FFFFC000)) #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE3_LAST_PAGE_SHIFT (14U) #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE3_LAST_PAGE_CLRMSK (IMG_UINT64_C(0XFFFFFFFC00003FFF)) #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE3_LAST_PAGE_ALIGNSHIFT (14U) #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE3_LAST_PAGE_ALIGNSIZE (16384U) /* Register VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE0_LAST */ #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE0_LAST (0xE0B8U) #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE0_LAST_MASKFULL (IMG_UINT64_C(0x00000003FFFFC000)) #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE0_LAST_PAGE_SHIFT (14U) #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE0_LAST_PAGE_CLRMSK (IMG_UINT64_C(0XFFFFFFFC00003FFF)) #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE0_LAST_PAGE_ALIGNSHIFT (14U) #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE0_LAST_PAGE_ALIGNSIZE (16384U) /* Register VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE1_LAST */ #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE1_LAST (0xE0C0U) #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE1_LAST_MASKFULL (IMG_UINT64_C(0x00000003FFFFC000)) #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE1_LAST_PAGE_SHIFT (14U) #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE1_LAST_PAGE_CLRMSK (IMG_UINT64_C(0XFFFFFFFC00003FFF)) #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE1_LAST_PAGE_ALIGNSHIFT (14U) #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE1_LAST_PAGE_ALIGNSIZE (16384U) /* Register VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE2_LAST */ #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE2_LAST (0xE0C8U) #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE2_LAST_MASKFULL (IMG_UINT64_C(0x00000003FFFFC000)) #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE2_LAST_PAGE_SHIFT (14U) #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE2_LAST_PAGE_CLRMSK (IMG_UINT64_C(0XFFFFFFFC00003FFF)) #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE2_LAST_PAGE_ALIGNSHIFT (14U) #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE2_LAST_PAGE_ALIGNSIZE (16384U) /* Register VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE3_LAST */ #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE3_LAST (0xE0D0U) #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE3_LAST_MASKFULL (IMG_UINT64_C(0x00000003FFFFC000)) #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE3_LAST_PAGE_SHIFT (14U) #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE3_LAST_PAGE_CLRMSK (IMG_UINT64_C(0XFFFFFFFC00003FFF)) #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE3_LAST_PAGE_ALIGNSHIFT (14U) #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE3_LAST_PAGE_ALIGNSIZE (16384U) /* Register VHA_CR_MMU_PM_CAT_BASE_ALIST0_LAST */ #define VHA_CR_MMU_PM_CAT_BASE_ALIST0_LAST (0xE0D8U) #define VHA_CR_MMU_PM_CAT_BASE_ALIST0_LAST_MASKFULL (IMG_UINT64_C(0x00000003FFFFC000)) #define VHA_CR_MMU_PM_CAT_BASE_ALIST0_LAST_PAGE_SHIFT (14U) #define VHA_CR_MMU_PM_CAT_BASE_ALIST0_LAST_PAGE_CLRMSK (IMG_UINT64_C(0XFFFFFFFC00003FFF)) #define VHA_CR_MMU_PM_CAT_BASE_ALIST0_LAST_PAGE_ALIGNSHIFT (14U) #define VHA_CR_MMU_PM_CAT_BASE_ALIST0_LAST_PAGE_ALIGNSIZE (16384U) /* Register VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE0_LAST */ #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE0_LAST (0xE0E0U) #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE0_LAST_MASKFULL (IMG_UINT64_C(0x00000003FFFFC000)) #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE0_LAST_PAGE_SHIFT (14U) #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE0_LAST_PAGE_CLRMSK (IMG_UINT64_C(0XFFFFFFFC00003FFF)) #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE0_LAST_PAGE_ALIGNSHIFT (14U) #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE0_LAST_PAGE_ALIGNSIZE (16384U) /* Register VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE1_LAST */ #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE1_LAST (0xE0E8U) #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE1_LAST_MASKFULL (IMG_UINT64_C(0x00000003FFFFC000)) #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE1_LAST_PAGE_SHIFT (14U) #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE1_LAST_PAGE_CLRMSK (IMG_UINT64_C(0XFFFFFFFC00003FFF)) #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE1_LAST_PAGE_ALIGNSHIFT (14U) #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE1_LAST_PAGE_ALIGNSIZE (16384U) /* Register VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE2_LAST */ #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE2_LAST (0xE0F0U) #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE2_LAST_MASKFULL (IMG_UINT64_C(0x00000003FFFFC000)) #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE2_LAST_PAGE_SHIFT (14U) #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE2_LAST_PAGE_CLRMSK (IMG_UINT64_C(0XFFFFFFFC00003FFF)) #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE2_LAST_PAGE_ALIGNSHIFT (14U) #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE2_LAST_PAGE_ALIGNSIZE (16384U) /* Register VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE3_LAST */ #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE3_LAST (0xE0F8U) #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE3_LAST_MASKFULL (IMG_UINT64_C(0x00000003FFFFC000)) #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE3_LAST_PAGE_SHIFT (14U) #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE3_LAST_PAGE_CLRMSK (IMG_UINT64_C(0XFFFFFFFC00003FFF)) #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE3_LAST_PAGE_ALIGNSHIFT (14U) #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE3_LAST_PAGE_ALIGNSIZE (16384U) /* Register VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE0_LAST */ #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE0_LAST (0xE100U) #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE0_LAST_MASKFULL (IMG_UINT64_C(0x00000003FFFFC000)) #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE0_LAST_PAGE_SHIFT (14U) #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE0_LAST_PAGE_CLRMSK (IMG_UINT64_C(0XFFFFFFFC00003FFF)) #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE0_LAST_PAGE_ALIGNSHIFT (14U) #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE0_LAST_PAGE_ALIGNSIZE (16384U) /* Register VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE1_LAST */ #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE1_LAST (0xE108U) #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE1_LAST_MASKFULL (IMG_UINT64_C(0x00000003FFFFC000)) #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE1_LAST_PAGE_SHIFT (14U) #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE1_LAST_PAGE_CLRMSK (IMG_UINT64_C(0XFFFFFFFC00003FFF)) #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE1_LAST_PAGE_ALIGNSHIFT (14U) #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE1_LAST_PAGE_ALIGNSIZE (16384U) /* Register VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE2_LAST */ #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE2_LAST (0xE110U) #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE2_LAST_MASKFULL (IMG_UINT64_C(0x00000003FFFFC000)) #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE2_LAST_PAGE_SHIFT (14U) #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE2_LAST_PAGE_CLRMSK (IMG_UINT64_C(0XFFFFFFFC00003FFF)) #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE2_LAST_PAGE_ALIGNSHIFT (14U) #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE2_LAST_PAGE_ALIGNSIZE (16384U) /* Register VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE3_LAST */ #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE3_LAST (0xE118U) #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE3_LAST_MASKFULL (IMG_UINT64_C(0x00000003FFFFC000)) #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE3_LAST_PAGE_SHIFT (14U) #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE3_LAST_PAGE_CLRMSK (IMG_UINT64_C(0XFFFFFFFC00003FFF)) #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE3_LAST_PAGE_ALIGNSHIFT (14U) #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE3_LAST_PAGE_ALIGNSIZE (16384U) /* Register VHA_CR_MMU_PM_CAT_BASE_ALIST1_LAST */ #define VHA_CR_MMU_PM_CAT_BASE_ALIST1_LAST (0xE120U) #define VHA_CR_MMU_PM_CAT_BASE_ALIST1_LAST_MASKFULL (IMG_UINT64_C(0x00000003FFFFC000)) #define VHA_CR_MMU_PM_CAT_BASE_ALIST1_LAST_PAGE_SHIFT (14U) #define VHA_CR_MMU_PM_CAT_BASE_ALIST1_LAST_PAGE_CLRMSK (IMG_UINT64_C(0XFFFFFFFC00003FFF)) #define VHA_CR_MMU_PM_CAT_BASE_ALIST1_LAST_PAGE_ALIGNSHIFT (14U) #define VHA_CR_MMU_PM_CAT_BASE_ALIST1_LAST_PAGE_ALIGNSIZE (16384U) /* Register VHA_CR_OS0_MMU_CTRL_INVAL */ #define VHA_CR_OS0_MMU_CTRL_INVAL (0xE138U) #define VHA_CR_OS0_MMU_CTRL_INVAL_MASKFULL (IMG_UINT64_C(0x0000000000000FFF)) #define VHA_CR_OS0_MMU_CTRL_INVAL_ALL_CONTEXTS_SHIFT (11U) #define VHA_CR_OS0_MMU_CTRL_INVAL_ALL_CONTEXTS_CLRMSK (0XFFFFF7FFU) #define VHA_CR_OS0_MMU_CTRL_INVAL_ALL_CONTEXTS_EN (0X00000800U) #define VHA_CR_OS0_MMU_CTRL_INVAL_CONTEXT_SHIFT (3U) #define VHA_CR_OS0_MMU_CTRL_INVAL_CONTEXT_CLRMSK (0XFFFFF807U) #define VHA_CR_OS0_MMU_CTRL_INVAL_PC_SHIFT (2U) #define VHA_CR_OS0_MMU_CTRL_INVAL_PC_CLRMSK (0XFFFFFFFBU) #define VHA_CR_OS0_MMU_CTRL_INVAL_PC_EN (0X00000004U) #define VHA_CR_OS0_MMU_CTRL_INVAL_PD_SHIFT (1U) #define VHA_CR_OS0_MMU_CTRL_INVAL_PD_CLRMSK (0XFFFFFFFDU) #define VHA_CR_OS0_MMU_CTRL_INVAL_PD_EN (0X00000002U) #define VHA_CR_OS0_MMU_CTRL_INVAL_PT_SHIFT (0U) #define VHA_CR_OS0_MMU_CTRL_INVAL_PT_CLRMSK (0XFFFFFFFEU) #define VHA_CR_OS0_MMU_CTRL_INVAL_PT_EN (0X00000001U) /* Register VHA_CR_OS0_MMU_CBASE_MAPPING_CONTEXT */ #define VHA_CR_OS0_MMU_CBASE_MAPPING_CONTEXT (0xE140U) #define VHA_CR_OS0_MMU_CBASE_MAPPING_CONTEXT_MASKFULL (IMG_UINT64_C(0x00000000000000FF)) #define VHA_CR_OS0_MMU_CBASE_MAPPING_CONTEXT_ID_SHIFT (0U) #define VHA_CR_OS0_MMU_CBASE_MAPPING_CONTEXT_ID_CLRMSK (0XFFFFFF00U) /* Register VHA_CR_OS0_MMU_CBASE_MAPPING */ #define VHA_CR_OS0_MMU_CBASE_MAPPING (0xE148U) #define VHA_CR_OS0_MMU_CBASE_MAPPING_MASKFULL (IMG_UINT64_C(0x000000001FFFFFFF)) #define VHA_CR_OS0_MMU_CBASE_MAPPING_INVALID_SHIFT (28U) #define VHA_CR_OS0_MMU_CBASE_MAPPING_INVALID_CLRMSK (0XEFFFFFFFU) #define VHA_CR_OS0_MMU_CBASE_MAPPING_INVALID_EN (0X10000000U) #define VHA_CR_OS0_MMU_CBASE_MAPPING_BASE_ADDR_SHIFT (0U) #define VHA_CR_OS0_MMU_CBASE_MAPPING_BASE_ADDR_CLRMSK (0XF0000000U) #define VHA_CR_OS0_MMU_CBASE_MAPPING_BASE_ADDR_ALIGNSHIFT (12U) #define VHA_CR_OS0_MMU_CBASE_MAPPING_BASE_ADDR_ALIGNSIZE (4096U) /* Register VHA_CR_OS0_MMU_FAULT_STATUS1 */ #define VHA_CR_OS0_MMU_FAULT_STATUS1 (0xE150U) #define VHA_CR_OS0_MMU_FAULT_STATUS1_MASKFULL (IMG_UINT64_C(0xFFFFFFFFFFFFFFFF)) #define VHA_CR_OS0_MMU_FAULT_STATUS1_LEVEL_SHIFT (62U) #define VHA_CR_OS0_MMU_FAULT_STATUS1_LEVEL_CLRMSK (IMG_UINT64_C(0X3FFFFFFFFFFFFFFF)) #define VHA_CR_OS0_MMU_FAULT_STATUS1_REQ_ID_SHIFT (56U) #define VHA_CR_OS0_MMU_FAULT_STATUS1_REQ_ID_CLRMSK (IMG_UINT64_C(0XC0FFFFFFFFFFFFFF)) #define VHA_CR_OS0_MMU_FAULT_STATUS1_CONTEXT_SHIFT (48U) #define VHA_CR_OS0_MMU_FAULT_STATUS1_CONTEXT_CLRMSK (IMG_UINT64_C(0XFF00FFFFFFFFFFFF)) #define VHA_CR_OS0_MMU_FAULT_STATUS1_ADDRESS_SHIFT (4U) #define VHA_CR_OS0_MMU_FAULT_STATUS1_ADDRESS_CLRMSK (IMG_UINT64_C(0XFFFF00000000000F)) #define VHA_CR_OS0_MMU_FAULT_STATUS1_RNW_SHIFT (3U) #define VHA_CR_OS0_MMU_FAULT_STATUS1_RNW_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFF7)) #define VHA_CR_OS0_MMU_FAULT_STATUS1_RNW_EN (IMG_UINT64_C(0X0000000000000008)) #define VHA_CR_OS0_MMU_FAULT_STATUS1_TYPE_SHIFT (1U) #define VHA_CR_OS0_MMU_FAULT_STATUS1_TYPE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFF9)) #define VHA_CR_OS0_MMU_FAULT_STATUS1_FAULT_SHIFT (0U) #define VHA_CR_OS0_MMU_FAULT_STATUS1_FAULT_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFE)) #define VHA_CR_OS0_MMU_FAULT_STATUS1_FAULT_EN (IMG_UINT64_C(0X0000000000000001)) /* Register VHA_CR_OS0_MMU_FAULT_STATUS2 */ #define VHA_CR_OS0_MMU_FAULT_STATUS2 (0xE158U) #define VHA_CR_OS0_MMU_FAULT_STATUS2_MASKFULL (IMG_UINT64_C(0x000000003FFF07FF)) #define VHA_CR_OS0_MMU_FAULT_STATUS2_WRITEBACK_SHIFT (29U) #define VHA_CR_OS0_MMU_FAULT_STATUS2_WRITEBACK_CLRMSK (0XDFFFFFFFU) #define VHA_CR_OS0_MMU_FAULT_STATUS2_WRITEBACK_EN (0X20000000U) #define VHA_CR_OS0_MMU_FAULT_STATUS2_CLEANUNIQUE_SHIFT (28U) #define VHA_CR_OS0_MMU_FAULT_STATUS2_CLEANUNIQUE_CLRMSK (0XEFFFFFFFU) #define VHA_CR_OS0_MMU_FAULT_STATUS2_CLEANUNIQUE_EN (0X10000000U) #define VHA_CR_OS0_MMU_FAULT_STATUS2_BANK_SHIFT (24U) #define VHA_CR_OS0_MMU_FAULT_STATUS2_BANK_CLRMSK (0XF0FFFFFFU) #define VHA_CR_OS0_MMU_FAULT_STATUS2_TLB_ENTRY_SHIFT (16U) #define VHA_CR_OS0_MMU_FAULT_STATUS2_TLB_ENTRY_CLRMSK (0XFF00FFFFU) #define VHA_CR_OS0_MMU_FAULT_STATUS2_FBM_FAULT_SHIFT (10U) #define VHA_CR_OS0_MMU_FAULT_STATUS2_FBM_FAULT_CLRMSK (0XFFFFFBFFU) #define VHA_CR_OS0_MMU_FAULT_STATUS2_FBM_FAULT_EN (0X00000400U) #define VHA_CR_OS0_MMU_FAULT_STATUS2_BIF_ID_SHIFT (0U) #define VHA_CR_OS0_MMU_FAULT_STATUS2_BIF_ID_CLRMSK (0XFFFFFC00U) /* Register VHA_CR_MMU_FAULT_STATUS_META */ #define VHA_CR_MMU_FAULT_STATUS_META (0xE160U) #define VHA_CR_MMU_FAULT_STATUS_META_MASKFULL (IMG_UINT64_C(0xFFFFFFFFFFFFFFFF)) #define VHA_CR_MMU_FAULT_STATUS_META_LEVEL_SHIFT (62U) #define VHA_CR_MMU_FAULT_STATUS_META_LEVEL_CLRMSK (IMG_UINT64_C(0X3FFFFFFFFFFFFFFF)) #define VHA_CR_MMU_FAULT_STATUS_META_REQ_ID_SHIFT (56U) #define VHA_CR_MMU_FAULT_STATUS_META_REQ_ID_CLRMSK (IMG_UINT64_C(0XC0FFFFFFFFFFFFFF)) #define VHA_CR_MMU_FAULT_STATUS_META_CONTEXT_SHIFT (48U) #define VHA_CR_MMU_FAULT_STATUS_META_CONTEXT_CLRMSK (IMG_UINT64_C(0XFF00FFFFFFFFFFFF)) #define VHA_CR_MMU_FAULT_STATUS_META_ADDRESS_SHIFT (4U) #define VHA_CR_MMU_FAULT_STATUS_META_ADDRESS_CLRMSK (IMG_UINT64_C(0XFFFF00000000000F)) #define VHA_CR_MMU_FAULT_STATUS_META_RNW_SHIFT (3U) #define VHA_CR_MMU_FAULT_STATUS_META_RNW_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFF7)) #define VHA_CR_MMU_FAULT_STATUS_META_RNW_EN (IMG_UINT64_C(0X0000000000000008)) #define VHA_CR_MMU_FAULT_STATUS_META_TYPE_SHIFT (1U) #define VHA_CR_MMU_FAULT_STATUS_META_TYPE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFF9)) #define VHA_CR_MMU_FAULT_STATUS_META_FAULT_SHIFT (0U) #define VHA_CR_MMU_FAULT_STATUS_META_FAULT_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFE)) #define VHA_CR_MMU_FAULT_STATUS_META_FAULT_EN (IMG_UINT64_C(0X0000000000000001)) /* Register VHA_CR_MMU_FAULT_STATUS2_META */ #define VHA_CR_MMU_FAULT_STATUS2_META (0xE198U) #define VHA_CR_MMU_FAULT_STATUS2_META_MASKFULL (IMG_UINT64_C(0x0000000000003FFF)) #define VHA_CR_MMU_FAULT_STATUS2_META_WRITEBACK_SHIFT (13U) #define VHA_CR_MMU_FAULT_STATUS2_META_WRITEBACK_CLRMSK (0XFFFFDFFFU) #define VHA_CR_MMU_FAULT_STATUS2_META_WRITEBACK_EN (0X00002000U) #define VHA_CR_MMU_FAULT_STATUS2_META_CLEANUNIQUE_SHIFT (12U) #define VHA_CR_MMU_FAULT_STATUS2_META_CLEANUNIQUE_CLRMSK (0XFFFFEFFFU) #define VHA_CR_MMU_FAULT_STATUS2_META_CLEANUNIQUE_EN (0X00001000U) #define VHA_CR_MMU_FAULT_STATUS2_META_BANK_SHIFT (8U) #define VHA_CR_MMU_FAULT_STATUS2_META_BANK_CLRMSK (0XFFFFF0FFU) #define VHA_CR_MMU_FAULT_STATUS2_META_TLB_ENTRY_SHIFT (0U) #define VHA_CR_MMU_FAULT_STATUS2_META_TLB_ENTRY_CLRMSK (0XFFFFFF00U) /* Register VHA_CR_MMU_FAULT_STATUS_PM */ #define VHA_CR_MMU_FAULT_STATUS_PM (0xE130U) #define VHA_CR_MMU_FAULT_STATUS_PM_MASKFULL (IMG_UINT64_C(0x0000000007FFFFFF)) #define VHA_CR_MMU_FAULT_STATUS_PM_DM_SHIFT (24U) #define VHA_CR_MMU_FAULT_STATUS_PM_DM_CLRMSK (IMG_UINT64_C(0XFFFFFFFFF8FFFFFF)) #define VHA_CR_MMU_FAULT_STATUS_PM_RNW_SHIFT (23U) #define VHA_CR_MMU_FAULT_STATUS_PM_RNW_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFF7FFFFF)) #define VHA_CR_MMU_FAULT_STATUS_PM_RNW_EN (IMG_UINT64_C(0X0000000000800000)) #define VHA_CR_MMU_FAULT_STATUS_PM_ADDRESS_SHIFT (3U) #define VHA_CR_MMU_FAULT_STATUS_PM_ADDRESS_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFF800007)) #define VHA_CR_MMU_FAULT_STATUS_PM_LEVEL_SHIFT (1U) #define VHA_CR_MMU_FAULT_STATUS_PM_LEVEL_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFF9)) #define VHA_CR_MMU_FAULT_STATUS_PM_FAULT_SHIFT (0U) #define VHA_CR_MMU_FAULT_STATUS_PM_FAULT_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFE)) #define VHA_CR_MMU_FAULT_STATUS_PM_FAULT_EN (IMG_UINT64_C(0X0000000000000001)) /* Register VHA_CR_MMU_FAULT_ACCESS */ #define VHA_CR_MMU_FAULT_ACCESS (0xE168U) #define VHA_CR_MMU_FAULT_ACCESS_MASKFULL (IMG_UINT64_C(0x000000FFFFFFF000)) #define VHA_CR_MMU_FAULT_ACCESS_ADDRESS_SHIFT (12U) #define VHA_CR_MMU_FAULT_ACCESS_ADDRESS_CLRMSK (IMG_UINT64_C(0XFFFFFF0000000FFF)) #define VHA_CR_MMU_FAULT_ACCESS_ADDRESS_ALIGNSHIFT (12U) #define VHA_CR_MMU_FAULT_ACCESS_ADDRESS_ALIGNSIZE (4096U) /* Register VHA_CR_MMU_STATUS */ #define VHA_CR_MMU_STATUS (0xE170U) #define VHA_CR_MMU_STATUS_MASKFULL (IMG_UINT64_C(0x000001FFFFFFFFFF)) #define VHA_CR_MMU_STATUS_MMU_STALLED_SHIFT (40U) #define VHA_CR_MMU_STATUS_MMU_STALLED_CLRMSK (IMG_UINT64_C(0XFFFFFEFFFFFFFFFF)) #define VHA_CR_MMU_STATUS_MMU_STALLED_EN (IMG_UINT64_C(0X0000010000000000)) #define VHA_CR_MMU_STATUS_PM_WRITES_SHIFT (38U) #define VHA_CR_MMU_STATUS_PM_WRITES_CLRMSK (IMG_UINT64_C(0XFFFFFF3FFFFFFFFF)) #define VHA_CR_MMU_STATUS_PM_READS_SHIFT (36U) #define VHA_CR_MMU_STATUS_PM_READS_CLRMSK (IMG_UINT64_C(0XFFFFFFCFFFFFFFFF)) #define VHA_CR_MMU_STATUS_PC_READS_SHIFT (24U) #define VHA_CR_MMU_STATUS_PC_READS_CLRMSK (IMG_UINT64_C(0XFFFFFFF000FFFFFF)) #define VHA_CR_MMU_STATUS_PD_READS_SHIFT (12U) #define VHA_CR_MMU_STATUS_PD_READS_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFF000FFF)) #define VHA_CR_MMU_STATUS_PT_READS_SHIFT (0U) #define VHA_CR_MMU_STATUS_PT_READS_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFF000)) /* Register VHA_CR_OS0_MMU_ENTRY_STATUS */ #define VHA_CR_OS0_MMU_ENTRY_STATUS (0xE178U) #define VHA_CR_OS0_MMU_ENTRY_STATUS_MASKFULL (IMG_UINT64_C(0x000000FFFFFF80FF)) #define VHA_CR_OS0_MMU_ENTRY_STATUS_ADDRESS_SHIFT (15U) #define VHA_CR_OS0_MMU_ENTRY_STATUS_ADDRESS_CLRMSK (IMG_UINT64_C(0XFFFFFF0000007FFF)) #define VHA_CR_OS0_MMU_ENTRY_STATUS_CONTEXT_ID_SHIFT (0U) #define VHA_CR_OS0_MMU_ENTRY_STATUS_CONTEXT_ID_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFF00)) /* Register VHA_CR_OS0_MMU_ENTRY */ #define VHA_CR_OS0_MMU_ENTRY (0xE180U) #define VHA_CR_OS0_MMU_ENTRY_MASKFULL (IMG_UINT64_C(0x0000000000000003)) #define VHA_CR_OS0_MMU_ENTRY_ENABLE_SHIFT (1U) #define VHA_CR_OS0_MMU_ENTRY_ENABLE_CLRMSK (0XFFFFFFFDU) #define VHA_CR_OS0_MMU_ENTRY_ENABLE_EN (0X00000002U) #define VHA_CR_OS0_MMU_ENTRY_PENDING_SHIFT (0U) #define VHA_CR_OS0_MMU_ENTRY_PENDING_CLRMSK (0XFFFFFFFEU) #define VHA_CR_OS0_MMU_ENTRY_PENDING_EN (0X00000001U) /* Register VHA_CR_MMU_ABORT_PM_CTRL */ #define VHA_CR_MMU_ABORT_PM_CTRL (0xE188U) #define VHA_CR_MMU_ABORT_PM_CTRL_MASKFULL (IMG_UINT64_C(0x0000000000000001)) #define VHA_CR_MMU_ABORT_PM_CTRL_ENABLE_SHIFT (0U) #define VHA_CR_MMU_ABORT_PM_CTRL_ENABLE_CLRMSK (0XFFFFFFFEU) #define VHA_CR_MMU_ABORT_PM_CTRL_ENABLE_EN (0X00000001U) /* Register VHA_CR_MMU_ABORT_PM_STATUS */ #define VHA_CR_MMU_ABORT_PM_STATUS (0xE190U) #define VHA_CR_MMU_ABORT_PM_STATUS_MASKFULL (IMG_UINT64_C(0x0000000000000001)) #define VHA_CR_MMU_ABORT_PM_STATUS_ABORT_SHIFT (0U) #define VHA_CR_MMU_ABORT_PM_STATUS_ABORT_CLRMSK (0XFFFFFFFEU) #define VHA_CR_MMU_ABORT_PM_STATUS_ABORT_EN (0X00000001U) /* Register VHA_CR_OS0_MMU_CTRL */ #define VHA_CR_OS0_MMU_CTRL (0xE1A8U) #define VHA_CR_OS0_MMU_CTRL_MASKFULL (IMG_UINT64_C(0x0000000000000001)) #define VHA_CR_OS0_MMU_CTRL_BYPASS_SHIFT (0U) #define VHA_CR_OS0_MMU_CTRL_BYPASS_CLRMSK (0XFFFFFFFEU) #define VHA_CR_OS0_MMU_CTRL_BYPASS_EN (0X00000001U) #define VHA_CR_SLC_CTRL_ENUM_HASH_MODE_MASK (0x00000003U) /* Reserved value */ #define VHA_CR_SLC_CTRL_ENUM_HASH_MODE_RESERVED (0x00000000U) /* Addresses interleaved between Cache Bank using a combined Set & Bank hash of the upper address bits */ #define VHA_CR_SLC_CTRL_ENUM_HASH_MODE_PVR_V3_HASHING (0x00000001U) /* Addresses are interleaved between Cache Banks on a Cacheline boundary */ #define VHA_CR_SLC_CTRL_ENUM_HASH_MODE_LINEAR (0x00000002U) /* Addresses interleaved between Cache Banks using an XOR hash of the address bits below the 4KB page granularity */ #define VHA_CR_SLC_CTRL_ENUM_HASH_MODE_IN_PAGE_HASH (0x00000003U) /* Register VHA_CR_SLC_CTRL */ #define VHA_CR_SLC_CTRL (0xE200U) #define VHA_CR_SLC_CTRL_MASKFULL (IMG_UINT64_C(0x0000000000001FF3)) #define VHA_CR_SLC_CTRL_CFI_TIMEOUT_ENABLE_SHIFT (12U) #define VHA_CR_SLC_CTRL_CFI_TIMEOUT_ENABLE_CLRMSK (0XFFFFEFFFU) #define VHA_CR_SLC_CTRL_CFI_TIMEOUT_ENABLE_EN (0X00001000U) #define VHA_CR_SLC_CTRL_CFI_TIMEOUT_CYCLES_SHIFT (8U) #define VHA_CR_SLC_CTRL_CFI_TIMEOUT_CYCLES_CLRMSK (0XFFFFF0FFU) #define VHA_CR_SLC_CTRL_PERSISTENCE_DECAY_ENABLE_SHIFT (7U) #define VHA_CR_SLC_CTRL_PERSISTENCE_DECAY_ENABLE_CLRMSK (0XFFFFFF7FU) #define VHA_CR_SLC_CTRL_PERSISTENCE_DECAY_ENABLE_EN (0X00000080U) #define VHA_CR_SLC_CTRL_MAX_FENCES_SHIFT (4U) #define VHA_CR_SLC_CTRL_MAX_FENCES_CLRMSK (0XFFFFFF8FU) #define VHA_CR_SLC_CTRL_HASH_MODE_SHIFT (0U) #define VHA_CR_SLC_CTRL_HASH_MODE_CLRMSK (0XFFFFFFFCU) #define VHA_CR_SLC_CTRL_HASH_MODE_RESERVED (00000000U) #define VHA_CR_SLC_CTRL_HASH_MODE_PVR_V3_HASHING (0X00000001U) #define VHA_CR_SLC_CTRL_HASH_MODE_LINEAR (0X00000002U) #define VHA_CR_SLC_CTRL_HASH_MODE_IN_PAGE_HASH (0X00000003U) /* Register VHA_CR_SLC_STATUS1 */ #define VHA_CR_SLC_STATUS1 (0xE210U) #define VHA_CR_SLC_STATUS1_MASKFULL (IMG_UINT64_C(0xFFFFFFFFFFFFFFFF)) #define VHA_CR_SLC_STATUS1_XBAR_CFI_TIMEOUTS_SHIFT (48U) #define VHA_CR_SLC_STATUS1_XBAR_CFI_TIMEOUTS_CLRMSK (IMG_UINT64_C(0X0000FFFFFFFFFFFF)) #define VHA_CR_SLC_STATUS1_BUS1_OUTSTANDING_WRITES_SHIFT (36U) #define VHA_CR_SLC_STATUS1_BUS1_OUTSTANDING_WRITES_CLRMSK (IMG_UINT64_C(0XFFFF000FFFFFFFFF)) #define VHA_CR_SLC_STATUS1_BUS0_OUTSTANDING_WRITES_SHIFT (24U) #define VHA_CR_SLC_STATUS1_BUS0_OUTSTANDING_WRITES_CLRMSK (IMG_UINT64_C(0XFFFFFFF000FFFFFF)) #define VHA_CR_SLC_STATUS1_BUS1_OUTSTANDING_READS_SHIFT (12U) #define VHA_CR_SLC_STATUS1_BUS1_OUTSTANDING_READS_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFF000FFF)) #define VHA_CR_SLC_STATUS1_BUS0_OUTSTANDING_READS_SHIFT (0U) #define VHA_CR_SLC_STATUS1_BUS0_OUTSTANDING_READS_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFF000)) /* Register VHA_CR_SLC_STATUS2 */ #define VHA_CR_SLC_STATUS2 (0xE218U) #define VHA_CR_SLC_STATUS2_MASKFULL (IMG_UINT64_C(0x0000FFFFFFFFFFFF)) #define VHA_CR_SLC_STATUS2_BUS3_OUTSTANDING_WRITES_SHIFT (36U) #define VHA_CR_SLC_STATUS2_BUS3_OUTSTANDING_WRITES_CLRMSK (IMG_UINT64_C(0XFFFF000FFFFFFFFF)) #define VHA_CR_SLC_STATUS2_BUS2_OUTSTANDING_WRITES_SHIFT (24U) #define VHA_CR_SLC_STATUS2_BUS2_OUTSTANDING_WRITES_CLRMSK (IMG_UINT64_C(0XFFFFFFF000FFFFFF)) #define VHA_CR_SLC_STATUS2_BUS3_OUTSTANDING_READS_SHIFT (12U) #define VHA_CR_SLC_STATUS2_BUS3_OUTSTANDING_READS_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFF000FFF)) #define VHA_CR_SLC_STATUS2_BUS2_OUTSTANDING_READS_SHIFT (0U) #define VHA_CR_SLC_STATUS2_BUS2_OUTSTANDING_READS_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFF000)) /* Register VHA_CR_SLC_STATUS_BYP_COH_ERROR_READS */ #define VHA_CR_SLC_STATUS_BYP_COH_ERROR_READS (0xE220U) #define VHA_CR_SLC_STATUS_BYP_COH_ERROR_READS_MASKFULL (IMG_UINT64_C(0xFFFFFFFFFFFFFFFF)) #define VHA_CR_SLC_STATUS_BYP_COH_ERROR_READS_BANK3_SHIFT (48U) #define VHA_CR_SLC_STATUS_BYP_COH_ERROR_READS_BANK3_CLRMSK (IMG_UINT64_C(0X0000FFFFFFFFFFFF)) #define VHA_CR_SLC_STATUS_BYP_COH_ERROR_READS_BANK2_SHIFT (32U) #define VHA_CR_SLC_STATUS_BYP_COH_ERROR_READS_BANK2_CLRMSK (IMG_UINT64_C(0XFFFF0000FFFFFFFF)) #define VHA_CR_SLC_STATUS_BYP_COH_ERROR_READS_BANK1_SHIFT (16U) #define VHA_CR_SLC_STATUS_BYP_COH_ERROR_READS_BANK1_CLRMSK (IMG_UINT64_C(0XFFFFFFFF0000FFFF)) #define VHA_CR_SLC_STATUS_BYP_COH_ERROR_READS_BANK0_SHIFT (0U) #define VHA_CR_SLC_STATUS_BYP_COH_ERROR_READS_BANK0_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFF0000)) /* Register VHA_CR_SLC_STATUS_BYP_COH_ERROR_WRITES */ #define VHA_CR_SLC_STATUS_BYP_COH_ERROR_WRITES (0xE228U) #define VHA_CR_SLC_STATUS_BYP_COH_ERROR_WRITES_MASKFULL (IMG_UINT64_C(0xFFFFFFFFFFFFFFFF)) #define VHA_CR_SLC_STATUS_BYP_COH_ERROR_WRITES_BANK3_SHIFT (48U) #define VHA_CR_SLC_STATUS_BYP_COH_ERROR_WRITES_BANK3_CLRMSK (IMG_UINT64_C(0X0000FFFFFFFFFFFF)) #define VHA_CR_SLC_STATUS_BYP_COH_ERROR_WRITES_BANK2_SHIFT (32U) #define VHA_CR_SLC_STATUS_BYP_COH_ERROR_WRITES_BANK2_CLRMSK (IMG_UINT64_C(0XFFFF0000FFFFFFFF)) #define VHA_CR_SLC_STATUS_BYP_COH_ERROR_WRITES_BANK1_SHIFT (16U) #define VHA_CR_SLC_STATUS_BYP_COH_ERROR_WRITES_BANK1_CLRMSK (IMG_UINT64_C(0XFFFFFFFF0000FFFF)) #define VHA_CR_SLC_STATUS_BYP_COH_ERROR_WRITES_BANK0_SHIFT (0U) #define VHA_CR_SLC_STATUS_BYP_COH_ERROR_WRITES_BANK0_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFF0000)) /* Register VHA_CR_SLC_IDLE */ #define VHA_CR_SLC_IDLE (0xE230U) #define VHA_CR_SLC_IDLE_MASKFULL (IMG_UINT64_C(0x000000000000FFFF)) #define VHA_CR_SLC_IDLE_ACE_CONVERTERS_SHIFT (12U) #define VHA_CR_SLC_IDLE_ACE_CONVERTERS_CLRMSK (0XFFFF0FFFU) #define VHA_CR_SLC_IDLE_CACHE_BANKS_SHIFT (4U) #define VHA_CR_SLC_IDLE_CACHE_BANKS_CLRMSK (0XFFFFF00FU) #define VHA_CR_SLC_IDLE_MMU_SHIFT (3U) #define VHA_CR_SLC_IDLE_MMU_CLRMSK (0XFFFFFFF7U) #define VHA_CR_SLC_IDLE_MMU_EN (0X00000008U) #define VHA_CR_SLC_IDLE_CCM_SHIFT (2U) #define VHA_CR_SLC_IDLE_CCM_CLRMSK (0XFFFFFFFBU) #define VHA_CR_SLC_IDLE_CCM_EN (0X00000004U) #define VHA_CR_SLC_IDLE_RDI_SHIFT (1U) #define VHA_CR_SLC_IDLE_RDI_CLRMSK (0XFFFFFFFDU) #define VHA_CR_SLC_IDLE_RDI_EN (0X00000002U) #define VHA_CR_SLC_IDLE_XBAR_SHIFT (0U) #define VHA_CR_SLC_IDLE_XBAR_CLRMSK (0XFFFFFFFEU) #define VHA_CR_SLC_IDLE_XBAR_EN (0X00000001U) /* Register VHA_CR_SLC_STATUS3 */ #define VHA_CR_SLC_STATUS3 (0xE238U) #define VHA_CR_SLC_STATUS3_MASKFULL (IMG_UINT64_C(0x0FFFFFFFFFFFFFFF)) #define VHA_CR_SLC_STATUS3_MAX_CRITICAL_QOS_READ_LATENCY_SHIFT (50U) #define VHA_CR_SLC_STATUS3_MAX_CRITICAL_QOS_READ_LATENCY_CLRMSK (IMG_UINT64_C(0XF003FFFFFFFFFFFF)) #define VHA_CR_SLC_STATUS3_MAX_LOW_QOS_READ_LATENCY_SHIFT (40U) #define VHA_CR_SLC_STATUS3_MAX_LOW_QOS_READ_LATENCY_CLRMSK (IMG_UINT64_C(0XFFFC00FFFFFFFFFF)) #define VHA_CR_SLC_STATUS3_AVG_CRITICAL_QOS_READ_LATENCY_SHIFT (30U) #define VHA_CR_SLC_STATUS3_AVG_CRITICAL_QOS_READ_LATENCY_CLRMSK (IMG_UINT64_C(0XFFFFFF003FFFFFFF)) #define VHA_CR_SLC_STATUS3_AVG_LOW_QOS_READ_LATENCY_SHIFT (20U) #define VHA_CR_SLC_STATUS3_AVG_LOW_QOS_READ_LATENCY_CLRMSK (IMG_UINT64_C(0XFFFFFFFFC00FFFFF)) #define VHA_CR_SLC_STATUS3_MIN_CRITICAL_QOS_READ_LATENCY_SHIFT (10U) #define VHA_CR_SLC_STATUS3_MIN_CRITICAL_QOS_READ_LATENCY_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFF003FF)) #define VHA_CR_SLC_STATUS3_MIN_LOW_QOS_READ_LATENCY_SHIFT (0U) #define VHA_CR_SLC_STATUS3_MIN_LOW_QOS_READ_LATENCY_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFC00)) /* Register VHA_CR_SLC_FAULT_STOP_STATUS */ #define VHA_CR_SLC_FAULT_STOP_STATUS (0xE240U) #define VHA_CR_SLC_FAULT_STOP_STATUS_MASKFULL (IMG_UINT64_C(0x000000000001FFFF)) #define VHA_CR_SLC_FAULT_STOP_STATUS_BIF_SHIFT (0U) #define VHA_CR_SLC_FAULT_STOP_STATUS_BIF_CLRMSK (0XFFFE0000U) /* Register VHA_CR_SLC_FAULT_STOP_CTRL */ #define VHA_CR_SLC_FAULT_STOP_CTRL (0xE248U) #define VHA_CR_SLC_FAULT_STOP_CTRL_MASKFULL (IMG_UINT64_C(0x000000000003FFFF)) #define VHA_CR_SLC_FAULT_STOP_CTRL_ALL_SHIFT (17U) #define VHA_CR_SLC_FAULT_STOP_CTRL_ALL_CLRMSK (0XFFFDFFFFU) #define VHA_CR_SLC_FAULT_STOP_CTRL_ALL_EN (0X00020000U) #define VHA_CR_SLC_FAULT_STOP_CTRL_ENABLE_SHIFT (0U) #define VHA_CR_SLC_FAULT_STOP_CTRL_ENABLE_CLRMSK (0XFFFE0000U) /* Register VHA_CR_SLC_STATUS_DEBUG */ #define VHA_CR_SLC_STATUS_DEBUG (0xE260U) #define VHA_CR_SLC_STATUS_DEBUG_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF)) #define VHA_CR_SLC_STATUS_DEBUG_ERR_COH_REQ_SHIFT (16U) #define VHA_CR_SLC_STATUS_DEBUG_ERR_COH_REQ_CLRMSK (0X0000FFFFU) #define VHA_CR_SLC_STATUS_DEBUG_ERR_ADDR_ALIAS_SHIFT (0U) #define VHA_CR_SLC_STATUS_DEBUG_ERR_ADDR_ALIAS_CLRMSK (0XFFFF0000U) /* Register VHA_CR_SLC_CCM_CTRL */ #define VHA_CR_SLC_CCM_CTRL (0xE300U) #define VHA_CR_SLC_CCM_CTRL_MASKFULL (IMG_UINT64_C(0x0000000000FF00FF)) #define VHA_CR_SLC_CCM_CTRL_SPILL_AMOUNT_SHIFT (16U) #define VHA_CR_SLC_CCM_CTRL_SPILL_AMOUNT_CLRMSK (0XFF00FFFFU) #define VHA_CR_SLC_CCM_CTRL_SPILL_THRESHOLD_SHIFT (0U) #define VHA_CR_SLC_CCM_CTRL_SPILL_THRESHOLD_CLRMSK (0XFFFFFF00U) /* Register VHA_CR_SLC_CCM_STATUS */ #define VHA_CR_SLC_CCM_STATUS (0xE308U) #define VHA_CR_SLC_CCM_STATUS_MASKFULL (IMG_UINT64_C(0x0FFFFFFFF10FF0FF)) #define VHA_CR_SLC_CCM_STATUS_SNOOP_COUNT3_SHIFT (52U) #define VHA_CR_SLC_CCM_STATUS_SNOOP_COUNT3_CLRMSK (IMG_UINT64_C(0XF00FFFFFFFFFFFFF)) #define VHA_CR_SLC_CCM_STATUS_SNOOP_COUNT2_SHIFT (44U) #define VHA_CR_SLC_CCM_STATUS_SNOOP_COUNT2_CLRMSK (IMG_UINT64_C(0XFFF00FFFFFFFFFFF)) #define VHA_CR_SLC_CCM_STATUS_SNOOP_COUNT1_SHIFT (36U) #define VHA_CR_SLC_CCM_STATUS_SNOOP_COUNT1_CLRMSK (IMG_UINT64_C(0XFFFFF00FFFFFFFFF)) #define VHA_CR_SLC_CCM_STATUS_SNOOP_COUNT0_SHIFT (28U) #define VHA_CR_SLC_CCM_STATUS_SNOOP_COUNT0_CLRMSK (IMG_UINT64_C(0XFFFFFFF00FFFFFFF)) #define VHA_CR_SLC_CCM_STATUS_SPILLING_SHIFT (24U) #define VHA_CR_SLC_CCM_STATUS_SPILLING_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFEFFFFFF)) #define VHA_CR_SLC_CCM_STATUS_SPILLING_EN (IMG_UINT64_C(0X0000000001000000)) #define VHA_CR_SLC_CCM_STATUS_SPILL_ENTRIES_SHIFT (12U) #define VHA_CR_SLC_CCM_STATUS_SPILL_ENTRIES_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFF00FFF)) #define VHA_CR_SLC_CCM_STATUS_ACTIVE_ENTRIES_SHIFT (0U) #define VHA_CR_SLC_CCM_STATUS_ACTIVE_ENTRIES_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFF00)) /* Register VHA_CR_ACE_QOS_CTRL */ #define VHA_CR_ACE_QOS_CTRL (0xE310U) #define VHA_CR_ACE_QOS_CTRL_MASKFULL (IMG_UINT64_C(0x000000000000FFFF)) #define VHA_CR_ACE_QOS_CTRL_CRITICAL_SHIFT (12U) #define VHA_CR_ACE_QOS_CTRL_CRITICAL_CLRMSK (0XFFFF0FFFU) #define VHA_CR_ACE_QOS_CTRL_HIGH_SHIFT (8U) #define VHA_CR_ACE_QOS_CTRL_HIGH_CLRMSK (0XFFFFF0FFU) #define VHA_CR_ACE_QOS_CTRL_MEDIUM_SHIFT (4U) #define VHA_CR_ACE_QOS_CTRL_MEDIUM_CLRMSK (0XFFFFFF0FU) #define VHA_CR_ACE_QOS_CTRL_LOW_SHIFT (0U) #define VHA_CR_ACE_QOS_CTRL_LOW_CLRMSK (0XFFFFFFF0U) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_ENUM_PRIORITIES_MASK (0x00000003U) /* Low */ #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_ENUM_PRIORITIES_LOW (0x00000000U) /* Medium */ #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_ENUM_PRIORITIES_MEDIUM (0x00000001U) /* High */ #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_ENUM_PRIORITIES_HIGH (0x00000002U) /* Critical */ #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_ENUM_PRIORITIES_CRITICAL (0x00000003U) /* Register VHA_CR_ACE_PRIORITY_MAPPING_CTRL */ #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL (0xE318U) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_MASKFULL (IMG_UINT64_C(0xFFFFFFFFFFFFFFFF)) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_MMU_SHIFT (62U) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_MMU_CLRMSK (IMG_UINT64_C(0X3FFFFFFFFFFFFFFF)) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_MMU_LOW (IMG_UINT64_C(0000000000000000)) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_MMU_MEDIUM (IMG_UINT64_C(0x4000000000000000)) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_MMU_HIGH (IMG_UINT64_C(0x8000000000000000)) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_MMU_CRITICAL (IMG_UINT64_C(0xc000000000000000)) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_UPS_SHIFT (60U) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_UPS_CLRMSK (IMG_UINT64_C(0XCFFFFFFFFFFFFFFF)) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_UPS_LOW (IMG_UINT64_C(0000000000000000)) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_UPS_MEDIUM (IMG_UINT64_C(0x1000000000000000)) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_UPS_HIGH (IMG_UINT64_C(0x2000000000000000)) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_UPS_CRITICAL (IMG_UINT64_C(0x3000000000000000)) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_FBM_BSC_SHIFT (58U) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_FBM_BSC_CLRMSK (IMG_UINT64_C(0XF3FFFFFFFFFFFFFF)) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_FBM_BSC_LOW (IMG_UINT64_C(0000000000000000)) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_FBM_BSC_MEDIUM (IMG_UINT64_C(0x0400000000000000)) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_FBM_BSC_HIGH (IMG_UINT64_C(0x0800000000000000)) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_FBM_BSC_CRITICAL (IMG_UINT64_C(0x0c00000000000000)) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_TUL_SHIFT (56U) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_TUL_CLRMSK (IMG_UINT64_C(0XFCFFFFFFFFFFFFFF)) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_TUL_LOW (IMG_UINT64_C(0000000000000000)) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_TUL_MEDIUM (IMG_UINT64_C(0x0100000000000000)) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_TUL_HIGH (IMG_UINT64_C(0x0200000000000000)) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_TUL_CRITICAL (IMG_UINT64_C(0x0300000000000000)) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_SHR_SHIFT (54U) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_SHR_CLRMSK (IMG_UINT64_C(0XFF3FFFFFFFFFFFFF)) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_SHR_LOW (IMG_UINT64_C(0000000000000000)) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_SHR_MEDIUM (IMG_UINT64_C(0x0040000000000000)) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_SHR_HIGH (IMG_UINT64_C(0x0080000000000000)) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_SHR_CRITICAL (IMG_UINT64_C(0x00c0000000000000)) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_FBA_SHIFT (52U) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_FBA_CLRMSK (IMG_UINT64_C(0XFFCFFFFFFFFFFFFF)) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_FBA_LOW (IMG_UINT64_C(0000000000000000)) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_FBA_MEDIUM (IMG_UINT64_C(0x0010000000000000)) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_FBA_HIGH (IMG_UINT64_C(0x0020000000000000)) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_FBA_CRITICAL (IMG_UINT64_C(0x0030000000000000)) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_VDM_SHIFT (50U) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_VDM_CLRMSK (IMG_UINT64_C(0XFFF3FFFFFFFFFFFF)) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_VDM_LOW (IMG_UINT64_C(0000000000000000)) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_VDM_MEDIUM (IMG_UINT64_C(0x0004000000000000)) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_VDM_HIGH (IMG_UINT64_C(0x0008000000000000)) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_VDM_CRITICAL (IMG_UINT64_C(0x000c000000000000)) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_USC_SHIFT (48U) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_USC_CLRMSK (IMG_UINT64_C(0XFFFCFFFFFFFFFFFF)) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_USC_LOW (IMG_UINT64_C(0000000000000000)) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_USC_MEDIUM (IMG_UINT64_C(0x0001000000000000)) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_USC_HIGH (IMG_UINT64_C(0x0002000000000000)) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_USC_CRITICAL (IMG_UINT64_C(0x0003000000000000)) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_PDS_SHIFT (46U) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_PDS_CLRMSK (IMG_UINT64_C(0XFFFF3FFFFFFFFFFF)) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_PDS_LOW (IMG_UINT64_C(0000000000000000)) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_PDS_MEDIUM (IMG_UINT64_C(0x0000400000000000)) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_PDS_HIGH (IMG_UINT64_C(0x0000800000000000)) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_PDS_CRITICAL (IMG_UINT64_C(0x0000c00000000000)) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_PDSRW_SHIFT (44U) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_PDSRW_CLRMSK (IMG_UINT64_C(0XFFFFCFFFFFFFFFFF)) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_PDSRW_LOW (IMG_UINT64_C(0000000000000000)) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_PDSRW_MEDIUM (IMG_UINT64_C(0x0000100000000000)) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_PDSRW_HIGH (IMG_UINT64_C(0x0000200000000000)) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_PDSRW_CRITICAL (IMG_UINT64_C(0x0000300000000000)) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_TPF_SHIFT (42U) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_TPF_CLRMSK (IMG_UINT64_C(0XFFFFF3FFFFFFFFFF)) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_TPF_LOW (IMG_UINT64_C(0000000000000000)) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_TPF_MEDIUM (IMG_UINT64_C(0x0000040000000000)) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_TPF_HIGH (IMG_UINT64_C(0x0000080000000000)) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_TPF_CRITICAL (IMG_UINT64_C(0x00000c0000000000)) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_SHF_SHG_SHIFT (40U) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_SHF_SHG_CLRMSK (IMG_UINT64_C(0XFFFFFCFFFFFFFFFF)) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_SHF_SHG_LOW (IMG_UINT64_C(0000000000000000)) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_SHF_SHG_MEDIUM (IMG_UINT64_C(0x0000010000000000)) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_SHF_SHG_HIGH (IMG_UINT64_C(0x0000020000000000)) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_SHF_SHG_CRITICAL (IMG_UINT64_C(0x0000030000000000)) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_AMC_SHIFT (38U) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_AMC_CLRMSK (IMG_UINT64_C(0XFFFFFF3FFFFFFFFF)) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_AMC_LOW (IMG_UINT64_C(0000000000000000)) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_AMC_MEDIUM (IMG_UINT64_C(0x0000004000000000)) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_AMC_HIGH (IMG_UINT64_C(0x0000008000000000)) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_AMC_CRITICAL (IMG_UINT64_C(0x000000c000000000)) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_RAC_SHIFT (36U) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_RAC_CLRMSK (IMG_UINT64_C(0XFFFFFFCFFFFFFFFF)) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_RAC_LOW (IMG_UINT64_C(0000000000000000)) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_RAC_MEDIUM (IMG_UINT64_C(0x0000001000000000)) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_RAC_HIGH (IMG_UINT64_C(0x0000002000000000)) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_RAC_CRITICAL (IMG_UINT64_C(0x0000003000000000)) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_VCE_RTC_SHIFT (34U) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_VCE_RTC_CLRMSK (IMG_UINT64_C(0XFFFFFFF3FFFFFFFF)) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_VCE_RTC_LOW (IMG_UINT64_C(0000000000000000)) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_VCE_RTC_MEDIUM (IMG_UINT64_C(0x0000000400000000)) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_VCE_RTC_HIGH (IMG_UINT64_C(0x0000000800000000)) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_VCE_RTC_CRITICAL (IMG_UINT64_C(0x0000000c00000000)) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_ISP_SHIFT (32U) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_ISP_CLRMSK (IMG_UINT64_C(0XFFFFFFFCFFFFFFFF)) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_ISP_LOW (IMG_UINT64_C(0000000000000000)) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_ISP_MEDIUM (IMG_UINT64_C(0x0000000100000000)) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_ISP_HIGH (IMG_UINT64_C(0x0000000200000000)) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_ISP_CRITICAL (IMG_UINT64_C(0x0000000300000000)) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_PPP_SHIFT (30U) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_PPP_CLRMSK (IMG_UINT64_C(0XFFFFFFFF3FFFFFFF)) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_PPP_LOW (IMG_UINT64_C(0000000000000000)) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_PPP_MEDIUM (IMG_UINT64_C(0x0000000040000000)) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_PPP_HIGH (IMG_UINT64_C(0x0000000080000000)) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_PPP_CRITICAL (IMG_UINT64_C(0x00000000c0000000)) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_IPF_SHIFT (28U) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_IPF_CLRMSK (IMG_UINT64_C(0XFFFFFFFFCFFFFFFF)) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_IPF_LOW (IMG_UINT64_C(0000000000000000)) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_IPF_MEDIUM (IMG_UINT64_C(0x0000000010000000)) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_IPF_HIGH (IMG_UINT64_C(0x0000000020000000)) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_IPF_CRITICAL (IMG_UINT64_C(0x0000000030000000)) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_VCE_SHIFT (26U) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_VCE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFF3FFFFFF)) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_VCE_LOW (IMG_UINT64_C(0000000000000000)) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_VCE_MEDIUM (IMG_UINT64_C(0x0000000004000000)) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_VCE_HIGH (IMG_UINT64_C(0x0000000008000000)) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_VCE_CRITICAL (IMG_UINT64_C(0x000000000c000000)) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_PBE_SHIFT (24U) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_PBE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFCFFFFFF)) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_PBE_LOW (IMG_UINT64_C(0000000000000000)) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_PBE_MEDIUM (IMG_UINT64_C(0x0000000001000000)) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_PBE_HIGH (IMG_UINT64_C(0x0000000002000000)) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_PBE_CRITICAL (IMG_UINT64_C(0x0000000003000000)) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_TCU_SHIFT (22U) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_TCU_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFF3FFFFF)) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_TCU_LOW (IMG_UINT64_C(0000000000000000)) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_TCU_MEDIUM (IMG_UINT64_C(0x0000000000400000)) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_TCU_HIGH (IMG_UINT64_C(0x0000000000800000)) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_TCU_CRITICAL (IMG_UINT64_C(0x0000000000c00000)) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_MCU_SHIFT (20U) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_MCU_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFCFFFFF)) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_MCU_LOW (IMG_UINT64_C(0000000000000000)) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_MCU_MEDIUM (IMG_UINT64_C(0x0000000000100000)) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_MCU_HIGH (IMG_UINT64_C(0x0000000000200000)) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_MCU_CRITICAL (IMG_UINT64_C(0x0000000000300000)) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_RPM_SHIFT (18U) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_RPM_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFF3FFFF)) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_RPM_LOW (IMG_UINT64_C(0000000000000000)) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_RPM_MEDIUM (IMG_UINT64_C(0x0000000000040000)) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_RPM_HIGH (IMG_UINT64_C(0x0000000000080000)) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_RPM_CRITICAL (IMG_UINT64_C(0x00000000000c0000)) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_RTU_SHIFT (16U) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_RTU_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFCFFFF)) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_RTU_LOW (IMG_UINT64_C(0000000000000000)) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_RTU_MEDIUM (IMG_UINT64_C(0x0000000000010000)) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_RTU_HIGH (IMG_UINT64_C(0x0000000000020000)) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_RTU_CRITICAL (IMG_UINT64_C(0x0000000000030000)) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_TILING_SHIFT (14U) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_TILING_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFF3FFF)) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_TILING_LOW (IMG_UINT64_C(0000000000000000)) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_TILING_MEDIUM (IMG_UINT64_C(0x0000000000004000)) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_TILING_HIGH (IMG_UINT64_C(0x0000000000008000)) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_TILING_CRITICAL (IMG_UINT64_C(0x000000000000c000)) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_META_DMA_SHIFT (12U) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_META_DMA_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFCFFF)) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_META_DMA_LOW (IMG_UINT64_C(0000000000000000)) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_META_DMA_MEDIUM (IMG_UINT64_C(0x0000000000001000)) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_META_DMA_HIGH (IMG_UINT64_C(0x0000000000002000)) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_META_DMA_CRITICAL (IMG_UINT64_C(0x0000000000003000)) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_META_SHIFT (10U) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_META_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFF3FF)) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_META_LOW (IMG_UINT64_C(0000000000000000)) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_META_MEDIUM (IMG_UINT64_C(0x0000000000000400)) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_META_HIGH (IMG_UINT64_C(0x0000000000000800)) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_META_CRITICAL (IMG_UINT64_C(0x0000000000000c00)) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_CDM_SHIFT (8U) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_CDM_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFCFF)) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_CDM_LOW (IMG_UINT64_C(0000000000000000)) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_CDM_MEDIUM (IMG_UINT64_C(0x0000000000000100)) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_CDM_HIGH (IMG_UINT64_C(0x0000000000000200)) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_CDM_CRITICAL (IMG_UINT64_C(0x0000000000000300)) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_PM_SHIFT (6U) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_PM_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFF3F)) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_PM_LOW (IMG_UINT64_C(0000000000000000)) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_PM_MEDIUM (IMG_UINT64_C(0x0000000000000040)) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_PM_HIGH (IMG_UINT64_C(0x0000000000000080)) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_PM_CRITICAL (IMG_UINT64_C(0x00000000000000c0)) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_TDM_SHIFT (4U) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_TDM_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFCF)) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_TDM_LOW (IMG_UINT64_C(0000000000000000)) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_TDM_MEDIUM (IMG_UINT64_C(0x0000000000000010)) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_TDM_HIGH (IMG_UINT64_C(0x0000000000000020)) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_TDM_CRITICAL (IMG_UINT64_C(0x0000000000000030)) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_DCE_SHIFT (2U) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_DCE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFF3)) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_DCE_LOW (IMG_UINT64_C(0000000000000000)) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_DCE_MEDIUM (IMG_UINT64_C(0x0000000000000004)) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_DCE_HIGH (IMG_UINT64_C(0x0000000000000008)) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_DCE_CRITICAL (IMG_UINT64_C(0x000000000000000c)) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_IPP_SHIFT (0U) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_IPP_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFC)) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_IPP_LOW (IMG_UINT64_C(0000000000000000)) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_IPP_MEDIUM (IMG_UINT64_C(0x0000000000000001)) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_IPP_HIGH (IMG_UINT64_C(0x0000000000000002)) #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_IPP_CRITICAL (IMG_UINT64_C(0x0000000000000003)) #define VHA_CR_ACE_CTRL_ENUM_WR_CACHEABLE_MASK (0x0000000FU) /* Device Non-bufferable */ #define VHA_CR_ACE_CTRL_ENUM_WR_CACHEABLE_DEVICE_NON_BUFFERABLE (0x00000000U) /* Device Bufferable */ #define VHA_CR_ACE_CTRL_ENUM_WR_CACHEABLE_DEVICE_BUFFERABLE (0x00000001U) /* Normal Non-cacheable Non-bufferable */ #define VHA_CR_ACE_CTRL_ENUM_WR_CACHEABLE_NORMAL_NC_NON_BUFFERABLE (0x00000002U) /* Normal Non-cacheable Bufferable */ #define VHA_CR_ACE_CTRL_ENUM_WR_CACHEABLE_NORMAL_NC_BUFFERABLE (0x00000003U) /* Write-through No-allocate */ #define VHA_CR_ACE_CTRL_ENUM_WR_CACHEABLE_WRITE_THROUGH_NO_ALLOCATE (0x00000006U) /* Write-through Write-allocate */ #define VHA_CR_ACE_CTRL_ENUM_WR_CACHEABLE_WRITE_THROUGH_WRITE_ALLOCATE (0x0000000eU) /* Write-back No-allocate */ #define VHA_CR_ACE_CTRL_ENUM_WR_CACHEABLE_WRITE_BACK_NO_ALLOCATE (0x00000007U) /* Write-back Write-allocate */ #define VHA_CR_ACE_CTRL_ENUM_WR_CACHEABLE_WRITE_BACK_WRITE_ALLOCATE (0x0000000fU) #define VHA_CR_ACE_CTRL_ENUM_RD_CACHEABLE_MASK (0x0000000FU) /* Device Non-bufferable */ #define VHA_CR_ACE_CTRL_ENUM_RD_CACHEABLE_DEVICE_NON_BUFFERABLE (0x00000000U) /* Device Bufferable */ #define VHA_CR_ACE_CTRL_ENUM_RD_CACHEABLE_DEVICE_BUFFERABLE (0x00000001U) /* Normal Non-cacheable Non-bufferable */ #define VHA_CR_ACE_CTRL_ENUM_RD_CACHEABLE_NORMAL_NC_NON_BUFFERABLE (0x00000002U) /* Normal Non-cacheable Bufferable */ #define VHA_CR_ACE_CTRL_ENUM_RD_CACHEABLE_NORMAL_NC_BUFFERABLE (0x00000003U) /* Write-through No-allocate */ #define VHA_CR_ACE_CTRL_ENUM_RD_CACHEABLE_WRITE_THROUGH_NO_ALLOCATE (0x0000000aU) /* Write-through Read-allocate */ #define VHA_CR_ACE_CTRL_ENUM_RD_CACHEABLE_WRITE_THROUGH_READ_ALLOCATE (0x0000000eU) /* Write-back No-allocate */ #define VHA_CR_ACE_CTRL_ENUM_RD_CACHEABLE_WRITE_BACK_NO_ALLOCATE (0x0000000bU) /* Write-back Read-allocate */ #define VHA_CR_ACE_CTRL_ENUM_RD_CACHEABLE_WRITE_BACK_READ_ALLOCATE (0x0000000fU) /* Non-Shareable */ #define VHA_CR_ACE_CTRL_ENUM_NCOH_DOMAIN_NON_SHAREABLE (0x00000000U) /* System */ #define VHA_CR_ACE_CTRL_ENUM_NCOH_DOMAIN_SYSTEM (0x00000001U) /* Inner-Shareable */ #define VHA_CR_ACE_CTRL_ENUM_COH_DOMAIN_INNER_SHAREABLE (0x00000000U) /* Outer-Shareable */ #define VHA_CR_ACE_CTRL_ENUM_COH_DOMAIN_OUTER_SHAREABLE (0x00000001U) /* Register VHA_CR_ACE_CTRL */ #define VHA_CR_ACE_CTRL (0xE320U) #define VHA_CR_ACE_CTRL_MASKFULL (IMG_UINT64_C(0x00000000007FCFFF)) #define VHA_CR_ACE_CTRL_CLB_AXQOS_SHIFT (19U) #define VHA_CR_ACE_CTRL_CLB_AXQOS_CLRMSK (0XFF87FFFFU) #define VHA_CR_ACE_CTRL_PM_MMU_AXCACHE_SHIFT (15U) #define VHA_CR_ACE_CTRL_PM_MMU_AXCACHE_CLRMSK (0XFFF87FFFU) #define VHA_CR_ACE_CTRL_ENABLE_NONSECURE_PROT_MATCH_SHIFT (14U) #define VHA_CR_ACE_CTRL_ENABLE_NONSECURE_PROT_MATCH_CLRMSK (0XFFFFBFFFU) #define VHA_CR_ACE_CTRL_ENABLE_NONSECURE_PROT_MATCH_EN (0X00004000U) #define VHA_CR_ACE_CTRL_MMU_AWCACHE_SHIFT (8U) #define VHA_CR_ACE_CTRL_MMU_AWCACHE_CLRMSK (0XFFFFF0FFU) #define VHA_CR_ACE_CTRL_MMU_AWCACHE_DEVICE_NON_BUFFERABLE (00000000U) #define VHA_CR_ACE_CTRL_MMU_AWCACHE_DEVICE_BUFFERABLE (0X00000100U) #define VHA_CR_ACE_CTRL_MMU_AWCACHE_NORMAL_NC_NON_BUFFERABLE (0X00000200U) #define VHA_CR_ACE_CTRL_MMU_AWCACHE_NORMAL_NC_BUFFERABLE (0X00000300U) #define VHA_CR_ACE_CTRL_MMU_AWCACHE_WRITE_THROUGH_NO_ALLOCATE (0X00000600U) #define VHA_CR_ACE_CTRL_MMU_AWCACHE_WRITE_THROUGH_WRITE_ALLOCATE (0X00000E00U) #define VHA_CR_ACE_CTRL_MMU_AWCACHE_WRITE_BACK_NO_ALLOCATE (0X00000700U) #define VHA_CR_ACE_CTRL_MMU_AWCACHE_WRITE_BACK_WRITE_ALLOCATE (0X00000F00U) #define VHA_CR_ACE_CTRL_MMU_ARCACHE_SHIFT (4U) #define VHA_CR_ACE_CTRL_MMU_ARCACHE_CLRMSK (0XFFFFFF0FU) #define VHA_CR_ACE_CTRL_MMU_ARCACHE_DEVICE_NON_BUFFERABLE (00000000U) #define VHA_CR_ACE_CTRL_MMU_ARCACHE_DEVICE_BUFFERABLE (0X00000010U) #define VHA_CR_ACE_CTRL_MMU_ARCACHE_NORMAL_NC_NON_BUFFERABLE (0X00000020U) #define VHA_CR_ACE_CTRL_MMU_ARCACHE_NORMAL_NC_BUFFERABLE (0X00000030U) #define VHA_CR_ACE_CTRL_MMU_ARCACHE_WRITE_THROUGH_NO_ALLOCATE (0X000000A0U) #define VHA_CR_ACE_CTRL_MMU_ARCACHE_WRITE_THROUGH_READ_ALLOCATE (0X000000E0U) #define VHA_CR_ACE_CTRL_MMU_ARCACHE_WRITE_BACK_NO_ALLOCATE (0X000000B0U) #define VHA_CR_ACE_CTRL_MMU_ARCACHE_WRITE_BACK_READ_ALLOCATE (0X000000F0U) #define VHA_CR_ACE_CTRL_MMU_DOMAIN_SHIFT (2U) #define VHA_CR_ACE_CTRL_MMU_DOMAIN_CLRMSK (0XFFFFFFF3U) #define VHA_CR_ACE_CTRL_COH_DOMAIN_SHIFT (1U) #define VHA_CR_ACE_CTRL_COH_DOMAIN_CLRMSK (0XFFFFFFFDU) #define VHA_CR_ACE_CTRL_COH_DOMAIN_INNER_SHAREABLE (00000000U) #define VHA_CR_ACE_CTRL_COH_DOMAIN_OUTER_SHAREABLE (0X00000002U) #define VHA_CR_ACE_CTRL_NON_COH_DOMAIN_SHIFT (0U) #define VHA_CR_ACE_CTRL_NON_COH_DOMAIN_CLRMSK (0XFFFFFFFEU) #define VHA_CR_ACE_CTRL_NON_COH_DOMAIN_NON_SHAREABLE (00000000U) #define VHA_CR_ACE_CTRL_NON_COH_DOMAIN_SYSTEM (0X00000001U) #define VHA_CR_ACE_PROT_CTRL_ENUM_PROT_MASK (0x00000007U) /* Unprivileged secure data access*/ #define VHA_CR_ACE_PROT_CTRL_ENUM_PROT_UNPRIVILEGED_SECURE_DATA (0x00000000U) /* Privileged secure data access*/ #define VHA_CR_ACE_PROT_CTRL_ENUM_PROT_PRIVILEGED_SECURE_DATA (0x00000001U) /* Unprivileged non-secure data access*/ #define VHA_CR_ACE_PROT_CTRL_ENUM_PROT_UNPRIVILEGED_NONSECURE_DATA (0x00000002U) /* Privileged non-secure data access*/ #define VHA_CR_ACE_PROT_CTRL_ENUM_PROT_PRIVILEGED_NONSECURE_DATA (0x00000003U) /* Unprivileged secure instruction access*/ #define VHA_CR_ACE_PROT_CTRL_ENUM_PROT_UNPRIVILEGED_SECURE_INSTRUCTION (0x00000004U) /* Privileged secure instruction access*/ #define VHA_CR_ACE_PROT_CTRL_ENUM_PROT_PRIVILEGED_SECURE_INSTRUCTION (0x00000005U) /* Unprivileged non-secure instruction access*/ #define VHA_CR_ACE_PROT_CTRL_ENUM_PROT_UNPRIVILEGED_NONSECURE_INSTRUCTION (0x00000006U) /* Privileged non-secure instruction access*/ #define VHA_CR_ACE_PROT_CTRL_ENUM_PROT_PRIVILEGED_NONSECURE_INSTRUCTION (0x00000007U) /* Register VHA_CR_ACE_PROT_CTRL */ #define VHA_CR_ACE_PROT_CTRL (0xE328U) #define VHA_CR_ACE_PROT_CTRL_MASKFULL (IMG_UINT64_C(0x0707070707070707)) #define VHA_CR_ACE_PROT_CTRL_OSID7_SHIFT (56U) #define VHA_CR_ACE_PROT_CTRL_OSID7_CLRMSK (IMG_UINT64_C(0XF8FFFFFFFFFFFFFF)) #define VHA_CR_ACE_PROT_CTRL_OSID7_UNPRIVILEGED_SECURE_DATA (IMG_UINT64_C(0000000000000000)) #define VHA_CR_ACE_PROT_CTRL_OSID7_PRIVILEGED_SECURE_DATA (IMG_UINT64_C(0x0100000000000000)) #define VHA_CR_ACE_PROT_CTRL_OSID7_UNPRIVILEGED_NONSECURE_DATA (IMG_UINT64_C(0x0200000000000000)) #define VHA_CR_ACE_PROT_CTRL_OSID7_PRIVILEGED_NONSECURE_DATA (IMG_UINT64_C(0x0300000000000000)) #define VHA_CR_ACE_PROT_CTRL_OSID7_UNPRIVILEGED_SECURE_INSTRUCTION (IMG_UINT64_C(0x0400000000000000)) #define VHA_CR_ACE_PROT_CTRL_OSID7_PRIVILEGED_SECURE_INSTRUCTION (IMG_UINT64_C(0x0500000000000000)) #define VHA_CR_ACE_PROT_CTRL_OSID7_UNPRIVILEGED_NONSECURE_INSTRUCTION (IMG_UINT64_C(0x0600000000000000)) #define VHA_CR_ACE_PROT_CTRL_OSID7_PRIVILEGED_NONSECURE_INSTRUCTION (IMG_UINT64_C(0x0700000000000000)) #define VHA_CR_ACE_PROT_CTRL_OSID6_SHIFT (48U) #define VHA_CR_ACE_PROT_CTRL_OSID6_CLRMSK (IMG_UINT64_C(0XFFF8FFFFFFFFFFFF)) #define VHA_CR_ACE_PROT_CTRL_OSID6_UNPRIVILEGED_SECURE_DATA (IMG_UINT64_C(0000000000000000)) #define VHA_CR_ACE_PROT_CTRL_OSID6_PRIVILEGED_SECURE_DATA (IMG_UINT64_C(0x0001000000000000)) #define VHA_CR_ACE_PROT_CTRL_OSID6_UNPRIVILEGED_NONSECURE_DATA (IMG_UINT64_C(0x0002000000000000)) #define VHA_CR_ACE_PROT_CTRL_OSID6_PRIVILEGED_NONSECURE_DATA (IMG_UINT64_C(0x0003000000000000)) #define VHA_CR_ACE_PROT_CTRL_OSID6_UNPRIVILEGED_SECURE_INSTRUCTION (IMG_UINT64_C(0x0004000000000000)) #define VHA_CR_ACE_PROT_CTRL_OSID6_PRIVILEGED_SECURE_INSTRUCTION (IMG_UINT64_C(0x0005000000000000)) #define VHA_CR_ACE_PROT_CTRL_OSID6_UNPRIVILEGED_NONSECURE_INSTRUCTION (IMG_UINT64_C(0x0006000000000000)) #define VHA_CR_ACE_PROT_CTRL_OSID6_PRIVILEGED_NONSECURE_INSTRUCTION (IMG_UINT64_C(0x0007000000000000)) #define VHA_CR_ACE_PROT_CTRL_OSID5_SHIFT (40U) #define VHA_CR_ACE_PROT_CTRL_OSID5_CLRMSK (IMG_UINT64_C(0XFFFFF8FFFFFFFFFF)) #define VHA_CR_ACE_PROT_CTRL_OSID5_UNPRIVILEGED_SECURE_DATA (IMG_UINT64_C(0000000000000000)) #define VHA_CR_ACE_PROT_CTRL_OSID5_PRIVILEGED_SECURE_DATA (IMG_UINT64_C(0x0000010000000000)) #define VHA_CR_ACE_PROT_CTRL_OSID5_UNPRIVILEGED_NONSECURE_DATA (IMG_UINT64_C(0x0000020000000000)) #define VHA_CR_ACE_PROT_CTRL_OSID5_PRIVILEGED_NONSECURE_DATA (IMG_UINT64_C(0x0000030000000000)) #define VHA_CR_ACE_PROT_CTRL_OSID5_UNPRIVILEGED_SECURE_INSTRUCTION (IMG_UINT64_C(0x0000040000000000)) #define VHA_CR_ACE_PROT_CTRL_OSID5_PRIVILEGED_SECURE_INSTRUCTION (IMG_UINT64_C(0x0000050000000000)) #define VHA_CR_ACE_PROT_CTRL_OSID5_UNPRIVILEGED_NONSECURE_INSTRUCTION (IMG_UINT64_C(0x0000060000000000)) #define VHA_CR_ACE_PROT_CTRL_OSID5_PRIVILEGED_NONSECURE_INSTRUCTION (IMG_UINT64_C(0x0000070000000000)) #define VHA_CR_ACE_PROT_CTRL_OSID4_SHIFT (32U) #define VHA_CR_ACE_PROT_CTRL_OSID4_CLRMSK (IMG_UINT64_C(0XFFFFFFF8FFFFFFFF)) #define VHA_CR_ACE_PROT_CTRL_OSID4_UNPRIVILEGED_SECURE_DATA (IMG_UINT64_C(0000000000000000)) #define VHA_CR_ACE_PROT_CTRL_OSID4_PRIVILEGED_SECURE_DATA (IMG_UINT64_C(0x0000000100000000)) #define VHA_CR_ACE_PROT_CTRL_OSID4_UNPRIVILEGED_NONSECURE_DATA (IMG_UINT64_C(0x0000000200000000)) #define VHA_CR_ACE_PROT_CTRL_OSID4_PRIVILEGED_NONSECURE_DATA (IMG_UINT64_C(0x0000000300000000)) #define VHA_CR_ACE_PROT_CTRL_OSID4_UNPRIVILEGED_SECURE_INSTRUCTION (IMG_UINT64_C(0x0000000400000000)) #define VHA_CR_ACE_PROT_CTRL_OSID4_PRIVILEGED_SECURE_INSTRUCTION (IMG_UINT64_C(0x0000000500000000)) #define VHA_CR_ACE_PROT_CTRL_OSID4_UNPRIVILEGED_NONSECURE_INSTRUCTION (IMG_UINT64_C(0x0000000600000000)) #define VHA_CR_ACE_PROT_CTRL_OSID4_PRIVILEGED_NONSECURE_INSTRUCTION (IMG_UINT64_C(0x0000000700000000)) #define VHA_CR_ACE_PROT_CTRL_OSID3_SHIFT (24U) #define VHA_CR_ACE_PROT_CTRL_OSID3_CLRMSK (IMG_UINT64_C(0XFFFFFFFFF8FFFFFF)) #define VHA_CR_ACE_PROT_CTRL_OSID3_UNPRIVILEGED_SECURE_DATA (IMG_UINT64_C(0000000000000000)) #define VHA_CR_ACE_PROT_CTRL_OSID3_PRIVILEGED_SECURE_DATA (IMG_UINT64_C(0x0000000001000000)) #define VHA_CR_ACE_PROT_CTRL_OSID3_UNPRIVILEGED_NONSECURE_DATA (IMG_UINT64_C(0x0000000002000000)) #define VHA_CR_ACE_PROT_CTRL_OSID3_PRIVILEGED_NONSECURE_DATA (IMG_UINT64_C(0x0000000003000000)) #define VHA_CR_ACE_PROT_CTRL_OSID3_UNPRIVILEGED_SECURE_INSTRUCTION (IMG_UINT64_C(0x0000000004000000)) #define VHA_CR_ACE_PROT_CTRL_OSID3_PRIVILEGED_SECURE_INSTRUCTION (IMG_UINT64_C(0x0000000005000000)) #define VHA_CR_ACE_PROT_CTRL_OSID3_UNPRIVILEGED_NONSECURE_INSTRUCTION (IMG_UINT64_C(0x0000000006000000)) #define VHA_CR_ACE_PROT_CTRL_OSID3_PRIVILEGED_NONSECURE_INSTRUCTION (IMG_UINT64_C(0x0000000007000000)) #define VHA_CR_ACE_PROT_CTRL_OSID2_SHIFT (16U) #define VHA_CR_ACE_PROT_CTRL_OSID2_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFF8FFFF)) #define VHA_CR_ACE_PROT_CTRL_OSID2_UNPRIVILEGED_SECURE_DATA (IMG_UINT64_C(0000000000000000)) #define VHA_CR_ACE_PROT_CTRL_OSID2_PRIVILEGED_SECURE_DATA (IMG_UINT64_C(0x0000000000010000)) #define VHA_CR_ACE_PROT_CTRL_OSID2_UNPRIVILEGED_NONSECURE_DATA (IMG_UINT64_C(0x0000000000020000)) #define VHA_CR_ACE_PROT_CTRL_OSID2_PRIVILEGED_NONSECURE_DATA (IMG_UINT64_C(0x0000000000030000)) #define VHA_CR_ACE_PROT_CTRL_OSID2_UNPRIVILEGED_SECURE_INSTRUCTION (IMG_UINT64_C(0x0000000000040000)) #define VHA_CR_ACE_PROT_CTRL_OSID2_PRIVILEGED_SECURE_INSTRUCTION (IMG_UINT64_C(0x0000000000050000)) #define VHA_CR_ACE_PROT_CTRL_OSID2_UNPRIVILEGED_NONSECURE_INSTRUCTION (IMG_UINT64_C(0x0000000000060000)) #define VHA_CR_ACE_PROT_CTRL_OSID2_PRIVILEGED_NONSECURE_INSTRUCTION (IMG_UINT64_C(0x0000000000070000)) #define VHA_CR_ACE_PROT_CTRL_OSID1_SHIFT (8U) #define VHA_CR_ACE_PROT_CTRL_OSID1_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFF8FF)) #define VHA_CR_ACE_PROT_CTRL_OSID1_UNPRIVILEGED_SECURE_DATA (IMG_UINT64_C(0000000000000000)) #define VHA_CR_ACE_PROT_CTRL_OSID1_PRIVILEGED_SECURE_DATA (IMG_UINT64_C(0x0000000000000100)) #define VHA_CR_ACE_PROT_CTRL_OSID1_UNPRIVILEGED_NONSECURE_DATA (IMG_UINT64_C(0x0000000000000200)) #define VHA_CR_ACE_PROT_CTRL_OSID1_PRIVILEGED_NONSECURE_DATA (IMG_UINT64_C(0x0000000000000300)) #define VHA_CR_ACE_PROT_CTRL_OSID1_UNPRIVILEGED_SECURE_INSTRUCTION (IMG_UINT64_C(0x0000000000000400)) #define VHA_CR_ACE_PROT_CTRL_OSID1_PRIVILEGED_SECURE_INSTRUCTION (IMG_UINT64_C(0x0000000000000500)) #define VHA_CR_ACE_PROT_CTRL_OSID1_UNPRIVILEGED_NONSECURE_INSTRUCTION (IMG_UINT64_C(0x0000000000000600)) #define VHA_CR_ACE_PROT_CTRL_OSID1_PRIVILEGED_NONSECURE_INSTRUCTION (IMG_UINT64_C(0x0000000000000700)) #define VHA_CR_ACE_PROT_CTRL_OSID0_SHIFT (0U) #define VHA_CR_ACE_PROT_CTRL_OSID0_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFF8)) #define VHA_CR_ACE_PROT_CTRL_OSID0_UNPRIVILEGED_SECURE_DATA (IMG_UINT64_C(0000000000000000)) #define VHA_CR_ACE_PROT_CTRL_OSID0_PRIVILEGED_SECURE_DATA (IMG_UINT64_C(0x0000000000000001)) #define VHA_CR_ACE_PROT_CTRL_OSID0_UNPRIVILEGED_NONSECURE_DATA (IMG_UINT64_C(0x0000000000000002)) #define VHA_CR_ACE_PROT_CTRL_OSID0_PRIVILEGED_NONSECURE_DATA (IMG_UINT64_C(0x0000000000000003)) #define VHA_CR_ACE_PROT_CTRL_OSID0_UNPRIVILEGED_SECURE_INSTRUCTION (IMG_UINT64_C(0x0000000000000004)) #define VHA_CR_ACE_PROT_CTRL_OSID0_PRIVILEGED_SECURE_INSTRUCTION (IMG_UINT64_C(0x0000000000000005)) #define VHA_CR_ACE_PROT_CTRL_OSID0_UNPRIVILEGED_NONSECURE_INSTRUCTION (IMG_UINT64_C(0x0000000000000006)) #define VHA_CR_ACE_PROT_CTRL_OSID0_PRIVILEGED_NONSECURE_INSTRUCTION (IMG_UINT64_C(0x0000000000000007)) /* Register VHA_CR_ACE_STATUS */ #define VHA_CR_ACE_STATUS (0xE330U) #define VHA_CR_ACE_STATUS_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF)) #define VHA_CR_ACE_STATUS_WR_BUS3_ERROR_SHIFT (28U) #define VHA_CR_ACE_STATUS_WR_BUS3_ERROR_CLRMSK (0X0FFFFFFFU) #define VHA_CR_ACE_STATUS_RD_BUS3_ERROR_SHIFT (24U) #define VHA_CR_ACE_STATUS_RD_BUS3_ERROR_CLRMSK (0XF0FFFFFFU) #define VHA_CR_ACE_STATUS_WR_BUS2_ERROR_SHIFT (20U) #define VHA_CR_ACE_STATUS_WR_BUS2_ERROR_CLRMSK (0XFF0FFFFFU) #define VHA_CR_ACE_STATUS_RD_BUS2_ERROR_SHIFT (16U) #define VHA_CR_ACE_STATUS_RD_BUS2_ERROR_CLRMSK (0XFFF0FFFFU) #define VHA_CR_ACE_STATUS_WR_BUS1_ERROR_SHIFT (12U) #define VHA_CR_ACE_STATUS_WR_BUS1_ERROR_CLRMSK (0XFFFF0FFFU) #define VHA_CR_ACE_STATUS_RD_BUS1_ERROR_SHIFT (8U) #define VHA_CR_ACE_STATUS_RD_BUS1_ERROR_CLRMSK (0XFFFFF0FFU) #define VHA_CR_ACE_STATUS_WR_BUS0_ERROR_SHIFT (4U) #define VHA_CR_ACE_STATUS_WR_BUS0_ERROR_CLRMSK (0XFFFFFF0FU) #define VHA_CR_ACE_STATUS_RD_BUS0_ERROR_SHIFT (0U) #define VHA_CR_ACE_STATUS_RD_BUS0_ERROR_CLRMSK (0XFFFFFFF0U) #define VHA_CR_SOC_AXI_ENUM_COH_MASK (0x00000003U) /* The SoC does not support any form of Coherency*/ #define VHA_CR_SOC_AXI_ENUM_COH_NO_COHERENCY (0x00000000U) /* The SoC supports ACE-Lite or I/O Coherency*/ #define VHA_CR_SOC_AXI_ENUM_COH_ACE_LITE_COHERENCY (0x00000001U) /* The SoC supports full ACE or 2-Way Coherency*/ #define VHA_CR_SOC_AXI_ENUM_COH_FULL_ACE_COHERENCY (0x00000002U) /* Register VHA_CR_SOC_AXI */ #define VHA_CR_SOC_AXI (0xE338U) #define VHA_CR_SOC_AXI_MASKFULL (IMG_UINT64_C(0x000000000000000F)) #define VHA_CR_SOC_AXI_NON_COHERENT_128_BYTE_BURST_SUPPORT_SHIFT (3U) #define VHA_CR_SOC_AXI_NON_COHERENT_128_BYTE_BURST_SUPPORT_CLRMSK (0XFFFFFFF7U) #define VHA_CR_SOC_AXI_NON_COHERENT_128_BYTE_BURST_SUPPORT_EN (0X00000008U) #define VHA_CR_SOC_AXI_COHERENT_128_BYTE_BURST_SUPPORT_SHIFT (2U) #define VHA_CR_SOC_AXI_COHERENT_128_BYTE_BURST_SUPPORT_CLRMSK (0XFFFFFFFBU) #define VHA_CR_SOC_AXI_COHERENT_128_BYTE_BURST_SUPPORT_EN (0X00000004U) #define VHA_CR_SOC_AXI_COHERENCY_SUPPORT_SHIFT (0U) #define VHA_CR_SOC_AXI_COHERENCY_SUPPORT_CLRMSK (0XFFFFFFFCU) #define VHA_CR_SOC_AXI_COHERENCY_SUPPORT_NO_COHERENCY (00000000U) #define VHA_CR_SOC_AXI_COHERENCY_SUPPORT_ACE_LITE_COHERENCY (0X00000001U) #define VHA_CR_SOC_AXI_COHERENCY_SUPPORT_FULL_ACE_COHERENCY (0X00000002U) #define VHA_CR_L1_GLB_CTRL_ENUM_HASH_MODE_MASK (0x00000003U) /* Addresses interleaved between Cache Banks using a weaved XOR hash of address bits */ #define VHA_CR_L1_GLB_CTRL_ENUM_HASH_MODE_WEAVED_HASH (0x00000000U) /* Addresses interleaved between Cache Bank using a combined Set & Bank hash of the upper address bits */ #define VHA_CR_L1_GLB_CTRL_ENUM_HASH_MODE_PVR_V3_HASHING (0x00000001U) /* Register VHA_CR_L1_GLB_CTRL */ #define VHA_CR_L1_GLB_CTRL (0xE400U) #define VHA_CR_L1_GLB_CTRL_MASKFULL (IMG_UINT64_C(0x0000000000000003)) #define VHA_CR_L1_GLB_CTRL_HASH_MODE_SHIFT (0U) #define VHA_CR_L1_GLB_CTRL_HASH_MODE_CLRMSK (0XFFFFFFFCU) #define VHA_CR_L1_GLB_CTRL_HASH_MODE_WEAVED_HASH (00000000U) #define VHA_CR_L1_GLB_CTRL_HASH_MODE_PVR_V3_HASHING (0X00000001U) /* Register VHA_CR_CONTEXT_MAPPING2 */ #define VHA_CR_CONTEXT_MAPPING2 (0xF088U) #define VHA_CR_CONTEXT_MAPPING2_MASKFULL (IMG_UINT64_C(0x0000000000FFFFFF)) #define VHA_CR_CONTEXT_MAPPING2_ALIST0_SHIFT (16U) #define VHA_CR_CONTEXT_MAPPING2_ALIST0_CLRMSK (0XFF00FFFFU) #define VHA_CR_CONTEXT_MAPPING2_TE0_SHIFT (8U) #define VHA_CR_CONTEXT_MAPPING2_TE0_CLRMSK (0XFFFF00FFU) #define VHA_CR_CONTEXT_MAPPING2_VCE0_SHIFT (0U) #define VHA_CR_CONTEXT_MAPPING2_VCE0_CLRMSK (0XFFFFFF00U) /* Register VHA_CR_CONTEXT_MAPPING3 */ #define VHA_CR_CONTEXT_MAPPING3 (0xF090U) #define VHA_CR_CONTEXT_MAPPING3_MASKFULL (IMG_UINT64_C(0x0000000000FFFFFF)) #define VHA_CR_CONTEXT_MAPPING3_ALIST1_SHIFT (16U) #define VHA_CR_CONTEXT_MAPPING3_ALIST1_CLRMSK (0XFF00FFFFU) #define VHA_CR_CONTEXT_MAPPING3_TE1_SHIFT (8U) #define VHA_CR_CONTEXT_MAPPING3_TE1_CLRMSK (0XFFFF00FFU) #define VHA_CR_CONTEXT_MAPPING3_VCE1_SHIFT (0U) #define VHA_CR_CONTEXT_MAPPING3_VCE1_CLRMSK (0XFFFFFF00U) /* Register VHA_CR_SLC_FIX */ #define VHA_CR_SLC_FIX (0xF0D8U) #define VHA_CR_SLC_FIX_MASKFULL (IMG_UINT64_C(0x000000000000FFFF)) #define VHA_CR_SLC_FIX_DISABLE_SHIFT (0U) #define VHA_CR_SLC_FIX_DISABLE_CLRMSK (0XFFFF0000U) /* Register VHA_CR_PERF_SLC */ #define VHA_CR_PERF_SLC (0xF0F0U) #define VHA_CR_PERF_SLC_MASKFULL (IMG_UINT64_C(0x000000000FFFFFFF)) #define VHA_CR_PERF_SLC_EWO_REQ_RD_WORD_COUNTER_RESET_SHIFT (27U) #define VHA_CR_PERF_SLC_EWO_REQ_RD_WORD_COUNTER_RESET_CLRMSK (0XF7FFFFFFU) #define VHA_CR_PERF_SLC_EWO_REQ_RD_WORD_COUNTER_RESET_EN (0X08000000U) #define VHA_CR_PERF_SLC_EWO_REQ_RD_COUNTER_RESET_SHIFT (26U) #define VHA_CR_PERF_SLC_EWO_REQ_RD_COUNTER_RESET_CLRMSK (0XFBFFFFFFU) #define VHA_CR_PERF_SLC_EWO_REQ_RD_COUNTER_RESET_EN (0X04000000U) #define VHA_CR_PERF_SLC_MMU_REQ_RD_WORD_COUNTER_RESET_SHIFT (25U) #define VHA_CR_PERF_SLC_MMU_REQ_RD_WORD_COUNTER_RESET_CLRMSK (0XFDFFFFFFU) #define VHA_CR_PERF_SLC_MMU_REQ_RD_WORD_COUNTER_RESET_EN (0X02000000U) #define VHA_CR_PERF_SLC_MMU_REQ_RD_COUNTER_RESET_SHIFT (24U) #define VHA_CR_PERF_SLC_MMU_REQ_RD_COUNTER_RESET_CLRMSK (0XFEFFFFFFU) #define VHA_CR_PERF_SLC_MMU_REQ_RD_COUNTER_RESET_EN (0X01000000U) #define VHA_CR_PERF_SLC_OPK_REQ_WR_WORD_COUNTER_RESET_SHIFT (23U) #define VHA_CR_PERF_SLC_OPK_REQ_WR_WORD_COUNTER_RESET_CLRMSK (0XFF7FFFFFU) #define VHA_CR_PERF_SLC_OPK_REQ_WR_WORD_COUNTER_RESET_EN (0X00800000U) #define VHA_CR_PERF_SLC_ABUF_REQ_RD_WORD_COUNTER_RESET_SHIFT (22U) #define VHA_CR_PERF_SLC_ABUF_REQ_RD_WORD_COUNTER_RESET_CLRMSK (0XFFBFFFFFU) #define VHA_CR_PERF_SLC_ABUF_REQ_RD_WORD_COUNTER_RESET_EN (0X00400000U) #define VHA_CR_PERF_SLC_CBUF_REQ_RD_WORD_COUNTER_RESET_SHIFT (21U) #define VHA_CR_PERF_SLC_CBUF_REQ_RD_WORD_COUNTER_RESET_CLRMSK (0XFFDFFFFFU) #define VHA_CR_PERF_SLC_CBUF_REQ_RD_WORD_COUNTER_RESET_EN (0X00200000U) #define VHA_CR_PERF_SLC_IBUF_REQ3_RD_WORD_COUNTER_RESET_SHIFT (20U) #define VHA_CR_PERF_SLC_IBUF_REQ3_RD_WORD_COUNTER_RESET_CLRMSK (0XFFEFFFFFU) #define VHA_CR_PERF_SLC_IBUF_REQ3_RD_WORD_COUNTER_RESET_EN (0X00100000U) #define VHA_CR_PERF_SLC_IBUF_REQ2_RD_WORD_COUNTER_RESET_SHIFT (19U) #define VHA_CR_PERF_SLC_IBUF_REQ2_RD_WORD_COUNTER_RESET_CLRMSK (0XFFF7FFFFU) #define VHA_CR_PERF_SLC_IBUF_REQ2_RD_WORD_COUNTER_RESET_EN (0X00080000U) #define VHA_CR_PERF_SLC_IBUF_REQ1_RD_WORD_COUNTER_RESET_SHIFT (18U) #define VHA_CR_PERF_SLC_IBUF_REQ1_RD_WORD_COUNTER_RESET_CLRMSK (0XFFFBFFFFU) #define VHA_CR_PERF_SLC_IBUF_REQ1_RD_WORD_COUNTER_RESET_EN (0X00040000U) #define VHA_CR_PERF_SLC_IBUF_REQ0_RD_WORD_COUNTER_RESET_SHIFT (17U) #define VHA_CR_PERF_SLC_IBUF_REQ0_RD_WORD_COUNTER_RESET_CLRMSK (0XFFFDFFFFU) #define VHA_CR_PERF_SLC_IBUF_REQ0_RD_WORD_COUNTER_RESET_EN (0X00020000U) #define VHA_CR_PERF_SLC_CMD_REQ_FENCE_WORD_COUNTER_RESET_SHIFT (16U) #define VHA_CR_PERF_SLC_CMD_REQ_FENCE_WORD_COUNTER_RESET_CLRMSK (0XFFFEFFFFU) #define VHA_CR_PERF_SLC_CMD_REQ_FENCE_WORD_COUNTER_RESET_EN (0X00010000U) #define VHA_CR_PERF_SLC_CMD_DBG_REQ_WR_WORD_COUNTER_RESET_SHIFT (15U) #define VHA_CR_PERF_SLC_CMD_DBG_REQ_WR_WORD_COUNTER_RESET_CLRMSK (0XFFFF7FFFU) #define VHA_CR_PERF_SLC_CMD_DBG_REQ_WR_WORD_COUNTER_RESET_EN (0X00008000U) #define VHA_CR_PERF_SLC_CMD_CRC_REQ_WR_WORD_COUNTER_RESET_SHIFT (14U) #define VHA_CR_PERF_SLC_CMD_CRC_REQ_WR_WORD_COUNTER_RESET_CLRMSK (0XFFFFBFFFU) #define VHA_CR_PERF_SLC_CMD_CRC_REQ_WR_WORD_COUNTER_RESET_EN (0X00004000U) #define VHA_CR_PERF_SLC_CMD_BCK_REQ_WR_WORD_COUNTER_RESET_SHIFT (13U) #define VHA_CR_PERF_SLC_CMD_BCK_REQ_WR_WORD_COUNTER_RESET_CLRMSK (0XFFFFDFFFU) #define VHA_CR_PERF_SLC_CMD_BCK_REQ_WR_WORD_COUNTER_RESET_EN (0X00002000U) #define VHA_CR_PERF_SLC_CMD_REQ_RD_WORD_COUNTER_RESET_SHIFT (12U) #define VHA_CR_PERF_SLC_CMD_REQ_RD_WORD_COUNTER_RESET_CLRMSK (0XFFFFEFFFU) #define VHA_CR_PERF_SLC_CMD_REQ_RD_WORD_COUNTER_RESET_EN (0X00001000U) #define VHA_CR_PERF_SLC_OPK_REQ_WR_COUNTER_RESET_SHIFT (11U) #define VHA_CR_PERF_SLC_OPK_REQ_WR_COUNTER_RESET_CLRMSK (0XFFFFF7FFU) #define VHA_CR_PERF_SLC_OPK_REQ_WR_COUNTER_RESET_EN (0X00000800U) #define VHA_CR_PERF_SLC_ABUF_REQ_RD_COUNTER_RESET_SHIFT (10U) #define VHA_CR_PERF_SLC_ABUF_REQ_RD_COUNTER_RESET_CLRMSK (0XFFFFFBFFU) #define VHA_CR_PERF_SLC_ABUF_REQ_RD_COUNTER_RESET_EN (0X00000400U) #define VHA_CR_PERF_SLC_CBUF_REQ_RD_COUNTER_RESET_SHIFT (9U) #define VHA_CR_PERF_SLC_CBUF_REQ_RD_COUNTER_RESET_CLRMSK (0XFFFFFDFFU) #define VHA_CR_PERF_SLC_CBUF_REQ_RD_COUNTER_RESET_EN (0X00000200U) #define VHA_CR_PERF_SLC_IBUF_REQ3_RD_COUNTER_RESET_SHIFT (8U) #define VHA_CR_PERF_SLC_IBUF_REQ3_RD_COUNTER_RESET_CLRMSK (0XFFFFFEFFU) #define VHA_CR_PERF_SLC_IBUF_REQ3_RD_COUNTER_RESET_EN (0X00000100U) #define VHA_CR_PERF_SLC_IBUF_REQ2_RD_COUNTER_RESET_SHIFT (7U) #define VHA_CR_PERF_SLC_IBUF_REQ2_RD_COUNTER_RESET_CLRMSK (0XFFFFFF7FU) #define VHA_CR_PERF_SLC_IBUF_REQ2_RD_COUNTER_RESET_EN (0X00000080U) #define VHA_CR_PERF_SLC_IBUF_REQ1_RD_COUNTER_RESET_SHIFT (6U) #define VHA_CR_PERF_SLC_IBUF_REQ1_RD_COUNTER_RESET_CLRMSK (0XFFFFFFBFU) #define VHA_CR_PERF_SLC_IBUF_REQ1_RD_COUNTER_RESET_EN (0X00000040U) #define VHA_CR_PERF_SLC_IBUF_REQ0_RD_COUNTER_RESET_SHIFT (5U) #define VHA_CR_PERF_SLC_IBUF_REQ0_RD_COUNTER_RESET_CLRMSK (0XFFFFFFDFU) #define VHA_CR_PERF_SLC_IBUF_REQ0_RD_COUNTER_RESET_EN (0X00000020U) #define VHA_CR_PERF_SLC_CMD_REQ_FENCE_COUNTER_RESET_SHIFT (4U) #define VHA_CR_PERF_SLC_CMD_REQ_FENCE_COUNTER_RESET_CLRMSK (0XFFFFFFEFU) #define VHA_CR_PERF_SLC_CMD_REQ_FENCE_COUNTER_RESET_EN (0X00000010U) #define VHA_CR_PERF_SLC_CMD_DBG_REQ_WR_COUNTER_RESET_SHIFT (3U) #define VHA_CR_PERF_SLC_CMD_DBG_REQ_WR_COUNTER_RESET_CLRMSK (0XFFFFFFF7U) #define VHA_CR_PERF_SLC_CMD_DBG_REQ_WR_COUNTER_RESET_EN (0X00000008U) #define VHA_CR_PERF_SLC_CMD_CRC_REQ_WR_COUNTER_RESET_SHIFT (2U) #define VHA_CR_PERF_SLC_CMD_CRC_REQ_WR_COUNTER_RESET_CLRMSK (0XFFFFFFFBU) #define VHA_CR_PERF_SLC_CMD_CRC_REQ_WR_COUNTER_RESET_EN (0X00000004U) #define VHA_CR_PERF_SLC_CMD_BCK_REQ_WR_COUNTER_RESET_SHIFT (1U) #define VHA_CR_PERF_SLC_CMD_BCK_REQ_WR_COUNTER_RESET_CLRMSK (0XFFFFFFFDU) #define VHA_CR_PERF_SLC_CMD_BCK_REQ_WR_COUNTER_RESET_EN (0X00000002U) #define VHA_CR_PERF_SLC_CMD_REQ_RD_COUNTER_RESET_SHIFT (0U) #define VHA_CR_PERF_SLC_CMD_REQ_RD_COUNTER_RESET_CLRMSK (0XFFFFFFFEU) #define VHA_CR_PERF_SLC_CMD_REQ_RD_COUNTER_RESET_EN (0X00000001U) /* Register VHA_CR_PERF_SLC_REQ_COUNT */ #define VHA_CR_PERF_SLC_REQ_COUNT (0xF0F8U) #define VHA_CR_PERF_SLC_REQ_COUNT_MASKFULL (IMG_UINT64_C(0x0000000000000001)) #define VHA_CR_PERF_SLC_REQ_COUNT_ENABLE_SHIFT (0U) #define VHA_CR_PERF_SLC_REQ_COUNT_ENABLE_CLRMSK (0XFFFFFFFEU) #define VHA_CR_PERF_SLC_REQ_COUNT_ENABLE_EN (0X00000001U) /* Register VHA_CR_PERF_SLC_CMD_REQ_RD */ #define VHA_CR_PERF_SLC_CMD_REQ_RD (0xF110U) #define VHA_CR_PERF_SLC_CMD_REQ_RD_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF)) #define VHA_CR_PERF_SLC_CMD_REQ_RD_COUNTER_SHIFT (0U) #define VHA_CR_PERF_SLC_CMD_REQ_RD_COUNTER_CLRMSK (00000000U) /* Register VHA_CR_PERF_SLC_CMD_BCK_REQ_WR */ #define VHA_CR_PERF_SLC_CMD_BCK_REQ_WR (0xF118U) #define VHA_CR_PERF_SLC_CMD_BCK_REQ_WR_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF)) #define VHA_CR_PERF_SLC_CMD_BCK_REQ_WR_COUNTER_SHIFT (0U) #define VHA_CR_PERF_SLC_CMD_BCK_REQ_WR_COUNTER_CLRMSK (00000000U) /* Register VHA_CR_PERF_SLC_CMD_CRC_REQ_WR */ #define VHA_CR_PERF_SLC_CMD_CRC_REQ_WR (0xF120U) #define VHA_CR_PERF_SLC_CMD_CRC_REQ_WR_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF)) #define VHA_CR_PERF_SLC_CMD_CRC_REQ_WR_COUNTER_SHIFT (0U) #define VHA_CR_PERF_SLC_CMD_CRC_REQ_WR_COUNTER_CLRMSK (00000000U) /* Register VHA_CR_PERF_SLC_CMD_DBG_REQ_WR */ #define VHA_CR_PERF_SLC_CMD_DBG_REQ_WR (0xF128U) #define VHA_CR_PERF_SLC_CMD_DBG_REQ_WR_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF)) #define VHA_CR_PERF_SLC_CMD_DBG_REQ_WR_COUNTER_SHIFT (0U) #define VHA_CR_PERF_SLC_CMD_DBG_REQ_WR_COUNTER_CLRMSK (00000000U) /* Register VHA_CR_PERF_SLC_CMD_REQ_FENCE */ #define VHA_CR_PERF_SLC_CMD_REQ_FENCE (0xF130U) #define VHA_CR_PERF_SLC_CMD_REQ_FENCE_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF)) #define VHA_CR_PERF_SLC_CMD_REQ_FENCE_COUNTER_SHIFT (0U) #define VHA_CR_PERF_SLC_CMD_REQ_FENCE_COUNTER_CLRMSK (00000000U) /* Register VHA_CR_PERF_SLC_IBUF_REQ0_RD */ #define VHA_CR_PERF_SLC_IBUF_REQ0_RD (0xF138U) #define VHA_CR_PERF_SLC_IBUF_REQ0_RD_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF)) #define VHA_CR_PERF_SLC_IBUF_REQ0_RD_COUNTER_SHIFT (0U) #define VHA_CR_PERF_SLC_IBUF_REQ0_RD_COUNTER_CLRMSK (00000000U) /* Register VHA_CR_PERF_SLC_IBUF_REQ1_RD */ #define VHA_CR_PERF_SLC_IBUF_REQ1_RD (0xF140U) #define VHA_CR_PERF_SLC_IBUF_REQ1_RD_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF)) #define VHA_CR_PERF_SLC_IBUF_REQ1_RD_COUNTER_SHIFT (0U) #define VHA_CR_PERF_SLC_IBUF_REQ1_RD_COUNTER_CLRMSK (00000000U) /* Register VHA_CR_PERF_SLC_IBUF_REQ2_RD */ #define VHA_CR_PERF_SLC_IBUF_REQ2_RD (0xF148U) #define VHA_CR_PERF_SLC_IBUF_REQ2_RD_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF)) #define VHA_CR_PERF_SLC_IBUF_REQ2_RD_COUNTER_SHIFT (0U) #define VHA_CR_PERF_SLC_IBUF_REQ2_RD_COUNTER_CLRMSK (00000000U) /* Register VHA_CR_PERF_SLC_IBUF_REQ3_RD */ #define VHA_CR_PERF_SLC_IBUF_REQ3_RD (0xF150U) #define VHA_CR_PERF_SLC_IBUF_REQ3_RD_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF)) #define VHA_CR_PERF_SLC_IBUF_REQ3_RD_COUNTER_SHIFT (0U) #define VHA_CR_PERF_SLC_IBUF_REQ3_RD_COUNTER_CLRMSK (00000000U) /* Register VHA_CR_PERF_SLC_CBUF_REQ_RD */ #define VHA_CR_PERF_SLC_CBUF_REQ_RD (0xF158U) #define VHA_CR_PERF_SLC_CBUF_REQ_RD_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF)) #define VHA_CR_PERF_SLC_CBUF_REQ_RD_COUNTER_SHIFT (0U) #define VHA_CR_PERF_SLC_CBUF_REQ_RD_COUNTER_CLRMSK (00000000U) /* Register VHA_CR_PERF_SLC_ABUF_REQ_RD */ #define VHA_CR_PERF_SLC_ABUF_REQ_RD (0xF160U) #define VHA_CR_PERF_SLC_ABUF_REQ_RD_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF)) #define VHA_CR_PERF_SLC_ABUF_REQ_RD_COUNTER_SHIFT (0U) #define VHA_CR_PERF_SLC_ABUF_REQ_RD_COUNTER_CLRMSK (00000000U) /* Register VHA_CR_PERF_SLC_OPK_REQ_WR */ #define VHA_CR_PERF_SLC_OPK_REQ_WR (0xF168U) #define VHA_CR_PERF_SLC_OPK_REQ_WR_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF)) #define VHA_CR_PERF_SLC_OPK_REQ_WR_COUNTER_SHIFT (0U) #define VHA_CR_PERF_SLC_OPK_REQ_WR_COUNTER_CLRMSK (00000000U) /* Register VHA_CR_PERF_SLC_CMD_REQ_RD_WORD */ #define VHA_CR_PERF_SLC_CMD_REQ_RD_WORD (0xF170U) #define VHA_CR_PERF_SLC_CMD_REQ_RD_WORD_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF)) #define VHA_CR_PERF_SLC_CMD_REQ_RD_WORD_COUNTER_SHIFT (0U) #define VHA_CR_PERF_SLC_CMD_REQ_RD_WORD_COUNTER_CLRMSK (00000000U) /* Register VHA_CR_PERF_SLC_CMD_BCK_REQ_WR_WORD */ #define VHA_CR_PERF_SLC_CMD_BCK_REQ_WR_WORD (0xF178U) #define VHA_CR_PERF_SLC_CMD_BCK_REQ_WR_WORD_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF)) #define VHA_CR_PERF_SLC_CMD_BCK_REQ_WR_WORD_COUNTER_SHIFT (0U) #define VHA_CR_PERF_SLC_CMD_BCK_REQ_WR_WORD_COUNTER_CLRMSK (00000000U) /* Register VHA_CR_PERF_SLC_CMD_CRC_REQ_WR_WORD */ #define VHA_CR_PERF_SLC_CMD_CRC_REQ_WR_WORD (0xF180U) #define VHA_CR_PERF_SLC_CMD_CRC_REQ_WR_WORD_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF)) #define VHA_CR_PERF_SLC_CMD_CRC_REQ_WR_WORD_COUNTER_SHIFT (0U) #define VHA_CR_PERF_SLC_CMD_CRC_REQ_WR_WORD_COUNTER_CLRMSK (00000000U) /* Register VHA_CR_PERF_SLC_CMD_DBG_REQ_WR_WORD */ #define VHA_CR_PERF_SLC_CMD_DBG_REQ_WR_WORD (0xF188U) #define VHA_CR_PERF_SLC_CMD_DBG_REQ_WR_WORD_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF)) #define VHA_CR_PERF_SLC_CMD_DBG_REQ_WR_WORD_COUNTER_SHIFT (0U) #define VHA_CR_PERF_SLC_CMD_DBG_REQ_WR_WORD_COUNTER_CLRMSK (00000000U) /* Register VHA_CR_PERF_SLC_CMD_REQ_FENCE_WORD */ #define VHA_CR_PERF_SLC_CMD_REQ_FENCE_WORD (0xF190U) #define VHA_CR_PERF_SLC_CMD_REQ_FENCE_WORD_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF)) #define VHA_CR_PERF_SLC_CMD_REQ_FENCE_WORD_COUNTER_SHIFT (0U) #define VHA_CR_PERF_SLC_CMD_REQ_FENCE_WORD_COUNTER_CLRMSK (00000000U) /* Register VHA_CR_PERF_SLC_IBUF_REQ0_RD_WORD */ #define VHA_CR_PERF_SLC_IBUF_REQ0_RD_WORD (0xF198U) #define VHA_CR_PERF_SLC_IBUF_REQ0_RD_WORD_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF)) #define VHA_CR_PERF_SLC_IBUF_REQ0_RD_WORD_COUNTER_SHIFT (0U) #define VHA_CR_PERF_SLC_IBUF_REQ0_RD_WORD_COUNTER_CLRMSK (00000000U) /* Register VHA_CR_PERF_SLC_IBUF_REQ1_RD_WORD */ #define VHA_CR_PERF_SLC_IBUF_REQ1_RD_WORD (0xF1A0U) #define VHA_CR_PERF_SLC_IBUF_REQ1_RD_WORD_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF)) #define VHA_CR_PERF_SLC_IBUF_REQ1_RD_WORD_COUNTER_SHIFT (0U) #define VHA_CR_PERF_SLC_IBUF_REQ1_RD_WORD_COUNTER_CLRMSK (00000000U) /* Register VHA_CR_PERF_SLC_IBUF_REQ2_RD_WORD */ #define VHA_CR_PERF_SLC_IBUF_REQ2_RD_WORD (0xF1A8U) #define VHA_CR_PERF_SLC_IBUF_REQ2_RD_WORD_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF)) #define VHA_CR_PERF_SLC_IBUF_REQ2_RD_WORD_COUNTER_SHIFT (0U) #define VHA_CR_PERF_SLC_IBUF_REQ2_RD_WORD_COUNTER_CLRMSK (00000000U) /* Register VHA_CR_PERF_SLC_IBUF_REQ3_RD_WORD */ #define VHA_CR_PERF_SLC_IBUF_REQ3_RD_WORD (0xF1B0U) #define VHA_CR_PERF_SLC_IBUF_REQ3_RD_WORD_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF)) #define VHA_CR_PERF_SLC_IBUF_REQ3_RD_WORD_COUNTER_SHIFT (0U) #define VHA_CR_PERF_SLC_IBUF_REQ3_RD_WORD_COUNTER_CLRMSK (00000000U) /* Register VHA_CR_PERF_SLC_CBUF_REQ_RD_WORD */ #define VHA_CR_PERF_SLC_CBUF_REQ_RD_WORD (0xF1B8U) #define VHA_CR_PERF_SLC_CBUF_REQ_RD_WORD_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF)) #define VHA_CR_PERF_SLC_CBUF_REQ_RD_WORD_COUNTER_SHIFT (0U) #define VHA_CR_PERF_SLC_CBUF_REQ_RD_WORD_COUNTER_CLRMSK (00000000U) /* Register VHA_CR_PERF_SLC_ABUF_REQ_RD_WORD */ #define VHA_CR_PERF_SLC_ABUF_REQ_RD_WORD (0xF1C0U) #define VHA_CR_PERF_SLC_ABUF_REQ_RD_WORD_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF)) #define VHA_CR_PERF_SLC_ABUF_REQ_RD_WORD_COUNTER_SHIFT (0U) #define VHA_CR_PERF_SLC_ABUF_REQ_RD_WORD_COUNTER_CLRMSK (00000000U) /* Register VHA_CR_PERF_SLC_OPK_REQ_WR_WORD */ #define VHA_CR_PERF_SLC_OPK_REQ_WR_WORD (0xF1C8U) #define VHA_CR_PERF_SLC_OPK_REQ_WR_WORD_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF)) #define VHA_CR_PERF_SLC_OPK_REQ_WR_WORD_COUNTER_SHIFT (0U) #define VHA_CR_PERF_SLC_OPK_REQ_WR_WORD_COUNTER_CLRMSK (00000000U) /* Register VHA_CR_PERF_SLC_MMU_REQ_RD */ #define VHA_CR_PERF_SLC_MMU_REQ_RD (0xF1D0U) #define VHA_CR_PERF_SLC_MMU_REQ_RD_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF)) #define VHA_CR_PERF_SLC_MMU_REQ_RD_COUNTER_SHIFT (0U) #define VHA_CR_PERF_SLC_MMU_REQ_RD_COUNTER_CLRMSK (00000000U) /* Register VHA_CR_PERF_SLC_MMU_REQ_RD_WORD */ #define VHA_CR_PERF_SLC_MMU_REQ_RD_WORD (0xF1D8U) #define VHA_CR_PERF_SLC_MMU_REQ_RD_WORD_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF)) #define VHA_CR_PERF_SLC_MMU_REQ_RD_WORD_COUNTER_SHIFT (0U) #define VHA_CR_PERF_SLC_MMU_REQ_RD_WORD_COUNTER_CLRMSK (00000000U) /* Register VHA_CR_PERF_SLC_EWO_REQ_RD */ #define VHA_CR_PERF_SLC_EWO_REQ_RD (0xF1E0U) #define VHA_CR_PERF_SLC_EWO_REQ_RD_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF)) #define VHA_CR_PERF_SLC_EWO_REQ_RD_COUNTER_SHIFT (0U) #define VHA_CR_PERF_SLC_EWO_REQ_RD_COUNTER_CLRMSK (00000000U) /* Register VHA_CR_PERF_SLC_EWO_REQ_RD_WORD */ #define VHA_CR_PERF_SLC_EWO_REQ_RD_WORD (0xF1E8U) #define VHA_CR_PERF_SLC_EWO_REQ_RD_WORD_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF)) #define VHA_CR_PERF_SLC_EWO_REQ_RD_WORD_COUNTER_SHIFT (0U) #define VHA_CR_PERF_SLC_EWO_REQ_RD_WORD_COUNTER_CLRMSK (00000000U) /* Register VHA_CR_PWR_MAN_HYSTERESIS */ #define VHA_CR_PWR_MAN_HYSTERESIS (0xF100U) #define VHA_CR_PWR_MAN_HYSTERESIS_MASKFULL (IMG_UINT64_C(0x000000000000001F)) #define VHA_CR_PWR_MAN_HYSTERESIS_VALUE_SHIFT (0U) #define VHA_CR_PWR_MAN_HYSTERESIS_VALUE_CLRMSK (0XFFFFFFE0U) #endif /* _VHA_CR_MIRAGE_H_ */ /***************************************************************************** End of file (vha_cr_mirage.h) *****************************************************************************/