Browse Source

Add xuantie-t910, support external toolchain.

等闲 3 years ago
parent
commit
045194ef53
30 changed files with 13970 additions and 1089 deletions
  1. 0 79
      conf/machine/freedom-u540.conf
  2. 63 0
      conf/machine/include/thead-base.inc
  3. 15 0
      conf/machine/light.conf
  4. 15 0
      conf/machine/qemu64.conf
  5. 51 0
      recipes-bsp/u-boot/files/ice_evb_c910_defconfig.patch
  6. 6 1
      recipes-bsp/u-boot/u-boot_%.bbappend
  7. 0 4
      recipes-core/sysvinit/sysvinit-inittab_%.bbappend
  8. 3 0
      recipes-devtools/libtool/libtool-cross_%.bbappend
  9. 3 0
      recipes-devtools/libtool/libtool-native_%.bbappend
  10. 12 0
      recipes-devtools/libtool/libtool/9999-fix-thead.patch
  11. 3 0
      recipes-devtools/libtool/libtool_%.bbappend
  12. 3 0
      recipes-devtools/libtool/nativesdk-libtool_%.bbappend
  13. 42 0
      recipes-devtools/meson/meson/0004-thead.patch
  14. 3 0
      recipes-devtools/meson/meson_%.bbappend
  15. 3 0
      recipes-devtools/meson/nativesdk-meson_%.bbappend
  16. 0 821
      recipes-kernel/linux/files/freedom-u540/0001-PCI-microsemi-Add-host-driver-for-Microsemi-PCIe-con.patch
  17. 0 50
      recipes-kernel/linux/files/freedom-u540/0002-Microsemi-PCIe-expansion-board-DT-entry.patch
  18. 0 42
      recipes-kernel/linux/files/freedom-u540/0003-HACK-Revert-of-device-Really-only-set-bus-DMA-mask-w.patch
  19. 0 42
      recipes-kernel/linux/files/freedom-u540/extra.cfg
  20. 411 0
      recipes-kernel/linux/files/xuantie-c910/ice-c910_defconfig
  21. 411 0
      recipes-kernel/linux/files/xuantie-c910/light-c910-dts.patch
  22. 3811 0
      recipes-kernel/linux/files/xuantie-c910/light-c910_defconfig
  23. 3811 0
      recipes-kernel/linux/files/xuantie-c910/qemu-c910_defconfig
  24. 989 0
      recipes-kernel/linux/files/xuantie-c910/xuantie-c910_defconfig
  25. 4269 0
      recipes-kernel/linux/files/xuantie-c910/xuantie-linux-5.4.36.patch
  26. 0 24
      recipes-kernel/linux/linux-mainline-common.inc
  27. 0 17
      recipes-kernel/linux/linux-mainline_5.4.bb
  28. 35 0
      recipes-kernel/linux/linux-thead_5.4.36.bb
  29. 6 4
      setup.sh
  30. 5 5
      tools/manifests/riscv-yocto.xml

+ 0 - 79
conf/machine/freedom-u540.conf

@@ -1,79 +0,0 @@
-#@TYPE: Machine
-#@NAME: freedom-u540
-#@SOC: Freedom U540
-#@DESCRIPTION: Machine configuration for the HiFive Unleashed development board
-
-require conf/machine/include/riscv/tune-riscv.inc
-
-MACHINE_FEATURES = "screen keyboard ext2 ext3 serial"
-
-KERNEL_CLASSES = "kernel-fitimage"
-KERNEL_IMAGETYPE = "fitImage"
-
-PREFERRED_PROVIDER_virtual/kernel ?= "linux-mainline"
-PREFERRED_PROVIDER_virtual/bootloader ?= "u-boot"
-
-PREFERRED_VERSION_openocd-native = "riscv"
-PREFERRED_VERSION_openocd = "riscv"
-
-EXTRA_IMAGEDEPENDS += "opensbi"
-RISCV_SBI_PLAT = "sifive/fu540"
-
-## This sets u-boot as the default OpenSBI payload
-RISCV_SBI_PAYLOAD ?= "u-boot.bin"
-## This will set the kernel as the OpenSBI payload. This is not recommended,
-##  you can use U-Boot's MMC loading instead.
-# RISCV_SBI_PAYLOAD ?= "${KERNEL_IMAGETYPE}-${MACHINE}.bin"
-
-RISCV_SBI_FDT ?= "hifive-unleashed-a00.dtb"
-## Use this to add Microsemi Expansion board support
-# RISCV_SBI_FDT ?=  "hifive-unleashed-a00-microsemi.dtb"
-
-SERIAL_CONSOLES = "115200;ttySIF0"
-
-MACHINE_EXTRA_RRECOMMENDS += " kernel-modules"
-
-IMAGE_FSTYPES += "wic.gz ext4"
-KERNEL_DEVICETREE ?= "sifive/${RISCV_SBI_FDT}"
-
-## Do not update fstab file when using wic images
-WIC_CREATE_EXTRA_ARGS ?= "--no-fstab-update"
-
-EXTRA_IMAGEDEPENDS += "u-boot"
-UBOOT_MACHINE = "sifive_fu540_defconfig"
-
-UBOOT_ENTRYPOINT = "0x80200000"
-UBOOT_DTB_LOADADDRESS = "0x82200000"
-
-## Set this to "mmc-boot" to generate a boot.scr file which should be included
-##  in the boot partition. It will try to load a kernel image by TFTP and if that
-##  fails it will fall back to local images in the boot partition.
-UBOOT_ENV ?= "tftp-mmc-boot"
-
-## wic default support
-WKS_FILE_DEPENDS ?= " \
-    opensbi \
-    e2fsprogs-native \
-    bmap-tools-native \
-"
-
-IMAGE_BOOT_FILES ?= " \
-    fw_payload.bin \
-    fitImage \
-    boot.scr.uimg \
-"
-
-WKS_FILE ?= "freedom-u540-opensbi.wks"
-
-BAD_RECOMMENDATIONS += "\
-    libcxx-dev \
-    libcxx-staticdev \
-    compiler-rt-dev \
-    compiler-rt-staticdev \
-"
-ASSUME_PROVIDED += "\
-    libcxx-dev \
-    libcxx-staticdev \
-    compiler-rt-dev \
-    compiler-rt-staticdev \
-"

+ 63 - 0
conf/machine/include/thead-base.inc

@@ -0,0 +1,63 @@
+require conf/machine/include/riscv/tune-riscv.inc
+
+EXTERNAL_TOOLCHAIN ?= "${HOME}/.thead/riscv64-linux"
+TCMODE="external"
+TARGET_PREFIX="riscv64-linux-gnu-"
+TARGET_ARCH="riscv64"
+TARGET_OS="linux"
+EXTERNAL_TOOLCHAIN_SYSROOT="${EXTERNAL_TOOLCHAIN}/riscv64-buildroot-linux-gnu/sysroot"
+
+INSANE_SKIP_${PN} += "glibc-so gobject-introspection-so glibc-external"
+
+PREFERRED_PROVIDER_virtual/kernel ?= "linux-thead"
+PREFERRED_PROVIDER_virtual/bootloader ?= "u-boot"
+PREFERRED_VERSION_openocd-native = "riscv"
+PREFERRED_VERSION_openocd = "riscv"
+
+# KERNEL_CLASSES  = "kernel-uimage"
+# KERNEL_IMAGETYPES = "itbImage"
+
+KERNEL_IMAGETYPE = "Image"
+
+# MACHINE_FEATURES = "usbgadget usbhost vfat alsa touchscreen"
+MACHINE_FEATURES = "screen keyboard ext2 ext3 serial"
+
+## This sets u-boot as the default OpenSBI payload
+RISCV_SBI_PAYLOAD ?= "u-boot.bin"
+
+EXTRA_IMAGEDEPENDS += "opensbi"
+RISCV_SBI_PLAT = "thead/c910"
+
+EXTRA_IMAGEDEPENDS += "u-boot"
+UBOOT_MACHINE = "qemu-riscv64_defconfig"
+
+## Do not update fstab file when using wic images
+WIC_CREATE_EXTRA_ARGS ?= "--no-fstab-update"
+
+## wic default support
+WKS_FILE_DEPENDS ?= " \
+    opensbi \
+    e2fsprogs-native \
+    bmap-tools-native \
+"
+
+IMAGE_BOOT_FILES ?= " \
+    fw_payload.bin \
+    fitImage \
+    boot.scr.uimg \
+"
+
+WKS_FILE ?= "xuantie-opensbi.wks"
+
+BAD_RECOMMENDATIONS += "\
+    libcxx-dev \
+    libcxx-staticdev \
+    compiler-rt-dev \
+    compiler-rt-staticdev \
+"
+ASSUME_PROVIDED += "\
+    libcxx-dev \
+    libcxx-staticdev \
+    compiler-rt-dev \
+    compiler-rt-staticdev \
+"

+ 15 - 0
conf/machine/light.conf

@@ -0,0 +1,15 @@
+#@TYPE: Machine
+#@NAME: xuantie
+#@SOC: XuanTie Light
+#@DESCRIPTION: Machine configuration for the HiFive Unleashed development board
+
+require conf/machine/include/thead-base.inc
+
+SERIAL_CONSOLES = "115200;ttySIF0"
+MACHINE_EXTRA_RRECOMMENDS += "kernel-modules"
+
+IMAGE_FSTYPES += "ext4"
+KERNEL_DEVICETREE ?= "thead/light-c910.dtb"
+
+UBOOT_ENTRYPOINT = "0x80200000"
+UBOOT_DTB_LOADADDRESS = "0x82200000"

+ 15 - 0
conf/machine/qemu64.conf

@@ -0,0 +1,15 @@
+#@TYPE: Machine
+#@NAME: qemu64
+#@SOC: XuanTie Light
+#@DESCRIPTION: Machine configuration for the HiFive Unleashed development board
+
+require conf/machine/include/thead-base.inc
+
+SERIAL_CONSOLES = "115200;ttySIF0"
+MACHINE_EXTRA_RRECOMMENDS += "kernel-modules"
+
+IMAGE_FSTYPES += "ext4"
+KERNEL_DEVICETREE ?= "thead/light-c910.dtb"
+
+UBOOT_ENTRYPOINT = "0x80200000"
+UBOOT_DTB_LOADADDRESS = "0x82200000"

+ 51 - 0
recipes-bsp/u-boot/files/ice_evb_c910_defconfig.patch

@@ -0,0 +1,51 @@
+From 89b448a7b17627f90ddb74f2d4d3f8d653721142 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?=E7=AD=89=E9=97=B2?= <zhiguo.zzg@alibaba-inc.com>
+Date: Tue, 15 Sep 2020 02:33:02 +0000
+Subject: [PATCH] update
+
+---
+ configs/ice_evb_c910_defconfig | 32 ++++++++++++++++++++++++++++++++
+ 1 file changed, 32 insertions(+)
+ create mode 100644 configs/ice_evb_c910_defconfig
+
+diff --git a/configs/ice_evb_c910_defconfig b/configs/ice_evb_c910_defconfig
+new file mode 100644
+index 0000000000..8fef4dcad7
+--- /dev/null
++++ b/configs/ice_evb_c910_defconfig
+@@ -0,0 +1,32 @@
++CONFIG_RISCV=y
++CONFIG_ENV_SIZE=0x20000
++CONFIG_NR_DRAM_BANKS=1
++CONFIG_TARGET_ICE_C910=y
++CONFIG_SYS_PROMPT="C910 # "
++CONFIG_ARCH_RV64I=y
++CONFIG_RISCV_SMODE=y
++CONFIG_DISTRO_DEFAULTS=y
++CONFIG_FIT=y
++CONFIG_DEFAULT_DEVICE_TREE="ice-c910"
++CONFIG_DISPLAY_CPUINFO=y
++CONFIG_DISPLAY_BOARDINFO=y
++CONFIG_OF_PRIOR_STAGE=y
++CONFIG_SYS_RELOC_GD_ENV_ADDR=y
++CONFIG_SYS_NS16550=y
++# CONFIG_EFI_LOADER is not set
++# CONFIG_PARTITIONS is not set
++CONFIG_OF_CONTROL=y
++CONFIG_CLK=y
++CONFIG_DM_MMC=y
++CONFIG_MMC_DW=y
++CONFIG_MMC_DW_SNPS=y
++CONFIG_DM_ETH=y
++CONFIG_ETH_DESIGNWARE=y
++CONFIG_PPL=y
++CONFIG_SPL=y
++# CONFIG_SPL_FRAMEWORK is not set
++# CONFIG_SPL_OF_CONTROL is not set
++# CONFIG_SPL_SERIAL_SUPPORT is not set
++# CONFIG_SPL_TIMER is not set
++CONFIG_SPL_LOAD_FIT=y
++CONFIG_IS_ASICF=y
+-- 
+2.17.1
+

+ 6 - 1
recipes-bsp/u-boot/u-boot_%.bbappend

@@ -1,8 +1,13 @@
 FILESEXTRAPATHS_prepend := "${THISDIR}/files:"
 
-SRC_URI_append_freedom-u540 = " \
+SRC_URI_append_light = " \
             file://tftp-mmc-boot.txt \
            "
+
+SRC_URI_append_light = " \
+            file://ice_evb_c910_defconfig.patch \
+"
+
 SRC_URI_append_freedom-u540_sota = " file://uEnv.txt"
 
 DEPENDS_append_freedom-u540 = " u-boot-tools-native"

+ 0 - 4
recipes-core/sysvinit/sysvinit-inittab_%.bbappend

@@ -1,4 +0,0 @@
-do_install_append_freedom-u540() {
-    sed -i -e 's#/bin/start_getty#/sbin/getty#g' ${D}${sysconfdir}/inittab
-    sed -i '/tty1/d' ${D}${sysconfdir}/inittab
-}

+ 3 - 0
recipes-devtools/libtool/libtool-cross_%.bbappend

@@ -0,0 +1,3 @@
+FILESEXTRAPATHS_prepend := "${THISDIR}/libtool:"
+
+SRC_URI += "file://9999-fix-thead.patch"

+ 3 - 0
recipes-devtools/libtool/libtool-native_%.bbappend

@@ -0,0 +1,3 @@
+FILESEXTRAPATHS_prepend := "${THISDIR}/libtool:"
+
+SRC_URI += "file://9999-fix-thead.patch"

+ 12 - 0
recipes-devtools/libtool/libtool/9999-fix-thead.patch

@@ -0,0 +1,12 @@
+diff -Nur libtool-2.4.6/m4/libtool.m4 libtool-2.4.6-fix/m4/libtool.m4
+--- libtool-2.4.6/m4/libtool.m4	2020-09-16 12:50:36.486764205 +0000
++++ libtool-2.4.6-fix/m4/libtool.m4	2020-09-16 13:46:53.272622322 +0000
+@@ -2303,7 +2303,7 @@
+     mingw* | cegcc*) lt_sed_strip_eq='s|=\([[A-Za-z]]:\)|\1|g' ;;
+     *) lt_sed_strip_eq='s|=/|/|g' ;;
+   esac
+-  lt_search_path_spec=`$CC -print-search-dirs | awk $lt_awk_arg | $SED -e "s/^libraries://" -e $lt_sed_strip_eq`
++  lt_search_path_spec=`$CC -print-search-dirs | awk $lt_awk_arg | $SED -e "s/^libraries://" -e $lt_sed_strip_eq -e "s/lib\/\.\.\/lib64xthead\/lp64d/lib64xthead\/lp64d/g" -e "s/lp64d\/\.\.\/lib64xthead\/lp64d/lp64d/g" -e "s/lib64xthead\/lib64xthead/lib64xthead/g"`
+   case $lt_search_path_spec in
+   *\;*)
+     # if the path contains ";" then we assume it to be the separator

+ 3 - 0
recipes-devtools/libtool/libtool_%.bbappend

@@ -0,0 +1,3 @@
+FILESEXTRAPATHS_prepend := "${THISDIR}/libtool:"
+
+SRC_URI += "file://9999-fix-thead.patch"

+ 3 - 0
recipes-devtools/libtool/nativesdk-libtool_%.bbappend

@@ -0,0 +1,3 @@
+FILESEXTRAPATHS_prepend := "${THISDIR}/libtool:"
+
+SRC_URI += "file://9999-fix-thead.patch"

+ 42 - 0
recipes-devtools/meson/meson/0004-thead.patch

@@ -0,0 +1,42 @@
+diff -Nur meson-0.55.1/mesonbuild/compilers/mixins/elbrus.py meson-0.55.1-fix/mesonbuild/compilers/mixins/elbrus.py
+--- meson-0.55.1/mesonbuild/compilers/mixins/elbrus.py	2020-08-15 16:27:05.000000000 +0000
++++ meson-0.55.1-fix/mesonbuild/compilers/mixins/elbrus.py	2020-09-17 04:29:46.910396526 +0000
+@@ -43,6 +43,7 @@
+         os_env = os.environ.copy()
+         os_env['LC_ALL'] = 'C'
+         stdo = Popen_safe(self.exelist + ['--print-search-dirs'], env=os_env)[1]
++        stdo = stdo.replace("lib/../lib64xthead/", "lib64xthead").replace("lp64d/../lib64xthead/", "").replace("lib64xthead/lib64xthead/", "")
+         for line in stdo.split('\n'):
+             if line.startswith('libraries:'):
+                 # lcc does not include '=' in --print-search-dirs output. Also it could show nonexistent dirs.
+@@ -54,6 +55,7 @@
+         os_env = os.environ.copy()
+         os_env['LC_ALL'] = 'C'
+         stdo = Popen_safe(self.exelist + ['--print-search-dirs'], env=os_env)[1]
++        stdo = stdo.replace("lib/../lib64xthead/", "lib64xthead").replace("lp64d/../lib64xthead/", "").replace("lib64xthead/lib64xthead/", "")
+         for line in stdo.split('\n'):
+             if line.startswith('programs:'):
+                 # lcc does not include '=' in --print-search-dirs output.
+diff -Nur meson-0.55.1/mesonbuild/compilers/mixins/gnu.py meson-0.55.1-fix/mesonbuild/compilers/mixins/gnu.py
+--- meson-0.55.1/mesonbuild/compilers/mixins/gnu.py	2020-08-15 16:27:05.000000000 +0000
++++ meson-0.55.1-fix/mesonbuild/compilers/mixins/gnu.py	2020-09-17 04:30:31.621394648 +0000
+@@ -227,7 +227,7 @@
+         with self._build_wrapper('', env, extra_args=extra_args,
+                                  dependencies=None, mode='compile',
+                                  want_output=True) as p:
+-            stdo = p.stdo
++            stdo = p.stdo.replace("lib/../lib64xthead/", "lib64xthead").replace("lp64d/../lib64xthead/", "").replace("lib64xthead/lib64xthead/", "")
+         return stdo
+ 
+     def _split_fetch_real_dirs(self, pathstr: str) -> T.List[str]:
+diff -Nur meson-0.55.1/mesonbuild/environment.py meson-0.55.1-fix/mesonbuild/environment.py
+--- meson-0.55.1/mesonbuild/environment.py	2020-09-17 04:28:27.469399864 +0000
++++ meson-0.55.1-fix/mesonbuild/environment.py	2020-09-17 03:49:08.282498990 +0000
+@@ -1844,6 +1844,7 @@
+         p, out, _ = Popen_safe(comp.get_exelist() + ['-print-search-dirs'])
+         if p.returncode != 0:
+             raise mesonlib.MesonException('Could not calculate system search dirs')
++        out = out.replace("lib/../lib64xthead/", "lib64xthead").replace("lp64d/../lib64xthead/", "").replace("lib64xthead/lib64xthead/", "")
+         out = out.split('\n')[index].lstrip('libraries: =').split(':')
+         return [os.path.normpath(p) for p in out]
+ 

+ 3 - 0
recipes-devtools/meson/meson_%.bbappend

@@ -0,0 +1,3 @@
+FILESEXTRAPATHS_prepend := "${THISDIR}/meson:"
+
+SRC_URI += "file://0004-thead.patch"

+ 3 - 0
recipes-devtools/meson/nativesdk-meson_%.bbappend

@@ -0,0 +1,3 @@
+FILESEXTRAPATHS_prepend := "${THISDIR}/meson:"
+
+SRC_URI += "file://0004-thead.patch"

+ 0 - 821
recipes-kernel/linux/files/freedom-u540/0001-PCI-microsemi-Add-host-driver-for-Microsemi-PCIe-con.patch

@@ -1,821 +0,0 @@
-From 3e5cd0fb40635b75140d8cc3b38d66eaaefcf901 Mon Sep 17 00:00:00 2001
-From: Daire McNamara <daire.mcnamara@microchip.com>
-Date: Fri, 15 Feb 2019 16:24:24 +0000
-Subject: [PATCH 1/4] PCI: microsemi: Add host driver for Microsemi PCIe
- controller
-
-This patch adds support to the Microsemi/Microchip PolarFire
-PCIe controller when configured in host (Root Complex) mode.
-
-Signed-off-by: Daire McNamara <daire.mcnamara@microchip.com>
-Upstream-Status: Inappropriate [not author]
----
- drivers/pci/controller/Kconfig          |   8 +
- drivers/pci/controller/Makefile         |   1 +
- drivers/pci/controller/pcie-microsemi.c | 764 ++++++++++++++++++++++++
- 3 files changed, 773 insertions(+)
- create mode 100644 drivers/pci/controller/pcie-microsemi.c
-
-diff --git a/drivers/pci/controller/Kconfig b/drivers/pci/controller/Kconfig
-index fe9f9f13ce11..800b0b61dedf 100644
---- a/drivers/pci/controller/Kconfig
-+++ b/drivers/pci/controller/Kconfig
-@@ -281,5 +281,13 @@ config VMD
- 	  To compile this driver as a module, choose M here: the
- 	  module will be called vmd.
- 
-+config PCIE_MICROSEMI
-+	bool "Microsemi AXI PCIe host bridge support"
-+	depends on PCI_MSI && OF
-+	help
-+	  Say 'Y' here if you want kernel to support the Microsemi AXI PCIe
-+	  Host Bridge driver.
-+
-+
- source "drivers/pci/controller/dwc/Kconfig"
- endmenu
-diff --git a/drivers/pci/controller/Makefile b/drivers/pci/controller/Makefile
-index d56a507495c5..c3b76ff221be 100644
---- a/drivers/pci/controller/Makefile
-+++ b/drivers/pci/controller/Makefile
-@@ -28,6 +28,7 @@ obj-$(CONFIG_PCIE_ROCKCHIP_HOST) += pcie-rockchip-host.o
- obj-$(CONFIG_PCIE_MEDIATEK) += pcie-mediatek.o
- obj-$(CONFIG_PCIE_MOBIVEIL) += pcie-mobiveil.o
- obj-$(CONFIG_PCIE_TANGO_SMP8759) += pcie-tango.o
-+obj-$(CONFIG_PCIE_MICROSEMI) += pcie-microsemi.o
- obj-$(CONFIG_VMD) += vmd.o
- # pcie-hisi.o quirks are needed even without CONFIG_PCIE_DW
- obj-y				+= dwc/
-diff --git a/drivers/pci/controller/pcie-microsemi.c b/drivers/pci/controller/pcie-microsemi.c
-new file mode 100644
-index 000000000000..60e185bebc60
---- /dev/null
-+++ b/drivers/pci/controller/pcie-microsemi.c
-@@ -0,0 +1,764 @@
-+// SPDX-License-Identifier: GPL-2.0+
-+/*
-+ * PCIe host controller driver for Microsemi AXI PCIe Bridge
-+ *
-+ * Copyright (c) 2018 - 2019 Microsemi Corporation.
-+ *
-+ * Based on:
-+ *	pcie-rcar.c
-+ *	pcie-xilinx.c
-+ *	pcie-altera.c
-+ */
-+
-+#include <linux/bitmap.h>
-+#include <linux/interrupt.h>
-+#include <linux/irq.h>
-+#include <linux/irqdomain.h>
-+#include <linux/kernel.h>
-+#include <linux/init.h>
-+#include <linux/msi.h>
-+#include <linux/of_address.h>
-+#include <linux/of_pci.h>
-+#include <linux/of_platform.h>
-+#include <linux/of_irq.h>
-+#include <linux/pci.h>
-+#include <linux/platform_device.h>
-+
-+#include "../pci.h"
-+
-+/* ECAM definitions */
-+#define ECAM_BUS_NUM_SHIFT		20
-+#define ECAM_DEV_NUM_SHIFT		12
-+
-+/* Number of MSI IRQs */
-+#define MICROSEMI_NUM_MSI_IRQS		32
-+#define MICROSEMI_NUM_MSI_IRQS_CODED	 5
-+
-+/* PCIe Bridge Phy and Controller Phy offsets */
-+#define MICROSEMI_PCIE0_BRIDGE_ADDR	0x00004000u
-+#define MICROSEMI_PCIE0_CTRL_ADDR	0x00006000u
-+
-+#define MICROSEMI_PCIE1_BRIDGE_ADDR	0x00008000u
-+#define MICROSEMI_PCIE1_CTRL_ADDR	0x0000a000u
-+
-+/* PCIe Controller Phy Regs */
-+#define MICROSEMI_SEC_ERROR_INT			0x28
-+#define SEC_ERROR_INT_TX_RAM_SEC_ERR_INT	GENMASK(3, 0)
-+#define SEC_ERROR_INT_RX_RAM_SEC_ERR_INT	GENMASK(7, 4)
-+#define SEC_ERROR_INT_PCIE2AXI_RAM_SEC_ERR_INT	GENMASK(11, 8)
-+#define SEC_ERROR_INT_AXI2PCIE_RAM_SEC_ERR_INT	GENMASK(15, 12)
-+#define MICROSEMI_SEC_ERROR_INT_MASK		0x2c
-+#define MICROSEMI_DED_ERROR_INT			0x30
-+#define DED_ERROR_INT_TX_RAM_DED_ERR_INT	GENMASK(3, 0)
-+#define DED_ERROR_INT_RX_RAM_DED_ERR_INT	GENMASK(7, 4)
-+#define DED_ERROR_INT_PCIE2AXI_RAM_DED_ERR_INT	GENMASK(11, 8)
-+#define DED_ERROR_INT_AXI2PCIE_RAM_DED_ERR_INT	GENMASK(15, 12)
-+#define MICROSEMI_DED_ERROR_INT_MASK		0x34
-+#define MICROSEMI_ECC_CONTROL			0x38
-+#define ECC_CONTROL_AXI2PCIE_RAM_ECC_BYPASS	BIT(27)
-+#define ECC_CONTROL_PCIE2AXI_RAM_ECC_BYPASS	BIT(26)
-+#define ECC_CONTROL_RX_RAM_ECC_BYPASS		BIT(25)
-+#define ECC_CONTROL_TX_RAM_ECC_BYPASS		BIT(24)
-+#define MICROSEMI_LTSSM_STATE			0x5c
-+#define MICROSEMI_LTSSM_L0_STATE		0x10
-+#define MICROSEMI_PCIE_EVENT_INT		0x14c
-+#define PCIE_EVENT_INT_L2_EXIT_INT		BIT(0)
-+#define PCIE_EVENT_INT_HOTRST_EXIT_INT		BIT(1)
-+#define PCIE_EVENT_INT_DLUP_EXIT_INT		BIT(2)
-+#define PCIE_EVENT_INT_L2_EXIT_INT_MASK		BIT(16)
-+#define PCIE_EVENT_INT_HOTRST_EXIT_INT_MASK	BIT(17)
-+#define PCIE_EVENT_INT_DLUP_EXIT_INT_MASK	BIT(18)
-+
-+/* PCIe Bridge Phy Regs */
-+#define MICROSEMI_PCIE_PCI_IDS_DW1		0x9c
-+#define MICROSEMI_IMASK_LOCAL			0x180
-+#define MICROSEMI_PCIE_LOCAL_INT_ENABLE		0x0f000000u
-+#define MICROSEMI_PCI_INTS			0x0f000000u
-+#define MICROSEMI_PM_MSI_INT_SHIFT		24
-+#define MICROSEMI_PCIE_ENABLE_MSI		0x10000000u
-+#define MICROSEMI_MSI_INT			0x10000000u
-+#define MICROSEMI_MSI_INT_SHIFT			28
-+#define MICROSEMI_ISTATUS_LOCAL			0x184
-+#define MICROSEMI_IMASK_HOST			0x188
-+#define MICROSEMI_ISTATUS_HOST			0x18c
-+#define MICROSEMI_ISTATUS_MSI			0x194
-+
-+/* PCIe AXI slave table init defines */
-+#define MICROSEMI_ATR0_AXI4_SLV0_SRCADDR_PARAM	0x800u
-+#define ATR_SIZE_SHIFT				1
-+#define ATR_IMPL_ENABLE				1
-+#define MICROSEMI_ATR0_AXI4_SLV0_SRC_ADDR	0x804u
-+#define MICROSEMI_ATR0_AXI4_SLV0_TRSL_ADDR_LSB	0x808u
-+#define MICROSEMI_ATR0_AXI4_SLV0_TRSL_ADDR_UDW	0x80cu
-+#define MICROSEMI_ATR0_AXI4_SLV0_TRSL_PARAM	0x810u
-+#define MICROSEMI_PCIE_TX_RX_INTERFACE		0x00000000u
-+#define MICROSEMI_PCIE_CONFIG_INTERFACE		0x00000001u
-+
-+#define MICROSEMI_ATR0_AXI4_SLV_SIZE		32
-+
-+/* PCIe Master table init defines */
-+#define MICROSEMI_ATR0_PCIE_WIN0_SRCADDR_31_12	0x600u
-+#define MICROSEMI_ATR0_PCIE_WIN0_SIZE		0x1f
-+#define MICROSEMI_ATR0_PCIE_WIN0_SIZE_SHIFT	1
-+#define MICROSEMI_ATR0_PCIE_WIN0_SRCADDR_63_32	0x604u
-+
-+#define MICROSEMI_MSI_MSG_ADDR			0x190u
-+
-+/* PCIe Config space MSI capability structure */
-+#define MSI_CAP_CTRL_OFFSET		0xe0u
-+#define MSI_ENABLE			(0x01u << 16)
-+#define MSI_ENABLE_MULTI		(MICROSEMI_NUM_MSI_IRQS_CODED << 20)
-+#define MSI_MSG_ADDR_OFFSET		0xe4u
-+#define MSI_MSG_UPPER_ADDR_OFFSET	0xe8u
-+#define MSI_MSG_DATA_OFFSET		0xf0u
-+
-+/**
-+ * struct microsemi_pcie_port - PCIe port information
-+ * @pcie_base_addr: IO Mapped Register Base
-+ * @axi_base_addr: AMBA Mapped Register Base
-+ * @irq: Interrupt number
-+ * @root_busno: Root Bus number
-+ * @dev: Device pointer
-+ * @msi_domain: MSI IRQ domain pointer
-+ * @leg_domain: Legacy IRQ domain pointer
-+ * @resources: Bus Resources
-+ */
-+struct microsemi_pcie_port {
-+	struct platform_device *pdev;
-+	void __iomem *pcie_base_addr;
-+	void __iomem *axi_base_addr;
-+	void __iomem *bridge_base_addr;
-+	void __iomem *ctrl_base_addr;
-+	int bridge;
-+	u32 irq;
-+	u8 root_busno;
-+	struct device *dev;
-+	struct irq_domain *msi_domain;
-+	struct irq_domain *leg_domain;
-+	struct list_head resources;
-+	struct mutex lock;			/* protect bitmap variable */
-+	DECLARE_BITMAP(msi_irq_in_use, MICROSEMI_NUM_MSI_IRQS);
-+};
-+
-+static inline u32 pcie_read(struct microsemi_pcie_port *port, u32 reg)
-+{
-+	return readl(port->pcie_base_addr + reg);
-+}
-+
-+static inline void pcie_write(struct microsemi_pcie_port *port,
-+			      u32 val, u32 reg)
-+{
-+	writel(val, port->pcie_base_addr + reg);
-+}
-+
-+static void microsemi_pcie_enable(struct microsemi_pcie_port *port)
-+{
-+	u32 enb;
-+
-+	enb = readl(port->bridge_base_addr + MICROSEMI_LTSSM_STATE);
-+	enb |= MICROSEMI_LTSSM_L0_STATE;
-+	writel(enb, port->bridge_base_addr + MICROSEMI_LTSSM_STATE);
-+}
-+
-+/**
-+ * microsemi_pcie_valid_device - Check if a valid device is present on bus
-+ * @bus: PCI Bus structure
-+ * @devfn: device/function
-+ *
-+ * Return: 'true' on success and 'false' if invalid device is found
-+ */
-+static bool microsemi_pcie_valid_device(struct pci_bus *bus, unsigned int devfn)
-+{
-+	struct microsemi_pcie_port *port = bus->sysdata;
-+
-+	/* Only one device down on each root port */
-+	if (bus->number == port->root_busno && devfn > 0)
-+		return false;
-+
-+	return true;
-+}
-+
-+/**
-+ * microsemi_pcie_map_bus - Get configuration base
-+ * @bus: PCI Bus structure
-+ * @devfn: Device/function
-+ * @where: Offset from base
-+ *
-+ * Return: Base address of the configuration space needed to be
-+ *	 accessed.
-+ */
-+static void __iomem *microsemi_pcie_map_bus(struct pci_bus *bus,
-+					    unsigned int devfn, int where)
-+{
-+	struct microsemi_pcie_port *port = bus->sysdata;
-+	int relbus;
-+
-+	if (!microsemi_pcie_valid_device(bus, devfn))
-+		return NULL;
-+
-+	relbus = (bus->number << ECAM_BUS_NUM_SHIFT) |
-+		(devfn << ECAM_DEV_NUM_SHIFT);
-+
-+	return port->pcie_base_addr + relbus + where;
-+}
-+
-+/* PCIe operations */
-+static struct pci_ops microsemi_pcie_ops = {
-+	.map_bus = microsemi_pcie_map_bus,
-+	.read	= pci_generic_config_read,
-+	.write	= pci_generic_config_write,
-+};
-+
-+/* MSI functions */
-+
-+/**
-+ * microsemi_pcie_destroy_msi - Free MSI number
-+ * @irq: IRQ to be freed
-+ */
-+static void microsemi_pcie_destroy_msi(unsigned int irq)
-+{
-+	struct microsemi_pcie_port *port =
-+		msi_desc_to_pci_sysdata(irq_get_msi_desc(irq));
-+	irq_hw_number_t hwirq = irqd_to_hwirq(irq_get_irq_data(irq));
-+
-+	if (!port)
-+		return;
-+
-+	if (!test_bit(hwirq, port->msi_irq_in_use))
-+		dev_err(port->dev, "trying to free unused MSI%d\n", irq);
-+	else
-+		clear_bit(hwirq, port->msi_irq_in_use);
-+}
-+
-+/**
-+ * microsemi_pcie_assign_msi - Allocate MSI number
-+ *
-+ * Return: A valid IRQ on success and error value on failure.
-+ */
-+static int microsemi_pcie_assign_msi(struct microsemi_pcie_port *port)
-+{
-+	int pos;
-+
-+	mutex_lock(&port->lock);
-+	pos = find_first_zero_bit(port->msi_irq_in_use, MICROSEMI_NUM_MSI_IRQS);
-+	if (pos < MICROSEMI_NUM_MSI_IRQS) {
-+		set_bit(pos, port->msi_irq_in_use);
-+	} else {
-+		mutex_unlock(&port->lock);
-+		return -ENOSPC;
-+	}
-+
-+	mutex_unlock(&port->lock);
-+	return pos;
-+}
-+
-+/**
-+ * microsemi_msi_teardown_irq - Destroy the MSI
-+ * @chip: MSI Chip descriptor
-+ * @irq: MSI IRQ to destroy
-+ */
-+static void microsemi_msi_teardown_irq(struct msi_controller *chip,
-+				       unsigned int irq)
-+{
-+	microsemi_pcie_destroy_msi(irq);
-+	irq_dispose_mapping(irq);
-+}
-+
-+/**
-+ * microsemi_pcie_msi_setup_irq - Setup MSI request
-+ * @chip: MSI chip pointer
-+ * @pdev: PCIe device pointer
-+ * @desc: MSI descriptor pointer
-+ *
-+ * Return: '0' on success and error value on failure
-+ */
-+static int microsemi_pcie_msi_setup_irq(struct msi_controller *chip,
-+					struct pci_dev *pdev,
-+					struct msi_desc *desc)
-+{
-+	struct microsemi_pcie_port *port = pdev->bus->sysdata;
-+	unsigned int irq;
-+	int hwirq;
-+	struct msi_msg msg;
-+
-+	hwirq = microsemi_pcie_assign_msi(port);
-+	if (hwirq < 0)
-+		return hwirq;
-+
-+	irq = irq_create_mapping(port->msi_domain, hwirq);
-+	if (!irq)
-+		return -EINVAL;
-+
-+	irq_set_msi_desc(irq, desc);
-+
-+	msg.address_hi = upper_32_bits(MICROSEMI_MSI_MSG_ADDR);
-+	msg.address_lo = lower_32_bits(MICROSEMI_MSI_MSG_ADDR);
-+	msg.data = hwirq;
-+
-+	pci_write_msi_msg(irq, &msg);
-+
-+	return 0;
-+}
-+
-+/* MSI Chip Descriptor */
-+static struct msi_controller microsemi_pcie_msi_chip = {
-+	.setup_irq = microsemi_pcie_msi_setup_irq,
-+	.teardown_irq = microsemi_msi_teardown_irq,
-+};
-+
-+/* HW Interrupt Chip Descriptor */
-+static struct irq_chip microsemi_msi_irq_chip = {
-+	.name = "Microsemi PCIe MSI",
-+	.irq_enable = pci_msi_unmask_irq,
-+	.irq_disable = pci_msi_mask_irq,
-+	.irq_mask = pci_msi_mask_irq,
-+	.irq_unmask = pci_msi_unmask_irq,
-+};
-+
-+/**
-+ * microsemi_pcie_msi_map - Set the handler for the MSI and mark IRQ as valid
-+ * @domain: IRQ domain
-+ * @irq: Virtual IRQ number
-+ * @hwirq: HW interrupt number
-+ *
-+ * Return: Always returns 0.
-+ */
-+static int microsemi_pcie_msi_map(struct irq_domain *domain, unsigned int irq,
-+				  irq_hw_number_t hwirq)
-+{
-+	irq_set_chip_and_handler(irq, &microsemi_msi_irq_chip,
-+				 handle_simple_irq);
-+	irq_set_chip_data(irq, domain->host_data);
-+
-+	return 0;
-+}
-+
-+/* IRQ Domain operations */
-+static const struct irq_domain_ops msi_domain_ops = {
-+	.map = microsemi_pcie_msi_map,
-+};
-+
-+/**
-+ * microsemi_pcie_enable_msi - Enable MSI support
-+ * @port: PCIe port information
-+ */
-+static void microsemi_pcie_enable_msi(struct microsemi_pcie_port *port)
-+{
-+	u32 cap_ctrl;
-+
-+	cap_ctrl = pcie_read(port, MSI_CAP_CTRL_OFFSET);
-+
-+	pcie_write(port, cap_ctrl | MSI_ENABLE_MULTI |
-+		MSI_ENABLE, MSI_CAP_CTRL_OFFSET);
-+	pcie_write(port, MICROSEMI_MSI_MSG_ADDR, MSI_MSG_ADDR_OFFSET);
-+}
-+
-+/* INTx Functions */
-+
-+/**
-+ * microsemi_pcie_intx_map - Set the handler for the INTx and mark IRQ as valid
-+ * @domain: IRQ domain
-+ * @irq: Virtual IRQ number
-+ * @hwirq: HW interrupt number
-+ *
-+ * Return: Always returns 0.
-+ */
-+static int microsemi_pcie_intx_map(struct irq_domain *domain, unsigned int irq,
-+				   irq_hw_number_t hwirq)
-+{
-+	irq_set_chip_and_handler(irq, &dummy_irq_chip, handle_simple_irq);
-+	irq_set_chip_data(irq, domain->host_data);
-+
-+	return 0;
-+}
-+
-+/* INTx IRQ Domain operations */
-+static const struct irq_domain_ops intx_domain_ops = {
-+	.map = microsemi_pcie_intx_map,
-+	.xlate = pci_irqd_intx_xlate,
-+};
-+
-+/* PCIe HW Functions */
-+
-+/**
-+ * microsemi_pcie_intr_handler - Interrupt Service Handler
-+ * @irq: IRQ number
-+ * @data: PCIe port information
-+ *
-+ * Return: IRQ_HANDLED on success and IRQ_NONE on failure
-+ */
-+static irqreturn_t microsemi_pcie_intr_handler(int irq, void *data)
-+{
-+	struct microsemi_pcie_port *port = (struct microsemi_pcie_port *)data;
-+	struct device *dev = port->dev;
-+	unsigned long status;
-+	unsigned long msi;
-+	u32 bit;
-+	u32 virq;
-+
-+	status = readl(port->bridge_base_addr + MICROSEMI_ISTATUS_LOCAL);
-+
-+	/* Might be sharing interrupt line.  Check if interrupt is for us */
-+	if (!status)
-+		return IRQ_NONE;
-+
-+	status = (status & MICROSEMI_PCI_INTS) >> MICROSEMI_PM_MSI_INT_SHIFT;
-+	for_each_set_bit(bit, &status, PCI_NUM_INTX) {
-+		/* clear that interrupt bit */
-+		writel(1 << (bit + MICROSEMI_PM_MSI_INT_SHIFT),
-+		       port->bridge_base_addr + MICROSEMI_ISTATUS_LOCAL);
-+		virq = irq_find_mapping(port->leg_domain, bit);
-+
-+		if (virq)
-+			generic_handle_irq(virq);
-+		else
-+			dev_err(dev, "unexpected IRQ, INT%d\n", bit);
-+	}
-+
-+	status = readl(port->bridge_base_addr + MICROSEMI_ISTATUS_LOCAL);
-+	if (status & MICROSEMI_MSI_INT) {
-+		/* Clear the ISTATUS MSI bit */
-+		writel((1 << MICROSEMI_MSI_INT_SHIFT),
-+		       port->bridge_base_addr + MICROSEMI_ISTATUS_LOCAL);
-+		msi = readl(port->bridge_base_addr + MICROSEMI_ISTATUS_MSI);
-+		for_each_set_bit(bit, &msi, MICROSEMI_NUM_MSI_IRQS) {
-+			/* clear that MSI interrupt bit */
-+			writel((1 << bit),
-+			       port->bridge_base_addr + MICROSEMI_ISTATUS_MSI);
-+			virq = irq_find_mapping(port->msi_domain, bit);
-+			if (virq)
-+				generic_handle_irq(virq);
-+			else
-+				dev_err(dev, "unexpected IRQ, INT%d\n", bit);
-+		}
-+	}
-+
-+	return IRQ_HANDLED;
-+}
-+
-+/**
-+ * microsemi_pcie_init_irq_domain - Initialize IRQ domain
-+ * @port: PCIe port information
-+ *
-+ * Return: '0' on success and error value on failure
-+ */
-+static int microsemi_pcie_init_irq_domain(struct microsemi_pcie_port *port)
-+{
-+	struct device *dev = port->dev;
-+	struct device_node *node = dev->of_node;
-+	struct device_node *pcie_intc_node;
-+
-+	/* Setup INTx */
-+	pcie_intc_node = of_get_next_child(node, NULL);
-+	if (!pcie_intc_node) {
-+		dev_err(dev, "no PCIe INTx node found\n");
-+		return -ENODEV;
-+	}
-+
-+	port->leg_domain = irq_domain_add_linear(pcie_intc_node, PCI_NUM_INTX,
-+						 &intx_domain_ops,
-+						 port);
-+	if (!port->leg_domain) {
-+		dev_err(dev, "failed to get a INTx IRQ domain\n");
-+		return -ENODEV;
-+	}
-+
-+	/* Setup MSI */
-+	if (IS_ENABLED(CONFIG_PCI_MSI)) {
-+		port->msi_domain =
-+			irq_domain_add_linear(node,
-+					      MICROSEMI_NUM_MSI_IRQS,
-+					      &msi_domain_ops,
-+					      &microsemi_pcie_msi_chip);
-+		if (!port->msi_domain) {
-+			dev_err(dev, "failed to get an MSI IRQ domain\n");
-+			return -ENODEV;
-+		}
-+		microsemi_pcie_enable_msi(port);
-+	}
-+
-+	/* Enable interrupts */
-+	writel(MICROSEMI_PCIE_ENABLE_MSI | MICROSEMI_PCIE_LOCAL_INT_ENABLE,
-+	       port->bridge_base_addr + MICROSEMI_IMASK_LOCAL);
-+
-+	return 0;
-+}
-+
-+/**
-+ * microsemi_pcie_init_port - Parse Device tree, Initialize hardware
-+ * @port: PCIe port information
-+ *
-+ * Return: '0' on success and error value on failure
-+ */
-+static int microsemi_pcie_init_port(struct microsemi_pcie_port *port)
-+{
-+	struct device *dev = port->dev;
-+	struct device_node *node = dev->of_node;
-+	struct of_pci_range_parser parser;
-+	struct of_pci_range range;
-+	struct resource regs;
-+	struct resource regs1;
-+	resource_size_t size;
-+	u32 atr_sz;
-+	const char *type;
-+	int err;
-+	u32 val;
-+	int index = 1;
-+
-+	type = of_get_property(node, "device_type", NULL);
-+	if (!type || strcmp(type, "pci")) {
-+		dev_err(dev, "invalid \"device_type\" %s\n", type);
-+		return -EINVAL;
-+	}
-+
-+	/* Only supporting bridge 1 */
-+	port->bridge = 1;
-+
-+	mutex_init(&port->lock);
-+
-+	err = of_address_to_resource(node, 0, &regs);
-+	if (err) {
-+		dev_err(dev, "missing \"reg\" property\n");
-+		return err;
-+	}
-+
-+	port->pcie_base_addr = devm_pci_remap_cfg_resource(dev, &regs);
-+	if (IS_ERR(port->pcie_base_addr))
-+		return PTR_ERR(port->pcie_base_addr);
-+
-+	err = of_address_to_resource(node, 1, &regs1);
-+	if (err) {
-+		dev_err(dev, "missing \"reg\" property\n");
-+		return err;
-+	}
-+
-+	port->axi_base_addr = devm_ioremap_resource(dev, &regs1);
-+	if (IS_ERR(port->axi_base_addr))
-+		return PTR_ERR(port->axi_base_addr);
-+
-+	if (port->bridge == 0) {
-+		port->bridge_base_addr = port->axi_base_addr
-+			+ MICROSEMI_PCIE0_BRIDGE_ADDR;
-+		port->ctrl_base_addr = port->axi_base_addr
-+			+ MICROSEMI_PCIE0_CTRL_ADDR;
-+	} else {
-+		port->bridge_base_addr = port->axi_base_addr
-+			+ MICROSEMI_PCIE1_BRIDGE_ADDR;
-+		port->ctrl_base_addr = port->axi_base_addr
-+			+ MICROSEMI_PCIE1_CTRL_ADDR;
-+	}
-+
-+	port->irq = irq_of_parse_and_map(node, 0);
-+
-+	err = devm_request_irq(dev, port->irq, microsemi_pcie_intr_handler,
-+			       IRQF_SHARED | IRQF_NO_THREAD,
-+			       "microsemi-pcie", port);
-+	if (err) {
-+		dev_err(dev, "unable to request IRQ%d\n", port->irq);
-+		return err;
-+	}
-+
-+	microsemi_pcie_enable(port);
-+
-+	/* Clear and Disable interrupts */
-+	val = ECC_CONTROL_AXI2PCIE_RAM_ECC_BYPASS
-+		| ECC_CONTROL_PCIE2AXI_RAM_ECC_BYPASS
-+		| ECC_CONTROL_RX_RAM_ECC_BYPASS
-+		| ECC_CONTROL_TX_RAM_ECC_BYPASS;
-+	writel(val, port->ctrl_base_addr + MICROSEMI_ECC_CONTROL);
-+
-+	val = PCIE_EVENT_INT_L2_EXIT_INT
-+		| PCIE_EVENT_INT_HOTRST_EXIT_INT
-+		| PCIE_EVENT_INT_DLUP_EXIT_INT
-+		| PCIE_EVENT_INT_L2_EXIT_INT_MASK
-+		| PCIE_EVENT_INT_HOTRST_EXIT_INT_MASK
-+		| PCIE_EVENT_INT_DLUP_EXIT_INT_MASK;
-+	writel(val, port->ctrl_base_addr + MICROSEMI_PCIE_EVENT_INT);
-+
-+	val = SEC_ERROR_INT_TX_RAM_SEC_ERR_INT
-+		| SEC_ERROR_INT_RX_RAM_SEC_ERR_INT
-+		| SEC_ERROR_INT_PCIE2AXI_RAM_SEC_ERR_INT
-+		| SEC_ERROR_INT_AXI2PCIE_RAM_SEC_ERR_INT;
-+	writel(val, port->ctrl_base_addr + MICROSEMI_SEC_ERROR_INT);
-+	writel(val, port->ctrl_base_addr + MICROSEMI_SEC_ERROR_INT_MASK);
-+
-+	val = DED_ERROR_INT_TX_RAM_DED_ERR_INT
-+		| DED_ERROR_INT_RX_RAM_DED_ERR_INT
-+		| DED_ERROR_INT_PCIE2AXI_RAM_DED_ERR_INT
-+		| DED_ERROR_INT_AXI2PCIE_RAM_DED_ERR_INT;
-+	writel(val, port->ctrl_base_addr + MICROSEMI_DED_ERROR_INT);
-+	writel(val, port->ctrl_base_addr + MICROSEMI_DED_ERROR_INT_MASK);
-+
-+	writel(0x00000000, port->bridge_base_addr + MICROSEMI_IMASK_LOCAL);
-+	writel(GENMASK(31, 0),
-+	       port->bridge_base_addr + MICROSEMI_ISTATUS_LOCAL);
-+	writel(0x00000000, port->bridge_base_addr + MICROSEMI_IMASK_HOST);
-+	writel(GENMASK(31, 0), port->bridge_base_addr + MICROSEMI_ISTATUS_HOST);
-+
-+	/* Configure Address Translation Table 0 for PCIe config space */
-+	writel(MICROSEMI_PCIE_CONFIG_INTERFACE,
-+	       port->bridge_base_addr + MICROSEMI_ATR0_AXI4_SLV0_TRSL_PARAM);
-+
-+	size = resource_size(&regs);
-+
-+	atr_sz = find_first_bit((const unsigned long *)&size, 64) - 1;
-+
-+	writel(lower_32_bits(regs.start)
-+		| atr_sz << ATR_SIZE_SHIFT | ATR_IMPL_ENABLE,
-+		port->bridge_base_addr
-+		+ MICROSEMI_ATR0_AXI4_SLV0_SRCADDR_PARAM);
-+
-+	writel(lower_32_bits(regs.start),
-+	       port->bridge_base_addr + MICROSEMI_ATR0_AXI4_SLV0_TRSL_ADDR_LSB);
-+
-+	if (of_pci_range_parser_init(&parser, node)) {
-+		dev_err(dev, "missing \"ranges\" property\n");
-+		return -EINVAL;
-+	}
-+
-+	for_each_of_pci_range(&parser, &range) {
-+		switch (range.flags & IORESOURCE_TYPE_BITS) {
-+		case IORESOURCE_MEM:
-+			size = range.size;
-+			atr_sz =
-+				find_first_bit((const unsigned long *)&size, 64)
-+				- 1;
-+
-+			/* Configure Address Translation Table index for PCIe
-+			 * mem space
-+			 */
-+			writel(MICROSEMI_PCIE_TX_RX_INTERFACE,
-+			       port->bridge_base_addr
-+				+ (index * MICROSEMI_ATR0_AXI4_SLV_SIZE)
-+				+ MICROSEMI_ATR0_AXI4_SLV0_TRSL_PARAM);
-+
-+			writel(lower_32_bits(range.cpu_addr)
-+				| (atr_sz << ATR_SIZE_SHIFT)
-+				| ATR_IMPL_ENABLE,
-+				port->bridge_base_addr
-+				+ (index * MICROSEMI_ATR0_AXI4_SLV_SIZE)
-+				+ MICROSEMI_ATR0_AXI4_SLV0_SRCADDR_PARAM);
-+
-+			writel(lower_32_bits(range.pci_addr),
-+			       port->bridge_base_addr
-+				+ (index * MICROSEMI_ATR0_AXI4_SLV_SIZE)
-+				+ MICROSEMI_ATR0_AXI4_SLV0_TRSL_ADDR_LSB);
-+
-+			break;
-+		}
-+		index++;
-+	}
-+
-+	writel(readl(port->bridge_base_addr
-+		+ MICROSEMI_ATR0_PCIE_WIN0_SRCADDR_31_12)
-+		| (MICROSEMI_ATR0_PCIE_WIN0_SIZE
-+		<< MICROSEMI_ATR0_PCIE_WIN0_SIZE_SHIFT),
-+		port->bridge_base_addr +
-+		MICROSEMI_ATR0_PCIE_WIN0_SRCADDR_31_12);
-+
-+	writel(0x0,
-+	       port->bridge_base_addr + MICROSEMI_ATR0_PCIE_WIN0_SRCADDR_63_32);
-+
-+	writel((readl(port->bridge_base_addr + MICROSEMI_PCIE_PCI_IDS_DW1)
-+		& 0xffff)
-+		| (PCI_CLASS_BRIDGE_PCI << 16),
-+		port->bridge_base_addr + MICROSEMI_PCIE_PCI_IDS_DW1);
-+
-+	return 0;
-+}
-+
-+/**
-+ * microsemi_pcie_probe - Probe function
-+ * @pdev: Platform device pointer
-+ *
-+ * Return: '0' on success and error value on failure
-+ */
-+static int microsemi_pcie_probe(struct platform_device *pdev)
-+{
-+	struct device *dev = &pdev->dev;
-+	struct microsemi_pcie_port *port;
-+	struct pci_bus *bus, *child;
-+	struct pci_host_bridge *bridge;
-+	int err;
-+	resource_size_t iobase = 0;
-+	LIST_HEAD(res);
-+
-+	if (!dev->of_node)
-+		return -ENODEV;
-+
-+	bridge = devm_pci_alloc_host_bridge(dev, sizeof(*port));
-+	if (!bridge)
-+		return -ENODEV;
-+
-+	port = pci_host_bridge_priv(bridge);
-+
-+	port->dev = dev;
-+	port->pdev = pdev;
-+
-+	err = microsemi_pcie_init_port(port);
-+	if (err) {
-+		dev_err(dev, "PCIe port initialization failed\n");
-+		return err;
-+	}
-+
-+	err = microsemi_pcie_init_irq_domain(port);
-+	if (err) {
-+		dev_err(dev, "failed creating IRQ domain\n");
-+		return err;
-+	}
-+
-+	err = devm_of_pci_get_host_bridge_resources(dev, 0, 0xff, &res,
-+						    &iobase);
-+	if (err) {
-+		dev_err(dev, "getting bridge resources failed\n");
-+		return err;
-+	}
-+
-+	err = devm_request_pci_bus_resources(dev, &res);
-+	if (err)
-+		goto error;
-+
-+	list_splice_init(&res, &bridge->windows);
-+	bridge->dev.parent = dev;
-+	bridge->sysdata = port;
-+	bridge->busnr = 0;
-+	bridge->ops = &microsemi_pcie_ops;
-+	bridge->map_irq = of_irq_parse_and_map_pci;
-+	bridge->swizzle_irq = pci_common_swizzle;
-+
-+#ifdef CONFIG_PCI_MSI
-+	microsemi_pcie_msi_chip.dev = dev;
-+	bridge->msi = &microsemi_pcie_msi_chip;
-+#endif
-+	err = pci_scan_root_bus_bridge(bridge);
-+	if (err < 0)
-+		goto error;
-+
-+	bus = bridge->bus;
-+
-+	pci_assign_unassigned_bus_resources(bus);
-+	list_for_each_entry(child, &bus->children, node)
-+		pcie_bus_configure_settings(child);
-+	pci_bus_add_devices(bus);
-+
-+	return 0;
-+
-+error:
-+	pci_free_resource_list(&res);
-+	return err;
-+}
-+
-+static const struct of_device_id microsemi_pcie_of_match[] = {
-+	{ .compatible = "microsemi,ms-pf-axi-pcie-host", },
-+	{}
-+};
-+
-+static struct platform_driver microsemi_pcie_driver = {
-+	.driver = {
-+		.name = "microsemi-pcie",
-+		.of_match_table = microsemi_pcie_of_match,
-+		.suppress_bind_attrs = true,
-+	},
-+	.probe = microsemi_pcie_probe,
-+};
-+builtin_platform_driver(microsemi_pcie_driver);
--- 
-2.22.0
-

+ 0 - 50
recipes-kernel/linux/files/freedom-u540/0002-Microsemi-PCIe-expansion-board-DT-entry.patch

@@ -1,50 +0,0 @@
-From b1103ea299e49c03555f12f080a1607969fd7e66 Mon Sep 17 00:00:00 2001
-From: Atish Patra <atish.patra@wdc.com>
-Date: Fri, 21 Jun 2019 12:36:21 -0700
-Subject: [PATCH 2/4] Microsemi PCIe expansion board DT entry.
-
-Signed-off-by: Atish Patra <atish.patra@wdc.com>
-Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
-Upstream-Status: Inappropriate [enable feature]
----
- .../sifive/hifive-unleashed-a00-microsemi.dts | 28 +++++++++++++++++++
- 1 file changed, 28 insertions(+)
- create mode 100644 arch/riscv/boot/dts/sifive/hifive-unleashed-a00-microsemi.dts
-
-diff --git a/arch/riscv/boot/dts/sifive/hifive-unleashed-a00-microsemi.dts b/arch/riscv/boot/dts/sifive/hifive-unleashed-a00-microsemi.dts
-new file mode 100644
-index 000000000000..4d25606f4e0c
---- /dev/null
-+++ b/arch/riscv/boot/dts/sifive/hifive-unleashed-a00-microsemi.dts
-@@ -0,0 +1,28 @@
-+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-+
-+#include "hifive-unleashed-a00.dts"
-+
-+/ {
-+	soc {
-+		pcie: pcie@2030000000 {
-+			#address-cells = <0x3>;
-+			#interrupt-cells = <0x1>;
-+			#size-cells = <0x2>;
-+			compatible = "microsemi,ms-pf-axi-pcie-host";
-+			device_type = "pci";
-+			bus-range = <0x01 0x7f>;
-+			interrupt-map = <0 0 0 1 &ms_pcie_intc 0 0 0 0 2 &ms_pcie_intc 1 0 0 0 3 &ms_pcie_intc 2 0 0 0 4 &ms_pcie_intc 3>;
-+			interrupt-map-mask = <0 0 0 7>;
-+			interrupt-parent = <&plic0>;
-+			interrupts = <32>;
-+			ranges = <0x3000000 0x0 0x40000000 0x0 0x40000000 0x0 0x20000000>;
-+			reg = <0x20 0x30000000 0x0 0x4000000 0x20 0x0 0x0 0x100000>;
-+			reg-names = "control", "apb";
-+			ms_pcie_intc: interrupt-controller {
-+				#address-cells = <0>;
-+				#interrupt-cells = <1>;
-+				interrupt-controller;
-+			};
-+		};
-+	};
-+};
--- 
-2.22.0
-

+ 0 - 42
recipes-kernel/linux/files/freedom-u540/0003-HACK-Revert-of-device-Really-only-set-bus-DMA-mask-w.patch

@@ -1,42 +0,0 @@
-From 3b579413ed231e51625b5f5b5f672d10fc570628 Mon Sep 17 00:00:00 2001
-From: Alistair Francis <alistair.francis@wdc.com>
-Date: Thu, 21 Feb 2019 16:29:37 -0800
-Subject: [PATCH 3/4] HACK: Revert "of/device: Really only set bus DMA mask
- when appropriate"
-
-This reverts commit 6778be4e520959659b27a441c06a84c9cb009085.
-
-Reverting the commit fixes these error messages and an non-functioning
-USB bus when attaching a USB to PCIe card to a RISC-V board:
-    xhci_hcd 0000:03:00.0: Host took too long to start, waited 16000 microseconds.
-    xhci_hcd 0000:03:00.0: startup error -19
-    xhci_hcd 0000:03:00.0: USB bus 2 deregistered
-    xhci_hcd 0000:03:00.0: WARNING: Host System Error
-    xhci_hcd 0000:03:00.0: remove, state 1
-
-Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
-Upstream-Status: Denied
----
- drivers/of/device.c | 4 +---
- 1 file changed, 1 insertion(+), 3 deletions(-)
-
-diff --git a/drivers/of/device.c b/drivers/of/device.c
-index da8158392010..e1fb703ff603 100644
---- a/drivers/of/device.c
-+++ b/drivers/of/device.c
-@@ -149,11 +149,9 @@ int of_dma_configure(struct device *dev, struct device_node *np, bool force_dma)
- 	 * set by the driver.
- 	 */
- 	mask = DMA_BIT_MASK(ilog2(dma_addr + size - 1) + 1);
-+	dev->bus_dma_mask = mask;
- 	dev->coherent_dma_mask &= mask;
- 	*dev->dma_mask &= mask;
--	/* ...but only set bus mask if we found valid dma-ranges earlier */
--	if (!ret)
--		dev->bus_dma_mask = mask;
- 
- 	coherent = of_dma_is_coherent(np);
- 	dev_dbg(dev, "device is%sdma coherent\n",
--- 
-2.22.0
-

+ 0 - 42
recipes-kernel/linux/files/freedom-u540/extra.cfg

@@ -1,42 +0,0 @@
-CONFIG_CMDLINE="earlycon=sbi earlycon=sbi root=/dev/mmcblk0p3 rootwait console=ttySIF0 console=tty0"
-CONFIG_BLK_DEV_ZONED=y
-CONFIG_PCI_DEBUG=y
-CONFIG_PCIE_MICROSEMI=y
-CONFIG_PCI_SW_SWITCHTEC=y
-CONFIG_EXTRA_FIRMWARE="radeon/BTC_rlc.bin radeon/CAICOS_mc.bin radeon/CAICOS_me.bin radeon/CAICOS_pfp.bin radeon/CAICOS_smc.bin radeon/SUMO_uvd.bin"
-CONFIG_BLK_DEV_NBD=y
-CONFIG_BLK_DEV_NVME=y
-CONFIG_NVME_MULTIPATH=y
-CONFIG_NVME_FC=y
-CONFIG_NVME_TARGET=y
-CONFIG_NVME_TARGET_LOOP=y
-CONFIG_NVME_TARGET_FC=y
-CONFIG_NVME_TARGET_FCLOOP=y
-CONFIG_NVME_TARGET_TCP=y
-CONFIG_SATA_MV=y
-CONFIG_SATA_SIL=y
-CONFIG_TARGET_CORE=y
-CONFIG_TCM_IBLOCK=y
-CONFIG_TCM_FILEIO=y
-CONFIG_ISCSI_TARGET=y
-CONFIG_INPUT_EVDEV=y
-# CONFIG_KEYBOARD_ATKBD is not set
-# CONFIG_MOUSE_PS2 is not set
-CONFIG_INPUT_TABLET=y
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_TOUCHSCREEN_USB_COMPOSITE=y
-CONFIG_SERIO_LIBPS2=y
-CONFIG_LOGO=y
-CONFIG_SOUND=y
-CONFIG_SND=y
-CONFIG_SND_USB_AUDIO=y
-CONFIG_DMADEVICES=y
-CONFIG_CLK_SIFIVE=y
-CONFIG_CLK_SIFIVE_FU540_PRCI=y
-CONFIG_SIFIVE_PLIC=y
-CONFIG_EXT3_FS=y
-CONFIG_F2FS_FS=y
-CONFIG_F2FS_FS_SECURITY=y
-CONFIG_FUSE_FS=m
-CONFIG_USB_ACM=y
-CONFIG_USB_SERIAL=y

+ 411 - 0
recipes-kernel/linux/files/xuantie-c910/ice-c910_defconfig

@@ -0,0 +1,411 @@
+diff -Nur linux-5.4.36/arch/riscv/boot/dts/thead/Makefile kernel/arch/riscv/boot/dts/thead/Makefile
+--- /dev/null
++++ kernel/arch/riscv/boot/dts/thead/Makefile
+@@ -0,0 +1,2 @@
++# SPDX-License-Identifier: GPL-2.0
++dtb-$(CONFIG_SOC_LIGHT) += k210.dtb
+diff -Nur linux-5.4.36/arch/riscv/boot/dts/thead/light-c910.dts kernel/arch/riscv/boot/dts/thead/light-c910.dts
+--- /dev/null
++++ kernel/arch/riscv/boot/dts/thead/light-c910.dts
+@@ -0,0 +1,401 @@
++/dts-v1/;
++/ {
++	model = "T-HEAD ICE soc";
++	compatible = "thead,ice_c910";
++	#address-cells = <2>;
++	#size-cells = <2>;
++
++	memory@0 {
++		device_type = "memory";
++		/*
++		 * Total memory size: 2GB (0x00000000 0x80000000)
++		 * 0x00200000 - 0x40000000: 1022MB for Linux system
++		 * 0x40000000 - 0x60000000:  512MB for NPU: IAS0
++		 * 0x60000000 - 0x80000000:  512MB for GPU
++		 */
++		reg = <0x0 0x200000 0x0 0x3fe00000>;
++	};
++
++	cpus {
++		#address-cells = <1>;
++		#size-cells = <0>;
++		timebase-frequency = <3000000>;
++		cpu@0 {
++			device_type = "cpu";
++			reg = <0>;
++			status = "okay";
++			compatible = "riscv";
++			riscv,isa = "rv64imafdcsu";
++			mmu-type = "riscv,sv39";
++			cpu0_intc: interrupt-controller {
++				#interrupt-cells = <1>;
++				compatible = "riscv,cpu-intc";
++				interrupt-controller;
++			};
++		};
++		cpu@1 {
++			device_type = "cpu";
++			reg = <1>;
++			status = "okay";
++			compatible = "riscv";
++			riscv,isa = "rv64imafdcsu";
++			mmu-type = "riscv,sv39";
++			cpu1_intc: interrupt-controller {
++				#interrupt-cells = <1>;
++				compatible = "riscv,cpu-intc";
++				interrupt-controller;
++			};
++		};
++		cpu@2 {
++			device_type = "cpu";
++			reg = <2>;
++			status = "fail";
++			compatible = "riscv";
++			riscv,isa = "rv64imafdcsu";
++			mmu-type = "riscv,sv39";
++			cpu2_intc: interrupt-controller {
++				#interrupt-cells = <1>;
++				compatible = "riscv,cpu-intc";
++				interrupt-controller;
++			};
++		};
++	};
++
++	aliases {
++		ethernet0 = &gmac;
++	};
++
++	soc {
++		#address-cells = <2>;
++		#size-cells = <2>;
++		compatible = "simple-bus";
++		ranges;
++
++		intc: interrupt-controller@3f0000000 {
++			#interrupt-cells = <1>;
++			compatible = "riscv,plic0";
++			interrupt-controller;
++			interrupts-extended = <
++				&cpu0_intc  0xffffffff &cpu0_intc  9
++				&cpu1_intc  0xffffffff &cpu1_intc  9
++				&cpu2_intc  0xffffffff &cpu2_intc  9
++				>;
++			reg = <0x3 0xf0000000 0x0 0x04000000>;
++			reg-names = "control";
++			riscv,max-priority = <7>;
++			riscv,ndev = <80>;
++		};
++
++		dummy_apb: apb-clock {
++			compatible = "fixed-clock";
++			clock-frequency = <62500000>;
++			clock-output-names = "dummy_apb";
++			#clock-cells = <0>;
++		};
++
++		dummy_ahb: ahb-clock {
++			compatible = "fixed-clock";
++			clock-frequency = <250000000>;
++			clock-output-names = "dummy_ahb";
++			#clock-cells = <0>;
++		};
++
++		dummy_axi: axi-clock {
++			compatible = "fixed-clock";
++			clock-frequency = <500000000>;
++			clock-output-names = "dummy_axi";
++			#clock-cells = <0>;
++		};
++
++		dummy_gmac: gmac-clock {
++			compatible = "fixed-clock";
++			clock-frequency = <1000000000>;
++			clock-output-names = "dummy_gmac";
++			#clock-cells = <0>;
++		};
++
++		dummy_clk_sdio: dummy-clk-sdio {
++			compatible = "fixed-clock";
++			clock-frequency = <150000000>;
++			clock-output-names = "dummy_sdio";
++			#clock-cells = <0>;
++		};
++
++		dummy_clk_dpu: dummy-clk-dpu {
++			compatible = "fixed-clock";
++			clock-frequency = <297000000>;
++			clock-output-names = "dummy_dpu";
++			#clock-cells = <0>;
++		};
++
++		gpio0: gpio@3fff71000 {
++			compatible = "snps,dw-apb-gpio";
++			reg = <0x3 0xfff71000 0x0 0x1000>;
++			#address-cells = <2>;
++			#size-cells = <2>;
++
++			/* GPIO0[0-31] */
++			gpio0_porta: gpio0-controller@0 {
++				compatible = "snps,dw-apb-gpio-port";
++				gpio-controller;
++				#gpio-cells = <2>;
++				snps,nr-gpios = <32>;
++				reg = <0>;
++
++				interrupt-controller;
++				#interrupt-cells = <2>;
++				interrupt-parent = <&intc>;
++				interrupts = <27>;
++			};
++
++			/* GPIO0[32-63] */
++			gpio0_portb: gpio0-controller@1 {
++				compatible = "snps,dw-apb-gpio-port";
++				gpio-controller;
++				#gpio-cells = <2>;
++				snps,nr-gpios = <32>;
++				reg = <1>;
++			};
++		};
++
++		gpio1: gpio@3fff72000 {
++			compatible = "snps,dw-apb-gpio";
++			reg = <0x3 0xfff72000 0x0 0x1000>;
++			#address-cells = <2>;
++			#size-cells = <2>;
++
++			/* GPIO1[0-31] */
++			gpio1_porta: gpio1-controller@0 {
++				compatible = "snps,dw-apb-gpio-port";
++				gpio-controller;
++				#gpio-cells = <2>;
++				snps,nr-gpios = <32>;
++				reg = <0>;
++			};
++
++			/* GPIO1[32-63] */
++			gpio1_portb: gpio1-controller@1 {
++				compatible = "snps,dw-apb-gpio-port";
++				gpio-controller;
++				#gpio-cells = <2>;
++				snps,nr-gpios = <32>;
++				reg = <1>;
++			};
++
++			/* GPIO1[64-95] */
++			gpio1_portc: gpio1-controller@2 {
++				compatible = "snps,dw-apb-gpio-port";
++				gpio-controller;
++				#gpio-cells = <2>;
++				snps,nr-gpios = <32>;
++				reg = <2>;
++			};
++		};
++
++		gpio-leds {
++			compatible = "gpio-leds";
++
++			led0 { /* GPIO0[11] - UART2_TXD */
++				label = "led0";
++				gpios = <&gpio0_porta 11 1>;
++				default-state = "off";
++			};
++		};
++
++		gpio-keys {
++			compatible = "gpio-keys";
++			/* autorepeat; */
++
++			key_0 { /* GPIO0[10] - UART2_RXD */
++				gpios = <&gpio0_porta 10 1>;
++				linux,code = <59>;
++				label = "key_0";
++			};
++		};
++
++		serial0@3fff73000 {
++			compatible = "snps,dw-apb-uart";
++			reg = <0x3 0xfff73000 0x0 0x400>;
++			interrupt-parent = <&intc>;
++			interrupts = <23>;
++			clocks = <&dummy_apb>;
++			clock-names = "baudclk";
++			reg-shift = <2>;
++			reg-io-width = <4>;
++			fifo-size = <16>;
++			/*
++			 * rx-trigger-level:
++			 *     0 - 1 character
++			 *     1 - 1/4 full
++			 *     2 - 1/2 full
++			 *     3 - (fifo size - 2)
++			 */
++			rx-trigger-level = <2>;
++		};
++
++		/* serial1@3fff73400, interrupt=24 is occupied by CK810 system */
++
++		serial2@3fff73800 {
++			compatible = "snps,dw-apb-uart";
++			reg = <0x3 0xfff73800 0x0 0x400>;
++			interrupt-parent = <&intc>;
++			interrupts = <25>;
++			clocks = <&dummy_apb>;
++			clock-names = "baudclk";
++			reg-shift = <2>;
++			reg-io-width = <4>;
++			fifo-size = <16>;
++			/*
++			 * rx-trigger-level:
++			 *     0 - 1 character
++			 *     1 - 1/4 full
++			 *     2 - 1/2 full
++			 *     3 - (fifo size - 2)
++			 */
++			rx-trigger-level = <2>;
++		};
++
++		i2c@3fff74000 {
++			#address-cells = <2>;
++			#size-cells = <2>;
++			compatible = "dahua,i2c-dw201a";
++			reg = <0x3 0xfff74000 0x0 0x1000>;
++			interrupts = <21>;
++			interrupt-parent = <&intc>;
++			clocks = <&dummy_apb>;
++			clock-frequency = <400000>;
++
++			eeprom@50 {
++				compatible = "atmel,24c64";
++				reg = <0x50>;
++				pagesize = <32>;
++			};
++		};
++
++		pmu: pmu {
++			compatible = "riscv,c910_pmu";
++		};
++
++		dmac0: dmac@3fffd0000 {
++			compatible = "snps,axi-dma-1.01a";
++			reg = <0x3 0xfffd0000 0x0 0x1000>;
++			interrupt-parent = <&intc>;
++			interrupts = <65>;
++			clocks = <&dummy_axi>, <&dummy_ahb>;
++			clock-names = "core-clk", "cfgr-clk";
++
++			dma-channels = <8>;
++			snps,block-size = <65536 65536 65536 65536 65536 65536 65536 65536>;
++			snps,priority = <0 1 2 3 4 5 6 7>;
++			snps,dma-masters = <1>;
++			snps,data-width = <4>;
++			snps,axi-max-burst-len = <16>;
++
++			/* status = "disabled"; */
++		};
++
++		sdhc0: sdhc0@3fffb0000 {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			compatible = "snps,dw-mshc";
++			reg = <0x3 0xfffb0000 0x0 0x1000>;
++			interrupt-parent = <&intc>;
++			interrupts = <37>;
++			clocks = <&dummy_clk_sdio>, <&dummy_clk_sdio>;
++			clock-names = "ciu", "biu";
++			num-slots = <1>;
++			card-detect-delay = <200>;
++			cap-mmc-highspeed;
++			cap-cmd23;
++			non-removable;
++			bus-width = <8>;
++		};
++
++		sdhc1: sdhc1@3fffa0000 {
++			compatible = "snps,dw-mshc";
++			reg = <0x3 0xfffa0000 0x0 0x1000>;
++			interrupt-parent = <&intc>;
++			interrupts = <38>;
++			clocks = <&dummy_clk_sdio>, <&dummy_clk_sdio>;
++			clock-names = "ciu", "biu";
++			num-slots = <1>;
++			card-detect-delay = <200>;
++			cap-sd-highspeed;
++			bus-width = <4>;
++		};
++
++		stmmac_axi_setup: stmmac-axi-config {
++			snps,wr_osr_lmt = <3>;
++			snps,rd_osr_lmt = <3>;
++			snps,blen = <16 8 4 0 0 0 0>;
++		};
++
++		gmac: ethernet@3fffc0000 {
++			compatible = "thead,dwmac";
++			reg = < 0x3 0xfffc0000 0x0 0x2000
++				0x3 0xfe83025c 0x0 0x4
++				0x3 0xfe83031c 0x0 0x4
++				0x3 0xfff770c0 0x0 0x1c>;
++			reg-names = "gmac", "phy_if_reg", "txclk_dir_reg", "clk_mgr_reg";
++			interrupt-parent = <&intc>;
++			interrupts = <40>;
++			interrupt-names = "macirq";
++			clocks = <&dummy_ahb>, <&dummy_gmac>;
++			clock-names = "stmmaceth", "gmac_pll_clk";
++			snps,pbl = <32>;
++			snps,fixed-burst;
++			snps,axi-config = <&stmmac_axi_setup>;
++
++			phy-mode = "rgmii-txid";
++			rx-clk-delay = <0x1f>; /* for RGMII */
++			tx-clk-delay = <0x1f>; /* for RGMII */
++
++			phy-handle = <&eth_phy_0>;
++			mdio0 {
++				#address-cells = <1>;
++				#size-cells = <0>;
++				compatible = "snps,dwmac-mdio";
++
++				eth_phy_0: ethernet-phy@0 {
++					reg = <0>;
++				};
++			};
++		};
++
++		npu0: npu@3fff20000 {
++			compatible = "verisilicon,vip8000";
++			core-id = <0>;
++			reg = <0x3 0xfff20000 0x0 0x1000>;
++			interrupt-parent = <&intc>;
++			interrupts = <66>;
++			contiguous-base = <0x0 0x40000000>;
++			contiguous-size = <0x0 0x20000000>;
++			extsram-base = <0x3 0xfe400000>;
++			extsram-size = <0x0 0x40000>;
++		};
++
++		gpu: gpu@3fff27000 {
++			compatible = "verisilicon,gc8000ul";
++			reg = <0x3 0xfff27000 0x0 0x1000>;
++			interrupt-parent = <&intc>;
++			interrupts = <63>;
++			contiguous-base = <0x0 0x60000000>;
++			contiguous-size = <0x0 0x10000000>;
++		};
++
++		dpu: dpu@3fff28000 {
++			compatible = "verisilicon,dc8000-fb";
++			reg = <0x3 0xfff28000 0x0 0x8000>;
++			interrupt-parent = <&intc>;
++			interrupts = <64>;
++		};
++
++	};
++
++	chosen {
++		bootargs = "console=ttyS0,115200 crashkernel=256M-:128M c910_mmu_v1";
++		linux,initrd-start = <0x2000000>;
++		linux,initrd-end = <0x17000000>;
++		stdout-path = "serial0@3fff73000:115200";
++	};
++};

+ 411 - 0
recipes-kernel/linux/files/xuantie-c910/light-c910-dts.patch

@@ -0,0 +1,411 @@
+diff -Nur linux-5.4.36/arch/riscv/boot/dts/thead/Makefile kernel/arch/riscv/boot/dts/thead/Makefile
+--- /dev/null
++++ kernel/arch/riscv/boot/dts/thead/Makefile
+@@ -0,0 +1,2 @@
++# SPDX-License-Identifier: GPL-2.0
++dtb-$(CONFIG_SOC_LIGHT) += k210.dtb
+diff -Nur linux-5.4.36/arch/riscv/boot/dts/thead/light-c910.dts kernel/arch/riscv/boot/dts/thead/light-c910.dts
+--- /dev/null
++++ kernel/arch/riscv/boot/dts/thead/light-c910.dts
+@@ -0,0 +1,401 @@
++/dts-v1/;
++/ {
++	model = "T-HEAD ICE soc";
++	compatible = "thead,ice_c910";
++	#address-cells = <2>;
++	#size-cells = <2>;
++
++	memory@0 {
++		device_type = "memory";
++		/*
++		 * Total memory size: 2GB (0x00000000 0x80000000)
++		 * 0x00200000 - 0x40000000: 1022MB for Linux system
++		 * 0x40000000 - 0x60000000:  512MB for NPU: IAS0
++		 * 0x60000000 - 0x80000000:  512MB for GPU
++		 */
++		reg = <0x0 0x200000 0x0 0x3fe00000>;
++	};
++
++	cpus {
++		#address-cells = <1>;
++		#size-cells = <0>;
++		timebase-frequency = <3000000>;
++		cpu@0 {
++			device_type = "cpu";
++			reg = <0>;
++			status = "okay";
++			compatible = "riscv";
++			riscv,isa = "rv64imafdcsu";
++			mmu-type = "riscv,sv39";
++			cpu0_intc: interrupt-controller {
++				#interrupt-cells = <1>;
++				compatible = "riscv,cpu-intc";
++				interrupt-controller;
++			};
++		};
++		cpu@1 {
++			device_type = "cpu";
++			reg = <1>;
++			status = "okay";
++			compatible = "riscv";
++			riscv,isa = "rv64imafdcsu";
++			mmu-type = "riscv,sv39";
++			cpu1_intc: interrupt-controller {
++				#interrupt-cells = <1>;
++				compatible = "riscv,cpu-intc";
++				interrupt-controller;
++			};
++		};
++		cpu@2 {
++			device_type = "cpu";
++			reg = <2>;
++			status = "fail";
++			compatible = "riscv";
++			riscv,isa = "rv64imafdcsu";
++			mmu-type = "riscv,sv39";
++			cpu2_intc: interrupt-controller {
++				#interrupt-cells = <1>;
++				compatible = "riscv,cpu-intc";
++				interrupt-controller;
++			};
++		};
++	};
++
++	aliases {
++		ethernet0 = &gmac;
++	};
++
++	soc {
++		#address-cells = <2>;
++		#size-cells = <2>;
++		compatible = "simple-bus";
++		ranges;
++
++		intc: interrupt-controller@3f0000000 {
++			#interrupt-cells = <1>;
++			compatible = "riscv,plic0";
++			interrupt-controller;
++			interrupts-extended = <
++				&cpu0_intc  0xffffffff &cpu0_intc  9
++				&cpu1_intc  0xffffffff &cpu1_intc  9
++				&cpu2_intc  0xffffffff &cpu2_intc  9
++				>;
++			reg = <0x3 0xf0000000 0x0 0x04000000>;
++			reg-names = "control";
++			riscv,max-priority = <7>;
++			riscv,ndev = <80>;
++		};
++
++		dummy_apb: apb-clock {
++			compatible = "fixed-clock";
++			clock-frequency = <62500000>;
++			clock-output-names = "dummy_apb";
++			#clock-cells = <0>;
++		};
++
++		dummy_ahb: ahb-clock {
++			compatible = "fixed-clock";
++			clock-frequency = <250000000>;
++			clock-output-names = "dummy_ahb";
++			#clock-cells = <0>;
++		};
++
++		dummy_axi: axi-clock {
++			compatible = "fixed-clock";
++			clock-frequency = <500000000>;
++			clock-output-names = "dummy_axi";
++			#clock-cells = <0>;
++		};
++
++		dummy_gmac: gmac-clock {
++			compatible = "fixed-clock";
++			clock-frequency = <1000000000>;
++			clock-output-names = "dummy_gmac";
++			#clock-cells = <0>;
++		};
++
++		dummy_clk_sdio: dummy-clk-sdio {
++			compatible = "fixed-clock";
++			clock-frequency = <150000000>;
++			clock-output-names = "dummy_sdio";
++			#clock-cells = <0>;
++		};
++
++		dummy_clk_dpu: dummy-clk-dpu {
++			compatible = "fixed-clock";
++			clock-frequency = <297000000>;
++			clock-output-names = "dummy_dpu";
++			#clock-cells = <0>;
++		};
++
++		gpio0: gpio@3fff71000 {
++			compatible = "snps,dw-apb-gpio";
++			reg = <0x3 0xfff71000 0x0 0x1000>;
++			#address-cells = <2>;
++			#size-cells = <2>;
++
++			/* GPIO0[0-31] */
++			gpio0_porta: gpio0-controller@0 {
++				compatible = "snps,dw-apb-gpio-port";
++				gpio-controller;
++				#gpio-cells = <2>;
++				snps,nr-gpios = <32>;
++				reg = <0>;
++
++				interrupt-controller;
++				#interrupt-cells = <2>;
++				interrupt-parent = <&intc>;
++				interrupts = <27>;
++			};
++
++			/* GPIO0[32-63] */
++			gpio0_portb: gpio0-controller@1 {
++				compatible = "snps,dw-apb-gpio-port";
++				gpio-controller;
++				#gpio-cells = <2>;
++				snps,nr-gpios = <32>;
++				reg = <1>;
++			};
++		};
++
++		gpio1: gpio@3fff72000 {
++			compatible = "snps,dw-apb-gpio";
++			reg = <0x3 0xfff72000 0x0 0x1000>;
++			#address-cells = <2>;
++			#size-cells = <2>;
++
++			/* GPIO1[0-31] */
++			gpio1_porta: gpio1-controller@0 {
++				compatible = "snps,dw-apb-gpio-port";
++				gpio-controller;
++				#gpio-cells = <2>;
++				snps,nr-gpios = <32>;
++				reg = <0>;
++			};
++
++			/* GPIO1[32-63] */
++			gpio1_portb: gpio1-controller@1 {
++				compatible = "snps,dw-apb-gpio-port";
++				gpio-controller;
++				#gpio-cells = <2>;
++				snps,nr-gpios = <32>;
++				reg = <1>;
++			};
++
++			/* GPIO1[64-95] */
++			gpio1_portc: gpio1-controller@2 {
++				compatible = "snps,dw-apb-gpio-port";
++				gpio-controller;
++				#gpio-cells = <2>;
++				snps,nr-gpios = <32>;
++				reg = <2>;
++			};
++		};
++
++		gpio-leds {
++			compatible = "gpio-leds";
++
++			led0 { /* GPIO0[11] - UART2_TXD */
++				label = "led0";
++				gpios = <&gpio0_porta 11 1>;
++				default-state = "off";
++			};
++		};
++
++		gpio-keys {
++			compatible = "gpio-keys";
++			/* autorepeat; */
++
++			key_0 { /* GPIO0[10] - UART2_RXD */
++				gpios = <&gpio0_porta 10 1>;
++				linux,code = <59>;
++				label = "key_0";
++			};
++		};
++
++		serial0@3fff73000 {
++			compatible = "snps,dw-apb-uart";
++			reg = <0x3 0xfff73000 0x0 0x400>;
++			interrupt-parent = <&intc>;
++			interrupts = <23>;
++			clocks = <&dummy_apb>;
++			clock-names = "baudclk";
++			reg-shift = <2>;
++			reg-io-width = <4>;
++			fifo-size = <16>;
++			/*
++			 * rx-trigger-level:
++			 *     0 - 1 character
++			 *     1 - 1/4 full
++			 *     2 - 1/2 full
++			 *     3 - (fifo size - 2)
++			 */
++			rx-trigger-level = <2>;
++		};
++
++		/* serial1@3fff73400, interrupt=24 is occupied by CK810 system */
++
++		serial2@3fff73800 {
++			compatible = "snps,dw-apb-uart";
++			reg = <0x3 0xfff73800 0x0 0x400>;
++			interrupt-parent = <&intc>;
++			interrupts = <25>;
++			clocks = <&dummy_apb>;
++			clock-names = "baudclk";
++			reg-shift = <2>;
++			reg-io-width = <4>;
++			fifo-size = <16>;
++			/*
++			 * rx-trigger-level:
++			 *     0 - 1 character
++			 *     1 - 1/4 full
++			 *     2 - 1/2 full
++			 *     3 - (fifo size - 2)
++			 */
++			rx-trigger-level = <2>;
++		};
++
++		i2c@3fff74000 {
++			#address-cells = <2>;
++			#size-cells = <2>;
++			compatible = "dahua,i2c-dw201a";
++			reg = <0x3 0xfff74000 0x0 0x1000>;
++			interrupts = <21>;
++			interrupt-parent = <&intc>;
++			clocks = <&dummy_apb>;
++			clock-frequency = <400000>;
++
++			eeprom@50 {
++				compatible = "atmel,24c64";
++				reg = <0x50>;
++				pagesize = <32>;
++			};
++		};
++
++		pmu: pmu {
++			compatible = "riscv,c910_pmu";
++		};
++
++		dmac0: dmac@3fffd0000 {
++			compatible = "snps,axi-dma-1.01a";
++			reg = <0x3 0xfffd0000 0x0 0x1000>;
++			interrupt-parent = <&intc>;
++			interrupts = <65>;
++			clocks = <&dummy_axi>, <&dummy_ahb>;
++			clock-names = "core-clk", "cfgr-clk";
++
++			dma-channels = <8>;
++			snps,block-size = <65536 65536 65536 65536 65536 65536 65536 65536>;
++			snps,priority = <0 1 2 3 4 5 6 7>;
++			snps,dma-masters = <1>;
++			snps,data-width = <4>;
++			snps,axi-max-burst-len = <16>;
++
++			/* status = "disabled"; */
++		};
++
++		sdhc0: sdhc0@3fffb0000 {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			compatible = "snps,dw-mshc";
++			reg = <0x3 0xfffb0000 0x0 0x1000>;
++			interrupt-parent = <&intc>;
++			interrupts = <37>;
++			clocks = <&dummy_clk_sdio>, <&dummy_clk_sdio>;
++			clock-names = "ciu", "biu";
++			num-slots = <1>;
++			card-detect-delay = <200>;
++			cap-mmc-highspeed;
++			cap-cmd23;
++			non-removable;
++			bus-width = <8>;
++		};
++
++		sdhc1: sdhc1@3fffa0000 {
++			compatible = "snps,dw-mshc";
++			reg = <0x3 0xfffa0000 0x0 0x1000>;
++			interrupt-parent = <&intc>;
++			interrupts = <38>;
++			clocks = <&dummy_clk_sdio>, <&dummy_clk_sdio>;
++			clock-names = "ciu", "biu";
++			num-slots = <1>;
++			card-detect-delay = <200>;
++			cap-sd-highspeed;
++			bus-width = <4>;
++		};
++
++		stmmac_axi_setup: stmmac-axi-config {
++			snps,wr_osr_lmt = <3>;
++			snps,rd_osr_lmt = <3>;
++			snps,blen = <16 8 4 0 0 0 0>;
++		};
++
++		gmac: ethernet@3fffc0000 {
++			compatible = "thead,dwmac";
++			reg = < 0x3 0xfffc0000 0x0 0x2000
++				0x3 0xfe83025c 0x0 0x4
++				0x3 0xfe83031c 0x0 0x4
++				0x3 0xfff770c0 0x0 0x1c>;
++			reg-names = "gmac", "phy_if_reg", "txclk_dir_reg", "clk_mgr_reg";
++			interrupt-parent = <&intc>;
++			interrupts = <40>;
++			interrupt-names = "macirq";
++			clocks = <&dummy_ahb>, <&dummy_gmac>;
++			clock-names = "stmmaceth", "gmac_pll_clk";
++			snps,pbl = <32>;
++			snps,fixed-burst;
++			snps,axi-config = <&stmmac_axi_setup>;
++
++			phy-mode = "rgmii-txid";
++			rx-clk-delay = <0x1f>; /* for RGMII */
++			tx-clk-delay = <0x1f>; /* for RGMII */
++
++			phy-handle = <&eth_phy_0>;
++			mdio0 {
++				#address-cells = <1>;
++				#size-cells = <0>;
++				compatible = "snps,dwmac-mdio";
++
++				eth_phy_0: ethernet-phy@0 {
++					reg = <0>;
++				};
++			};
++		};
++
++		npu0: npu@3fff20000 {
++			compatible = "verisilicon,vip8000";
++			core-id = <0>;
++			reg = <0x3 0xfff20000 0x0 0x1000>;
++			interrupt-parent = <&intc>;
++			interrupts = <66>;
++			contiguous-base = <0x0 0x40000000>;
++			contiguous-size = <0x0 0x20000000>;
++			extsram-base = <0x3 0xfe400000>;
++			extsram-size = <0x0 0x40000>;
++		};
++
++		gpu: gpu@3fff27000 {
++			compatible = "verisilicon,gc8000ul";
++			reg = <0x3 0xfff27000 0x0 0x1000>;
++			interrupt-parent = <&intc>;
++			interrupts = <63>;
++			contiguous-base = <0x0 0x60000000>;
++			contiguous-size = <0x0 0x10000000>;
++		};
++
++		dpu: dpu@3fff28000 {
++			compatible = "verisilicon,dc8000-fb";
++			reg = <0x3 0xfff28000 0x0 0x8000>;
++			interrupt-parent = <&intc>;
++			interrupts = <64>;
++		};
++
++	};
++
++	chosen {
++		bootargs = "console=ttyS0,115200 crashkernel=256M-:128M c910_mmu_v1";
++		linux,initrd-start = <0x2000000>;
++		linux,initrd-end = <0x17000000>;
++		stdout-path = "serial0@3fff73000:115200";
++	};
++};

+ 3811 - 0
recipes-kernel/linux/files/xuantie-c910/light-c910_defconfig

@@ -0,0 +1,3811 @@
+#
+# Automatically generated file; DO NOT EDIT.
+# Linux/riscv 5.4.36 Kernel Configuration
+#
+
+#
+# Compiler: riscv64-unknown-linux-gnu-gcc (C-SKY RISCV Tools V1.8.4 B20200702) 8.1.0
+#
+CONFIG_CC_IS_GCC=y
+CONFIG_GCC_VERSION=80100
+CONFIG_CLANG_VERSION=0
+CONFIG_CC_CAN_LINK=y
+CONFIG_CC_HAS_ASM_GOTO=y
+CONFIG_CC_HAS_WARN_MAYBE_UNINITIALIZED=y
+CONFIG_IRQ_WORK=y
+CONFIG_THREAD_INFO_IN_TASK=y
+
+#
+# General setup
+#
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_COMPILE_TEST=y
+CONFIG_LOCALVERSION=""
+CONFIG_BUILD_SALT=""
+CONFIG_DEFAULT_HOSTNAME="(none)"
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_POSIX_MQUEUE_SYSCTL=y
+CONFIG_CROSS_MEMORY_ATTACH=y
+# CONFIG_USELIB is not set
+# CONFIG_AUDIT is not set
+CONFIG_HAVE_ARCH_AUDITSYSCALL=y
+
+#
+# IRQ subsystem
+#
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_IRQ_DOMAIN=y
+CONFIG_IRQ_DOMAIN_HIERARCHY=y
+CONFIG_GENERIC_MSI_IRQ=y
+CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
+CONFIG_SPARSE_IRQ=y
+# CONFIG_GENERIC_IRQ_DEBUGFS is not set
+# end of IRQ subsystem
+
+CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+
+#
+# Timers subsystem
+#
+CONFIG_TICK_ONESHOT=y
+CONFIG_NO_HZ_COMMON=y
+# CONFIG_HZ_PERIODIC is not set
+CONFIG_NO_HZ_IDLE=y
+# CONFIG_NO_HZ is not set
+CONFIG_HIGH_RES_TIMERS=y
+# end of Timers subsystem
+
+CONFIG_PREEMPT_NONE=y
+# CONFIG_PREEMPT_VOLUNTARY is not set
+# CONFIG_PREEMPT is not set
+CONFIG_PREEMPT_COUNT=y
+
+#
+# CPU/Task time and stats accounting
+#
+CONFIG_TICK_CPU_ACCOUNTING=y
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_PSI is not set
+# end of CPU/Task time and stats accounting
+
+CONFIG_CPU_ISOLATION=y
+
+#
+# RCU Subsystem
+#
+CONFIG_TREE_RCU=y
+# CONFIG_RCU_EXPERT is not set
+CONFIG_SRCU=y
+CONFIG_TREE_SRCU=y
+CONFIG_RCU_STALL_COMMON=y
+CONFIG_RCU_NEED_SEGCBLIST=y
+# end of RCU Subsystem
+
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+# CONFIG_IKHEADERS is not set
+CONFIG_LOG_BUF_SHIFT=17
+CONFIG_LOG_CPU_MAX_BUF_SHIFT=12
+CONFIG_PRINTK_SAFE_LOG_BUF_SHIFT=13
+CONFIG_GENERIC_SCHED_CLOCK=y
+
+#
+# Scheduler features
+#
+# end of Scheduler features
+
+CONFIG_ARCH_SUPPORTS_INT128=y
+CONFIG_CGROUPS=y
+# CONFIG_MEMCG is not set
+# CONFIG_BLK_CGROUP is not set
+CONFIG_CGROUP_SCHED=y
+CONFIG_FAIR_GROUP_SCHED=y
+CONFIG_CFS_BANDWIDTH=y
+# CONFIG_RT_GROUP_SCHED is not set
+# CONFIG_CGROUP_PIDS is not set
+# CONFIG_CGROUP_RDMA is not set
+# CONFIG_CGROUP_FREEZER is not set
+# CONFIG_CPUSETS is not set
+# CONFIG_CGROUP_DEVICE is not set
+# CONFIG_CGROUP_CPUACCT is not set
+# CONFIG_CGROUP_PERF is not set
+CONFIG_CGROUP_BPF=y
+# CONFIG_CGROUP_DEBUG is not set
+CONFIG_SOCK_CGROUP_DATA=y
+CONFIG_NAMESPACES=y
+CONFIG_UTS_NS=y
+CONFIG_IPC_NS=y
+CONFIG_USER_NS=y
+CONFIG_PID_NS=y
+CONFIG_NET_NS=y
+CONFIG_CHECKPOINT_RESTORE=y
+# CONFIG_SCHED_AUTOGROUP is not set
+# CONFIG_SYSFS_DEPRECATED is not set
+# CONFIG_RELAY is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_RD_GZIP=y
+CONFIG_RD_BZIP2=y
+CONFIG_RD_LZMA=y
+CONFIG_RD_XZ=y
+CONFIG_RD_LZO=y
+CONFIG_RD_LZ4=y
+CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_SYSCTL=y
+CONFIG_SYSCTL_EXCEPTION_TRACE=y
+CONFIG_BPF=y
+CONFIG_EXPERT=y
+CONFIG_MULTIUSER=y
+# CONFIG_SGETMASK_SYSCALL is not set
+CONFIG_SYSFS_SYSCALL=y
+# CONFIG_SYSCTL_SYSCALL is not set
+CONFIG_FHANDLE=y
+CONFIG_POSIX_TIMERS=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_FUTEX_PI=y
+CONFIG_HAVE_FUTEX_CMPXCHG=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_AIO=y
+CONFIG_IO_URING=y
+CONFIG_ADVISE_SYSCALLS=y
+CONFIG_MEMBARRIER=y
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_ALL is not set
+CONFIG_KALLSYMS_BASE_RELATIVE=y
+CONFIG_BPF_SYSCALL=y
+# CONFIG_USERFAULTFD is not set
+# CONFIG_EMBEDDED is not set
+CONFIG_HAVE_PERF_EVENTS=y
+# CONFIG_PC104 is not set
+
+#
+# Kernel Performance Events And Counters
+#
+CONFIG_PERF_EVENTS=y
+# CONFIG_DEBUG_PERF_USE_VMALLOC is not set
+# end of Kernel Performance Events And Counters
+
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLUB_DEBUG=y
+CONFIG_COMPAT_BRK=y
+# CONFIG_SLAB is not set
+CONFIG_SLUB=y
+# CONFIG_SLOB is not set
+CONFIG_SLAB_MERGE_DEFAULT=y
+# CONFIG_SLAB_FREELIST_RANDOM is not set
+# CONFIG_SLAB_FREELIST_HARDENED is not set
+# CONFIG_SHUFFLE_PAGE_ALLOCATOR is not set
+CONFIG_SLUB_CPU_PARTIAL=y
+# CONFIG_PROFILING is not set
+# end of General setup
+
+CONFIG_64BIT=y
+CONFIG_RISCV=y
+CONFIG_ARCH_MMAP_RND_BITS_MIN=18
+CONFIG_ARCH_MMAP_RND_BITS_MAX=24
+CONFIG_MMU=y
+CONFIG_ZONE_DMA32=y
+CONFIG_VA_BITS=39
+CONFIG_PA_BITS=56
+CONFIG_PAGE_OFFSET=0xffffffe000000000
+CONFIG_ARCH_FLATMEM_ENABLE=y
+CONFIG_ARCH_SPARSEMEM_ENABLE=y
+CONFIG_ARCH_SELECT_MEMORY_MODEL=y
+CONFIG_ARCH_WANT_GENERAL_HUGETLB=y
+CONFIG_SYS_SUPPORTS_HUGETLBFS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_GENERIC_BUG=y
+CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_CSUM=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_FIX_EARLYCON_MEM=y
+CONFIG_PGTABLE_LEVELS=3
+
+#
+# SoC selection
+#
+CONFIG_SOC_SIFIVE=y
+# end of SoC selection
+
+#
+# Platform type
+#
+# CONFIG_ARCH_RV32I is not set
+CONFIG_ARCH_RV64I=y
+# CONFIG_CMODEL_MEDLOW is not set
+CONFIG_CMODEL_MEDANY=y
+CONFIG_MODULE_SECTIONS=y
+# CONFIG_MAXPHYSMEM_2GB is not set
+CONFIG_MAXPHYSMEM_128GB=y
+CONFIG_SMP=y
+CONFIG_NR_CPUS=8
+CONFIG_TUNE_GENERIC=y
+CONFIG_RISCV_ISA_C=y
+
+#
+# supported PMU type
+#
+CONFIG_RISCV_BASE_PMU=y
+# end of supported PMU type
+
+CONFIG_FPU=y
+CONFIG_VECTOR=y
+# end of Platform type
+
+#
+# Kernel features
+#
+# CONFIG_HZ_12 is not set
+# CONFIG_HZ_100 is not set
+CONFIG_HZ_250=y
+# CONFIG_HZ_300 is not set
+# CONFIG_HZ_1000 is not set
+CONFIG_HZ=250
+CONFIG_SCHED_HRTICK=y
+# CONFIG_KEXEC is not set
+# CONFIG_CRASH_DUMP is not set
+# end of Kernel features
+
+#
+# Boot options
+#
+CONFIG_CMDLINE=""
+# end of Boot options
+
+#
+# Power management options
+#
+# CONFIG_PM is not set
+# end of Power management options
+
+#
+# General architecture-dependent options
+#
+CONFIG_HAVE_ARCH_TRACEHOOK=y
+CONFIG_HAVE_DMA_CONTIGUOUS=y
+CONFIG_GENERIC_SMP_IDLE_THREAD=y
+CONFIG_HAVE_ASM_MODVERSIONS=y
+CONFIG_HAVE_CLK=y
+CONFIG_HAVE_PERF_REGS=y
+CONFIG_HAVE_PERF_USER_STACK_DUMP=y
+CONFIG_CC_HAS_STACKPROTECTOR_NONE=y
+CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y
+CONFIG_ARCH_WANT_HUGE_PMD_SHARE=y
+CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
+CONFIG_MODULES_USE_ELF_RELA=y
+CONFIG_ARCH_HAS_ELF_RANDOMIZE=y
+CONFIG_HAVE_ARCH_MMAP_RND_BITS=y
+CONFIG_ARCH_MMAP_RND_BITS=18
+CONFIG_ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT=y
+CONFIG_HAVE_COPY_THREAD_TLS=y
+CONFIG_CLONE_BACKWARDS=y
+CONFIG_64BIT_TIME=y
+# CONFIG_REFCOUNT_FULL is not set
+# CONFIG_LOCK_EVENT_COUNTS is not set
+
+#
+# GCOV-based kernel profiling
+#
+# CONFIG_GCOV_KERNEL is not set
+# end of GCOV-based kernel profiling
+
+CONFIG_PLUGIN_HOSTCC=""
+# end of General architecture-dependent options
+
+CONFIG_RT_MUTEXES=y
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+# CONFIG_MODULE_SIG is not set
+# CONFIG_MODULE_COMPRESS is not set
+# CONFIG_MODULE_ALLOW_MISSING_NAMESPACE_IMPORTS is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_TRIM_UNUSED_KSYMS is not set
+CONFIG_MODULES_TREE_LOOKUP=y
+CONFIG_BLOCK=y
+CONFIG_BLK_SCSI_REQUEST=y
+CONFIG_BLK_DEV_BSG=y
+# CONFIG_BLK_DEV_BSGLIB is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
+# CONFIG_BLK_DEV_ZONED is not set
+# CONFIG_BLK_CMDLINE_PARSER is not set
+# CONFIG_BLK_WBT is not set
+CONFIG_BLK_DEBUG_FS=y
+# CONFIG_BLK_SED_OPAL is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+CONFIG_EFI_PARTITION=y
+# end of Partition Types
+
+CONFIG_BLK_MQ_PCI=y
+CONFIG_BLK_MQ_VIRTIO=y
+
+#
+# IO Schedulers
+#
+CONFIG_MQ_IOSCHED_DEADLINE=y
+CONFIG_MQ_IOSCHED_KYBER=y
+# CONFIG_IOSCHED_BFQ is not set
+# end of IO Schedulers
+
+CONFIG_INLINE_SPIN_UNLOCK_IRQ=y
+CONFIG_INLINE_READ_UNLOCK=y
+CONFIG_INLINE_READ_UNLOCK_IRQ=y
+CONFIG_INLINE_WRITE_UNLOCK=y
+CONFIG_INLINE_WRITE_UNLOCK_IRQ=y
+CONFIG_ARCH_HAS_MMIOWB=y
+CONFIG_MMIOWB=y
+
+#
+# Executable file formats
+#
+CONFIG_BINFMT_ELF=y
+CONFIG_ELFCORE=y
+CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y
+CONFIG_BINFMT_SCRIPT=y
+CONFIG_ARCH_HAS_BINFMT_FLAT=y
+# CONFIG_BINFMT_FLAT is not set
+# CONFIG_BINFMT_MISC is not set
+CONFIG_COREDUMP=y
+# end of Executable file formats
+
+#
+# Memory Management options
+#
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
+CONFIG_HAVE_MEMBLOCK_NODE_MAP=y
+CONFIG_SPLIT_PTLOCK_CPUS=4
+CONFIG_MEMORY_BALLOON=y
+CONFIG_BALLOON_COMPACTION=y
+CONFIG_COMPACTION=y
+CONFIG_MIGRATION=y
+CONFIG_PHYS_ADDR_T_64BIT=y
+# CONFIG_KSM is not set
+CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
+# CONFIG_CLEANCACHE is not set
+# CONFIG_FRONTSWAP is not set
+# CONFIG_CMA is not set
+# CONFIG_ZPOOL is not set
+# CONFIG_ZBUD is not set
+# CONFIG_ZSMALLOC is not set
+# CONFIG_IDLE_PAGE_TRACKING is not set
+# CONFIG_PERCPU_STATS is not set
+# CONFIG_GUP_BENCHMARK is not set
+CONFIG_ARCH_HAS_PTE_SPECIAL=y
+# end of Memory Management options
+
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_DIAG is not set
+CONFIG_UNIX=y
+CONFIG_UNIX_SCM=y
+# CONFIG_UNIX_DIAG is not set
+# CONFIG_TLS is not set
+# CONFIG_XFRM_USER is not set
+# CONFIG_NET_KEY is not set
+# CONFIG_XDP_SOCKETS is not set
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_ADVANCED_ROUTER=y
+# CONFIG_IP_FIB_TRIE_STATS is not set
+# CONFIG_IP_MULTIPLE_TABLES is not set
+# CONFIG_IP_ROUTE_MULTIPATH is not set
+# CONFIG_IP_ROUTE_VERBOSE is not set
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_IP_PNP_RARP=y
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE_DEMUX is not set
+CONFIG_NET_IP_TUNNEL=y
+# CONFIG_IP_MROUTE is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_NET_IPVTI is not set
+# CONFIG_NET_FOU is not set
+# CONFIG_NET_FOU_IP_TUNNELS is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+CONFIG_INET_TUNNEL=y
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+# CONFIG_INET_UDP_DIAG is not set
+# CONFIG_INET_RAW_DIAG is not set
+# CONFIG_INET_DIAG_DESTROY is not set
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+CONFIG_IPV6=y
+# CONFIG_IPV6_ROUTER_PREF is not set
+# CONFIG_IPV6_OPTIMISTIC_DAD is not set
+# CONFIG_INET6_AH is not set
+# CONFIG_INET6_ESP is not set
+# CONFIG_INET6_IPCOMP is not set
+# CONFIG_IPV6_MIP6 is not set
+# CONFIG_IPV6_VTI is not set
+CONFIG_IPV6_SIT=y
+# CONFIG_IPV6_SIT_6RD is not set
+CONFIG_IPV6_NDISC_NODETYPE=y
+# CONFIG_IPV6_TUNNEL is not set
+# CONFIG_IPV6_MULTIPLE_TABLES is not set
+# CONFIG_IPV6_MROUTE is not set
+# CONFIG_IPV6_SEG6_LWTUNNEL is not set
+# CONFIG_IPV6_SEG6_HMAC is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETWORK_PHY_TIMESTAMPING is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_BPFILTER is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_RDS is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_L2TP is not set
+# CONFIG_BRIDGE is not set
+CONFIG_HAVE_NET_DSA=y
+# CONFIG_NET_DSA is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_PHONET is not set
+# CONFIG_6LOWPAN is not set
+# CONFIG_IEEE802154 is not set
+# CONFIG_NET_SCHED is not set
+# CONFIG_DCB is not set
+CONFIG_DNS_RESOLVER=y
+# CONFIG_BATMAN_ADV is not set
+# CONFIG_OPENVSWITCH is not set
+# CONFIG_VSOCKETS is not set
+CONFIG_NETLINK_DIAG=y
+# CONFIG_MPLS is not set
+# CONFIG_NET_NSH is not set
+# CONFIG_HSR is not set
+# CONFIG_NET_SWITCHDEV is not set
+# CONFIG_NET_L3_MASTER_DEV is not set
+# CONFIG_QRTR is not set
+# CONFIG_NET_NCSI is not set
+CONFIG_RPS=y
+CONFIG_RFS_ACCEL=y
+CONFIG_XPS=y
+# CONFIG_CGROUP_NET_PRIO is not set
+# CONFIG_CGROUP_NET_CLASSID is not set
+CONFIG_NET_RX_BUSY_POLL=y
+CONFIG_BQL=y
+# CONFIG_BPF_JIT is not set
+# CONFIG_BPF_STREAM_PARSER is not set
+CONFIG_NET_FLOW_LIMIT=y
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# end of Network testing
+# end of Networking options
+
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+# CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+# CONFIG_AF_KCM is not set
+CONFIG_WIRELESS=y
+# CONFIG_CFG80211 is not set
+
+#
+# CFG80211 needs to be enabled for MAC80211
+#
+CONFIG_MAC80211_STA_HASH_MAX_SIZE=0
+# CONFIG_WIMAX is not set
+# CONFIG_RFKILL is not set
+CONFIG_NET_9P=y
+CONFIG_NET_9P_VIRTIO=y
+CONFIG_NET_9P_DEBUG=y
+# CONFIG_CAIF is not set
+# CONFIG_CEPH_LIB is not set
+# CONFIG_NFC is not set
+# CONFIG_PSAMPLE is not set
+# CONFIG_NET_IFE is not set
+# CONFIG_LWTUNNEL is not set
+CONFIG_DST_CACHE=y
+CONFIG_GRO_CELLS=y
+CONFIG_PAGE_POOL=y
+CONFIG_FAILOVER=y
+CONFIG_HAVE_EBPF_JIT=y
+
+#
+# Device Drivers
+#
+CONFIG_HAVE_PCI=y
+CONFIG_PCI=y
+CONFIG_PCI_DOMAINS=y
+CONFIG_PCI_DOMAINS_GENERIC=y
+CONFIG_PCIEPORTBUS=y
+CONFIG_PCIEAER=y
+# CONFIG_PCIEAER_INJECT is not set
+# CONFIG_PCIE_ECRC is not set
+CONFIG_PCIEASPM=y
+# CONFIG_PCIEASPM_DEBUG is not set
+CONFIG_PCIEASPM_DEFAULT=y
+# CONFIG_PCIEASPM_POWERSAVE is not set
+# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set
+# CONFIG_PCIEASPM_PERFORMANCE is not set
+# CONFIG_PCIE_DPC is not set
+# CONFIG_PCIE_PTM is not set
+# CONFIG_PCIE_BW is not set
+CONFIG_PCI_MSI=y
+CONFIG_PCI_MSI_IRQ_DOMAIN=y
+CONFIG_PCI_QUIRKS=y
+CONFIG_PCI_DEBUG=y
+# CONFIG_PCI_STUB is not set
+CONFIG_PCI_ECAM=y
+# CONFIG_PCI_IOV is not set
+# CONFIG_PCI_PRI is not set
+# CONFIG_PCI_PASID is not set
+# CONFIG_HOTPLUG_PCI is not set
+
+#
+# PCI controller drivers
+#
+# CONFIG_PCI_AARDVARK is not set
+
+#
+# Cadence PCIe controllers support
+#
+# CONFIG_PCIE_CADENCE_HOST is not set
+# end of Cadence PCIe controllers support
+
+# CONFIG_PCIE_XILINX_NWL is not set
+# CONFIG_PCI_FTPCI100 is not set
+# CONFIG_PCI_TEGRA is not set
+# CONFIG_PCIE_RCAR is not set
+CONFIG_PCI_HOST_COMMON=y
+CONFIG_PCI_HOST_GENERIC=y
+CONFIG_PCIE_XILINX=y
+# CONFIG_PCI_XGENE is not set
+# CONFIG_PCI_V3_SEMI is not set
+# CONFIG_PCIE_ALTERA is not set
+# CONFIG_PCI_HOST_THUNDER_PEM is not set
+# CONFIG_PCI_HOST_THUNDER_ECAM is not set
+# CONFIG_PCIE_ROCKCHIP_HOST is not set
+# CONFIG_PCIE_MEDIATEK is not set
+# CONFIG_PCIE_MOBIVEIL is not set
+
+#
+# DesignWare PCI Core Support
+#
+# CONFIG_PCIE_DW_PLAT_HOST is not set
+# CONFIG_PCI_EXYNOS is not set
+# CONFIG_PCI_IMX6 is not set
+# CONFIG_PCIE_SPEAR13XX is not set
+# CONFIG_PCI_LAYERSCAPE is not set
+# CONFIG_PCI_HISI is not set
+# CONFIG_PCIE_QCOM is not set
+# CONFIG_PCIE_ARMADA_8K is not set
+# CONFIG_PCIE_ARTPEC6_HOST is not set
+# CONFIG_PCIE_KIRIN is not set
+# CONFIG_PCIE_HISI_STB is not set
+# CONFIG_PCI_MESON is not set
+# CONFIG_PCIE_TEGRA194 is not set
+# CONFIG_PCIE_UNIPHIER is not set
+# CONFIG_PCIE_AL is not set
+# end of DesignWare PCI Core Support
+# end of PCI controller drivers
+
+#
+# PCI Endpoint
+#
+# CONFIG_PCI_ENDPOINT is not set
+# end of PCI Endpoint
+
+#
+# PCI switch controller drivers
+#
+# CONFIG_PCI_SW_SWITCHTEC is not set
+# end of PCI switch controller drivers
+
+# CONFIG_PCCARD is not set
+# CONFIG_RAPIDIO is not set
+
+#
+# Generic Driver Options
+#
+# CONFIG_UEVENT_HELPER is not set
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+
+#
+# Firmware loader
+#
+CONFIG_FW_LOADER=y
+CONFIG_EXTRA_FIRMWARE=""
+# CONFIG_FW_LOADER_USER_HELPER is not set
+# CONFIG_FW_LOADER_COMPRESS is not set
+# end of Firmware loader
+
+CONFIG_ALLOW_DEV_COREDUMP=y
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set
+# CONFIG_TEST_ASYNC_DRIVER_PROBE is not set
+CONFIG_GENERIC_CPU_DEVICES=y
+CONFIG_REGMAP=y
+CONFIG_REGMAP_MMIO=y
+CONFIG_DMA_SHARED_BUFFER=y
+# CONFIG_DMA_FENCE_TRACE is not set
+CONFIG_GENERIC_ARCH_TOPOLOGY=y
+# end of Generic Driver Options
+
+#
+# Bus devices
+#
+# CONFIG_MOXTET is not set
+# CONFIG_QCOM_EBI2 is not set
+# end of Bus devices
+
+# CONFIG_CONNECTOR is not set
+# CONFIG_GNSS is not set
+# CONFIG_MTD is not set
+CONFIG_DTC=y
+CONFIG_OF=y
+# CONFIG_OF_UNITTEST is not set
+# CONFIG_OF_ALL_DTBS is not set
+CONFIG_OF_FLATTREE=y
+CONFIG_OF_EARLY_FLATTREE=y
+CONFIG_OF_KOBJ=y
+CONFIG_OF_ADDRESS=y
+CONFIG_OF_IRQ=y
+CONFIG_OF_NET=y
+CONFIG_OF_MDIO=y
+CONFIG_OF_RESERVED_MEM=y
+# CONFIG_OF_OVERLAY is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_NULL_BLK is not set
+CONFIG_CDROM=y
+# CONFIG_BLK_DEV_PCIESSD_MTIP32XX is not set
+# CONFIG_BLK_DEV_UMEM is not set
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_LOOP_MIN_COUNT=8
+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
+# CONFIG_BLK_DEV_DRBD is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_SKD is not set
+# CONFIG_BLK_DEV_SX8 is not set
+# CONFIG_BLK_DEV_RAM is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+CONFIG_VIRTIO_BLK=y
+# CONFIG_VIRTIO_BLK_SCSI is not set
+# CONFIG_BLK_DEV_RBD is not set
+# CONFIG_BLK_DEV_RSXX is not set
+
+#
+# NVME Support
+#
+# CONFIG_BLK_DEV_NVME is not set
+# CONFIG_NVME_FC is not set
+# end of NVME Support
+
+#
+# Misc devices
+#
+# CONFIG_AD525X_DPOT is not set
+# CONFIG_DUMMY_IRQ is not set
+# CONFIG_PHANTOM is not set
+# CONFIG_INTEL_MID_PTI is not set
+# CONFIG_TIFM_CORE is not set
+# CONFIG_ICS932S401 is not set
+# CONFIG_ATMEL_SSC is not set
+# CONFIG_ENCLOSURE_SERVICES is not set
+# CONFIG_HP_ILO is not set
+# CONFIG_QCOM_COINCELL is not set
+# CONFIG_QCOM_FASTRPC is not set
+# CONFIG_APDS9802ALS is not set
+# CONFIG_ISL29003 is not set
+# CONFIG_ISL29020 is not set
+# CONFIG_SENSORS_TSL2550 is not set
+# CONFIG_SENSORS_BH1770 is not set
+# CONFIG_SENSORS_APDS990X is not set
+# CONFIG_HMC6352 is not set
+# CONFIG_DS1682 is not set
+# CONFIG_PCH_PHUB is not set
+# CONFIG_LATTICE_ECP3_CONFIG is not set
+# CONFIG_SRAM is not set
+# CONFIG_PCI_ENDPOINT_TEST is not set
+# CONFIG_XILINX_SDFEC is not set
+# CONFIG_PVPANIC is not set
+# CONFIG_C2PORT is not set
+
+#
+# EEPROM support
+#
+# CONFIG_EEPROM_AT24 is not set
+# CONFIG_EEPROM_AT25 is not set
+# CONFIG_EEPROM_LEGACY is not set
+# CONFIG_EEPROM_MAX6875 is not set
+# CONFIG_EEPROM_93CX6 is not set
+# CONFIG_EEPROM_93XX46 is not set
+# CONFIG_EEPROM_IDT_89HPESX is not set
+# CONFIG_EEPROM_EE1004 is not set
+# end of EEPROM support
+
+# CONFIG_CB710_CORE is not set
+
+#
+# Texas Instruments shared transport line discipline
+#
+# CONFIG_TI_ST is not set
+# end of Texas Instruments shared transport line discipline
+
+# CONFIG_SENSORS_LIS3_SPI is not set
+# CONFIG_SENSORS_LIS3_I2C is not set
+# CONFIG_ALTERA_STAPL is not set
+
+#
+# Intel MIC & related support
+#
+
+#
+# Intel MIC Bus Driver
+#
+
+#
+# SCIF Bus Driver
+#
+
+#
+# VOP Bus Driver
+#
+# CONFIG_VOP_BUS is not set
+
+#
+# Intel MIC Host Driver
+#
+
+#
+# Intel MIC Card Driver
+#
+
+#
+# SCIF Driver
+#
+
+#
+# Intel MIC Coprocessor State Management (COSM) Drivers
+#
+
+#
+# VOP Driver
+#
+# end of Intel MIC & related support
+
+# CONFIG_GENWQE is not set
+# CONFIG_ECHO is not set
+# CONFIG_MISC_ALCOR_PCI is not set
+# CONFIG_MISC_RTSX_PCI is not set
+# CONFIG_MISC_RTSX_USB is not set
+# CONFIG_HABANA_AI is not set
+# end of Misc devices
+
+#
+# SCSI device support
+#
+CONFIG_SCSI_MOD=y
+# CONFIG_RAID_ATTRS is not set
+CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
+CONFIG_SCSI_PROC_FS=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+# CONFIG_CHR_DEV_ST is not set
+CONFIG_BLK_DEV_SR=y
+# CONFIG_BLK_DEV_SR_VENDOR is not set
+# CONFIG_CHR_DEV_SG is not set
+# CONFIG_CHR_DEV_SCH is not set
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+# CONFIG_SCSI_SCAN_ASYNC is not set
+
+#
+# SCSI Transports
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+# CONFIG_SCSI_ISCSI_ATTRS is not set
+# CONFIG_SCSI_SAS_ATTRS is not set
+# CONFIG_SCSI_SAS_LIBSAS is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+# end of SCSI Transports
+
+CONFIG_SCSI_LOWLEVEL=y
+# CONFIG_ISCSI_TCP is not set
+# CONFIG_ISCSI_BOOT_SYSFS is not set
+# CONFIG_SCSI_CXGB3_ISCSI is not set
+# CONFIG_SCSI_CXGB4_ISCSI is not set
+# CONFIG_SCSI_BNX2_ISCSI is not set
+# CONFIG_BE2ISCSI is not set
+# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
+# CONFIG_SCSI_HPSA is not set
+# CONFIG_SCSI_3W_9XXX is not set
+# CONFIG_SCSI_3W_SAS is not set
+# CONFIG_SCSI_ACARD is not set
+# CONFIG_SCSI_AACRAID is not set
+# CONFIG_SCSI_AIC7XXX is not set
+# CONFIG_SCSI_AIC79XX is not set
+# CONFIG_SCSI_AIC94XX is not set
+# CONFIG_SCSI_HISI_SAS is not set
+# CONFIG_SCSI_MVSAS is not set
+# CONFIG_SCSI_MVUMI is not set
+# CONFIG_SCSI_ADVANSYS is not set
+# CONFIG_SCSI_ARCMSR is not set
+# CONFIG_SCSI_ESAS2R is not set
+# CONFIG_MEGARAID_NEWGEN is not set
+# CONFIG_MEGARAID_LEGACY is not set
+# CONFIG_MEGARAID_SAS is not set
+# CONFIG_SCSI_MPT3SAS is not set
+# CONFIG_SCSI_MPT2SAS is not set
+# CONFIG_SCSI_SMARTPQI is not set
+# CONFIG_SCSI_UFSHCD is not set
+# CONFIG_SCSI_HPTIOP is not set
+# CONFIG_SCSI_MYRB is not set
+# CONFIG_SCSI_MYRS is not set
+# CONFIG_SCSI_SNIC is not set
+# CONFIG_SCSI_DMX3191D is not set
+# CONFIG_SCSI_FDOMAIN_PCI is not set
+# CONFIG_SCSI_GDTH is not set
+# CONFIG_SCSI_IPS is not set
+# CONFIG_SCSI_INITIO is not set
+# CONFIG_SCSI_INIA100 is not set
+# CONFIG_SCSI_STEX is not set
+# CONFIG_SCSI_SYM53C8XX_2 is not set
+# CONFIG_SCSI_IPR is not set
+# CONFIG_SCSI_QLOGIC_1280 is not set
+# CONFIG_SCSI_QLA_ISCSI is not set
+# CONFIG_SCSI_DC395x is not set
+# CONFIG_SCSI_AM53C974 is not set
+# CONFIG_SCSI_WD719X is not set
+# CONFIG_SCSI_DEBUG is not set
+# CONFIG_SCSI_PMCRAID is not set
+# CONFIG_SCSI_PM8001 is not set
+CONFIG_SCSI_VIRTIO=y
+# CONFIG_SCSI_DH is not set
+# end of SCSI device support
+
+CONFIG_ATA=y
+CONFIG_ATA_VERBOSE_ERROR=y
+CONFIG_SATA_PMP=y
+
+#
+# Controllers with non-SFF native interface
+#
+CONFIG_SATA_AHCI=y
+CONFIG_SATA_MOBILE_LPM_POLICY=0
+CONFIG_SATA_AHCI_PLATFORM=y
+# CONFIG_AHCI_IMX is not set
+# CONFIG_AHCI_CEVA is not set
+# CONFIG_AHCI_QORIQ is not set
+# CONFIG_SATA_GEMINI is not set
+# CONFIG_SATA_INIC162X is not set
+# CONFIG_SATA_ACARD_AHCI is not set
+# CONFIG_SATA_SIL24 is not set
+CONFIG_ATA_SFF=y
+
+#
+# SFF controllers with custom DMA interface
+#
+# CONFIG_PDC_ADMA is not set
+# CONFIG_SATA_QSTOR is not set
+# CONFIG_SATA_SX4 is not set
+CONFIG_ATA_BMDMA=y
+
+#
+# SATA SFF controllers with BMDMA
+#
+# CONFIG_ATA_PIIX is not set
+# CONFIG_SATA_DWC is not set
+# CONFIG_SATA_HIGHBANK is not set
+# CONFIG_SATA_MV is not set
+# CONFIG_SATA_NV is not set
+# CONFIG_SATA_PROMISE is not set
+# CONFIG_SATA_RCAR is not set
+# CONFIG_SATA_SIL is not set
+# CONFIG_SATA_SIS is not set
+# CONFIG_SATA_SVW is not set
+# CONFIG_SATA_ULI is not set
+# CONFIG_SATA_VIA is not set
+# CONFIG_SATA_VITESSE is not set
+
+#
+# PATA SFF controllers with BMDMA
+#
+# CONFIG_PATA_ALI is not set
+# CONFIG_PATA_AMD is not set
+# CONFIG_PATA_ARASAN_CF is not set
+# CONFIG_PATA_ARTOP is not set
+# CONFIG_PATA_ATIIXP is not set
+# CONFIG_PATA_ATP867X is not set
+# CONFIG_PATA_CMD64X is not set
+# CONFIG_PATA_CS5520 is not set
+# CONFIG_PATA_CS5530 is not set
+# CONFIG_PATA_CS5536 is not set
+# CONFIG_PATA_CYPRESS is not set
+# CONFIG_PATA_EFAR is not set
+# CONFIG_PATA_HPT366 is not set
+# CONFIG_PATA_HPT37X is not set
+# CONFIG_PATA_HPT3X2N is not set
+# CONFIG_PATA_HPT3X3 is not set
+# CONFIG_PATA_IT8213 is not set
+# CONFIG_PATA_IT821X is not set
+# CONFIG_PATA_JMICRON is not set
+# CONFIG_PATA_MARVELL is not set
+# CONFIG_PATA_NETCELL is not set
+# CONFIG_PATA_NINJA32 is not set
+# CONFIG_PATA_NS87415 is not set
+# CONFIG_PATA_OLDPIIX is not set
+# CONFIG_PATA_OPTIDMA is not set
+# CONFIG_PATA_PDC2027X is not set
+# CONFIG_PATA_PDC_OLD is not set
+# CONFIG_PATA_RADISYS is not set
+# CONFIG_PATA_RDC is not set
+# CONFIG_PATA_SC1200 is not set
+# CONFIG_PATA_SCH is not set
+# CONFIG_PATA_SERVERWORKS is not set
+# CONFIG_PATA_SIL680 is not set
+# CONFIG_PATA_SIS is not set
+# CONFIG_PATA_TOSHIBA is not set
+# CONFIG_PATA_TRIFLEX is not set
+# CONFIG_PATA_VIA is not set
+# CONFIG_PATA_WINBOND is not set
+
+#
+# PIO-only SFF controllers
+#
+# CONFIG_PATA_CMD640_PCI is not set
+# CONFIG_PATA_MPIIX is not set
+# CONFIG_PATA_NS87410 is not set
+# CONFIG_PATA_OPTI is not set
+# CONFIG_PATA_PLATFORM is not set
+# CONFIG_PATA_RZ1000 is not set
+
+#
+# Generic fallback / legacy drivers
+#
+# CONFIG_ATA_GENERIC is not set
+# CONFIG_PATA_LEGACY is not set
+# CONFIG_MD is not set
+# CONFIG_TARGET_CORE is not set
+# CONFIG_FUSION is not set
+
+#
+# IEEE 1394 (FireWire) support
+#
+# CONFIG_FIREWIRE is not set
+# CONFIG_FIREWIRE_NOSY is not set
+# end of IEEE 1394 (FireWire) support
+
+CONFIG_NETDEVICES=y
+CONFIG_MII=y
+CONFIG_NET_CORE=y
+# CONFIG_BONDING is not set
+# CONFIG_DUMMY is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_NET_FC is not set
+# CONFIG_NET_TEAM is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_IPVLAN is not set
+# CONFIG_VXLAN is not set
+# CONFIG_GENEVE is not set
+# CONFIG_GTP is not set
+# CONFIG_MACSEC is not set
+# CONFIG_NETCONSOLE is not set
+# CONFIG_TUN is not set
+# CONFIG_TUN_VNET_CROSS_LE is not set
+# CONFIG_VETH is not set
+CONFIG_VIRTIO_NET=y
+# CONFIG_NLMON is not set
+# CONFIG_ARCNET is not set
+
+#
+# CAIF transport drivers
+#
+
+#
+# Distributed Switch Architecture drivers
+#
+# end of Distributed Switch Architecture drivers
+
+CONFIG_ETHERNET=y
+CONFIG_NET_VENDOR_3COM=y
+# CONFIG_VORTEX is not set
+# CONFIG_TYPHOON is not set
+CONFIG_NET_VENDOR_ADAPTEC=y
+# CONFIG_ADAPTEC_STARFIRE is not set
+CONFIG_NET_VENDOR_AGERE=y
+# CONFIG_ET131X is not set
+CONFIG_NET_VENDOR_ALACRITECH=y
+# CONFIG_SLICOSS is not set
+CONFIG_NET_VENDOR_ALTEON=y
+# CONFIG_ACENIC is not set
+# CONFIG_ALTERA_TSE is not set
+CONFIG_NET_VENDOR_AMAZON=y
+# CONFIG_ENA_ETHERNET is not set
+CONFIG_NET_VENDOR_AMD=y
+# CONFIG_AMD8111_ETH is not set
+# CONFIG_PCNET32 is not set
+# CONFIG_AMD_XGBE is not set
+# CONFIG_NET_XGENE is not set
+# CONFIG_NET_XGENE_V2 is not set
+CONFIG_NET_VENDOR_AQUANTIA=y
+# CONFIG_AQTION is not set
+CONFIG_NET_VENDOR_ARC=y
+# CONFIG_ARC_EMAC is not set
+CONFIG_NET_VENDOR_ATHEROS=y
+# CONFIG_ATL2 is not set
+# CONFIG_ATL1 is not set
+# CONFIG_ATL1E is not set
+# CONFIG_ATL1C is not set
+# CONFIG_ALX is not set
+CONFIG_NET_VENDOR_AURORA=y
+# CONFIG_AURORA_NB8800 is not set
+CONFIG_NET_VENDOR_BROADCOM=y
+# CONFIG_B44 is not set
+# CONFIG_BCMGENET is not set
+# CONFIG_BNX2 is not set
+# CONFIG_CNIC is not set
+# CONFIG_TIGON3 is not set
+# CONFIG_BNX2X is not set
+# CONFIG_BGMAC_PLATFORM is not set
+# CONFIG_SYSTEMPORT is not set
+# CONFIG_BNXT is not set
+CONFIG_NET_VENDOR_BROCADE=y
+# CONFIG_BNA is not set
+CONFIG_NET_VENDOR_CADENCE=y
+CONFIG_MACB=y
+CONFIG_MACB_USE_HWSTAMP=y
+# CONFIG_MACB_PCI is not set
+# CONFIG_NET_CALXEDA_XGMAC is not set
+CONFIG_NET_VENDOR_CAVIUM=y
+# CONFIG_THUNDER_NIC_PF is not set
+# CONFIG_THUNDER_NIC_VF is not set
+# CONFIG_THUNDER_NIC_BGX is not set
+# CONFIG_THUNDER_NIC_RGX is not set
+# CONFIG_CAVIUM_PTP is not set
+# CONFIG_LIQUIDIO is not set
+# CONFIG_LIQUIDIO_VF is not set
+CONFIG_NET_VENDOR_CHELSIO=y
+# CONFIG_CHELSIO_T1 is not set
+# CONFIG_CHELSIO_T3 is not set
+# CONFIG_CHELSIO_T4 is not set
+# CONFIG_CHELSIO_T4VF is not set
+CONFIG_NET_VENDOR_CISCO=y
+# CONFIG_ENIC is not set
+CONFIG_NET_VENDOR_CORTINA=y
+# CONFIG_GEMINI_ETHERNET is not set
+# CONFIG_CX_ECAT is not set
+# CONFIG_DNET is not set
+CONFIG_NET_VENDOR_DEC=y
+# CONFIG_NET_TULIP is not set
+CONFIG_NET_VENDOR_DLINK=y
+# CONFIG_DL2K is not set
+# CONFIG_SUNDANCE is not set
+CONFIG_NET_VENDOR_EMULEX=y
+# CONFIG_BE2NET is not set
+CONFIG_NET_VENDOR_EZCHIP=y
+# CONFIG_EZCHIP_NPS_MANAGEMENT_ENET is not set
+CONFIG_NET_VENDOR_FARADAY=y
+CONFIG_NET_VENDOR_FREESCALE=y
+# CONFIG_FEC is not set
+# CONFIG_FSL_FMAN is not set
+# CONFIG_FSL_PQ_MDIO is not set
+# CONFIG_FSL_XGMAC_MDIO is not set
+# CONFIG_GIANFAR is not set
+# CONFIG_FSL_ENETC is not set
+# CONFIG_FSL_ENETC_VF is not set
+# CONFIG_FSL_ENETC_MDIO is not set
+CONFIG_NET_VENDOR_GOOGLE=y
+# CONFIG_GVE is not set
+CONFIG_NET_VENDOR_HISILICON=y
+# CONFIG_HIX5HD2_GMAC is not set
+# CONFIG_HISI_FEMAC is not set
+# CONFIG_HIP04_ETH is not set
+# CONFIG_HNS is not set
+# CONFIG_HNS_DSAF is not set
+# CONFIG_HNS_ENET is not set
+# CONFIG_HNS3 is not set
+CONFIG_NET_VENDOR_HP=y
+# CONFIG_HP100 is not set
+CONFIG_NET_VENDOR_HUAWEI=y
+CONFIG_NET_VENDOR_I825XX=y
+CONFIG_NET_VENDOR_INTEL=y
+# CONFIG_E100 is not set
+# CONFIG_E1000 is not set
+CONFIG_E1000E=y
+# CONFIG_IGB is not set
+# CONFIG_IGBVF is not set
+# CONFIG_IXGB is not set
+# CONFIG_IXGBE is not set
+# CONFIG_IXGBEVF is not set
+# CONFIG_I40E is not set
+# CONFIG_I40EVF is not set
+# CONFIG_ICE is not set
+# CONFIG_FM10K is not set
+# CONFIG_IGC is not set
+# CONFIG_JME is not set
+CONFIG_NET_VENDOR_MARVELL=y
+# CONFIG_MV643XX_ETH is not set
+# CONFIG_MVMDIO is not set
+# CONFIG_MVNETA is not set
+# CONFIG_MVPP2 is not set
+# CONFIG_PXA168_ETH is not set
+# CONFIG_SKGE is not set
+# CONFIG_SKY2 is not set
+# CONFIG_OCTEONTX2_AF is not set
+CONFIG_NET_VENDOR_MELLANOX=y
+# CONFIG_MLX4_EN is not set
+# CONFIG_MLX5_CORE is not set
+# CONFIG_MLXSW_CORE is not set
+# CONFIG_MLXFW is not set
+CONFIG_NET_VENDOR_MICREL=y
+# CONFIG_KS8842 is not set
+# CONFIG_KS8851 is not set
+# CONFIG_KS8851_MLL is not set
+# CONFIG_KSZ884X_PCI is not set
+CONFIG_NET_VENDOR_MICROCHIP=y
+# CONFIG_ENC28J60 is not set
+# CONFIG_ENCX24J600 is not set
+# CONFIG_LAN743X is not set
+CONFIG_NET_VENDOR_MICROSEMI=y
+CONFIG_NET_VENDOR_MYRI=y
+# CONFIG_MYRI10GE is not set
+# CONFIG_FEALNX is not set
+CONFIG_NET_VENDOR_NATSEMI=y
+# CONFIG_NATSEMI is not set
+# CONFIG_NS83820 is not set
+CONFIG_NET_VENDOR_NETERION=y
+# CONFIG_S2IO is not set
+# CONFIG_VXGE is not set
+CONFIG_NET_VENDOR_NETRONOME=y
+# CONFIG_NFP is not set
+CONFIG_NET_VENDOR_NI=y
+# CONFIG_NI_XGE_MANAGEMENT_ENET is not set
+CONFIG_NET_VENDOR_8390=y
+# CONFIG_AX88796 is not set
+# CONFIG_NE2K_PCI is not set
+CONFIG_NET_VENDOR_NVIDIA=y
+# CONFIG_FORCEDETH is not set
+# CONFIG_LPC_ENET is not set
+CONFIG_NET_VENDOR_OKI=y
+# CONFIG_PCH_GBE is not set
+# CONFIG_ETHOC is not set
+CONFIG_NET_VENDOR_PACKET_ENGINES=y
+# CONFIG_HAMACHI is not set
+# CONFIG_YELLOWFIN is not set
+CONFIG_NET_VENDOR_PENSANDO=y
+# CONFIG_IONIC is not set
+CONFIG_NET_VENDOR_QLOGIC=y
+# CONFIG_QLA3XXX is not set
+# CONFIG_QLCNIC is not set
+# CONFIG_NETXEN_NIC is not set
+# CONFIG_QED is not set
+CONFIG_NET_VENDOR_QUALCOMM=y
+# CONFIG_QCA7000_SPI is not set
+# CONFIG_QCOM_EMAC is not set
+# CONFIG_RMNET is not set
+CONFIG_NET_VENDOR_RDC=y
+# CONFIG_R6040 is not set
+CONFIG_NET_VENDOR_REALTEK=y
+# CONFIG_8139CP is not set
+# CONFIG_8139TOO is not set
+CONFIG_R8169=y
+CONFIG_NET_VENDOR_RENESAS=y
+# CONFIG_SH_ETH is not set
+# CONFIG_RAVB is not set
+CONFIG_NET_VENDOR_ROCKER=y
+CONFIG_NET_VENDOR_SAMSUNG=y
+# CONFIG_SXGBE_ETH is not set
+CONFIG_NET_VENDOR_SEEQ=y
+CONFIG_NET_VENDOR_SOLARFLARE=y
+# CONFIG_SFC is not set
+# CONFIG_SFC_FALCON is not set
+CONFIG_NET_VENDOR_SILAN=y
+# CONFIG_SC92031 is not set
+CONFIG_NET_VENDOR_SIS=y
+# CONFIG_SIS900 is not set
+# CONFIG_SIS190 is not set
+CONFIG_NET_VENDOR_SMSC=y
+# CONFIG_EPIC100 is not set
+# CONFIG_SMSC911X is not set
+# CONFIG_SMSC9420 is not set
+CONFIG_NET_VENDOR_SOCIONEXT=y
+# CONFIG_SNI_AVE is not set
+# CONFIG_SNI_NETSEC is not set
+CONFIG_NET_VENDOR_STMICRO=y
+CONFIG_STMMAC_ETH=y
+# CONFIG_STMMAC_SELFTESTS is not set
+CONFIG_STMMAC_PLATFORM=y
+# CONFIG_DWMAC_DWC_QOS_ETH is not set
+CONFIG_DWMAC_GENERIC=y
+# CONFIG_DWMAC_ANARION is not set
+# CONFIG_DWMAC_IPQ806X is not set
+# CONFIG_DWMAC_LPC18XX is not set
+# CONFIG_DWMAC_MEDIATEK is not set
+# CONFIG_DWMAC_MESON is not set
+# CONFIG_DWMAC_OXNAS is not set
+# CONFIG_DWMAC_QCOM_ETHQOS is not set
+# CONFIG_DWMAC_ROCKCHIP is not set
+# CONFIG_DWMAC_SOCFPGA is not set
+# CONFIG_DWMAC_STI is not set
+# CONFIG_DWMAC_STM32 is not set
+# CONFIG_DWMAC_SUNXI is not set
+# CONFIG_DWMAC_SUN8I is not set
+CONFIG_STMMAC_PCI=y
+CONFIG_NET_VENDOR_SUN=y
+# CONFIG_HAPPYMEAL is not set
+# CONFIG_SUNGEM is not set
+# CONFIG_CASSINI is not set
+# CONFIG_NIU is not set
+CONFIG_NET_VENDOR_SYNOPSYS=y
+# CONFIG_DWC_XLGMAC is not set
+CONFIG_NET_VENDOR_TEHUTI=y
+# CONFIG_TEHUTI is not set
+CONFIG_NET_VENDOR_TI=y
+# CONFIG_TI_DAVINCI_EMAC is not set
+# CONFIG_TI_DAVINCI_MDIO is not set
+# CONFIG_TI_CPSW_PHY_SEL is not set
+# CONFIG_TI_CPSW is not set
+# CONFIG_TI_CPTS is not set
+# CONFIG_TLAN is not set
+CONFIG_NET_VENDOR_VIA=y
+# CONFIG_VIA_RHINE is not set
+# CONFIG_VIA_VELOCITY is not set
+CONFIG_NET_VENDOR_WIZNET=y
+# CONFIG_WIZNET_W5100 is not set
+# CONFIG_WIZNET_W5300 is not set
+CONFIG_NET_VENDOR_XILINX=y
+# CONFIG_XILINX_AXI_EMAC is not set
+# CONFIG_XILINX_LL_TEMAC is not set
+# CONFIG_FDDI is not set
+# CONFIG_HIPPI is not set
+CONFIG_MDIO_DEVICE=y
+CONFIG_MDIO_BUS=y
+# CONFIG_MDIO_ASPEED is not set
+# CONFIG_MDIO_BCM_IPROC is not set
+# CONFIG_MDIO_BCM_UNIMAC is not set
+# CONFIG_MDIO_BITBANG is not set
+# CONFIG_MDIO_BUS_MUX_BCM_IPROC is not set
+# CONFIG_MDIO_BUS_MUX_MESON_G12A is not set
+# CONFIG_MDIO_BUS_MUX_MMIOREG is not set
+# CONFIG_MDIO_BUS_MUX_MULTIPLEXER is not set
+# CONFIG_MDIO_HISI_FEMAC is not set
+# CONFIG_MDIO_MOXART is not set
+# CONFIG_MDIO_MSCC_MIIM is not set
+# CONFIG_MDIO_OCTEON is not set
+# CONFIG_MDIO_SUN4I is not set
+# CONFIG_MDIO_THUNDER is not set
+# CONFIG_MDIO_XGENE is not set
+CONFIG_PHYLINK=y
+CONFIG_PHYLIB=y
+CONFIG_SWPHY=y
+
+#
+# MII PHY device drivers
+#
+# CONFIG_SFP is not set
+# CONFIG_ADIN_PHY is not set
+# CONFIG_AMD_PHY is not set
+# CONFIG_AQUANTIA_PHY is not set
+# CONFIG_AX88796B_PHY is not set
+# CONFIG_AT803X_PHY is not set
+# CONFIG_BCM63XX_PHY is not set
+# CONFIG_BCM7XXX_PHY is not set
+# CONFIG_BCM87XX_PHY is not set
+# CONFIG_BROADCOM_PHY is not set
+# CONFIG_CICADA_PHY is not set
+# CONFIG_CORTINA_PHY is not set
+# CONFIG_DAVICOM_PHY is not set
+# CONFIG_DP83822_PHY is not set
+# CONFIG_DP83TC811_PHY is not set
+# CONFIG_DP83848_PHY is not set
+# CONFIG_DP83867_PHY is not set
+CONFIG_FIXED_PHY=y
+# CONFIG_ICPLUS_PHY is not set
+# CONFIG_INTEL_XWAY_PHY is not set
+# CONFIG_LSI_ET1011C_PHY is not set
+# CONFIG_LXT_PHY is not set
+# CONFIG_MARVELL_PHY is not set
+# CONFIG_MARVELL_10G_PHY is not set
+# CONFIG_MESON_GXL_PHY is not set
+# CONFIG_MICREL_PHY is not set
+# CONFIG_MICROCHIP_PHY is not set
+# CONFIG_MICROCHIP_T1_PHY is not set
+CONFIG_MICROSEMI_PHY=y
+# CONFIG_NATIONAL_PHY is not set
+# CONFIG_NXP_TJA11XX_PHY is not set
+# CONFIG_QSEMI_PHY is not set
+CONFIG_REALTEK_PHY=y
+# CONFIG_RENESAS_PHY is not set
+# CONFIG_ROCKCHIP_PHY is not set
+# CONFIG_SMSC_PHY is not set
+# CONFIG_STE10XP is not set
+# CONFIG_TERANETICS_PHY is not set
+# CONFIG_VITESSE_PHY is not set
+# CONFIG_XILINX_GMII2RGMII is not set
+# CONFIG_MICREL_KS8995MA is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+CONFIG_USB_NET_DRIVERS=y
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_RTL8150 is not set
+# CONFIG_USB_RTL8152 is not set
+# CONFIG_USB_LAN78XX is not set
+# CONFIG_USB_USBNET is not set
+# CONFIG_USB_IPHETH is not set
+CONFIG_WLAN=y
+# CONFIG_WIRELESS_WDS is not set
+CONFIG_WLAN_VENDOR_ADMTEK=y
+CONFIG_WLAN_VENDOR_ATH=y
+# CONFIG_ATH_DEBUG is not set
+# CONFIG_ATH5K_PCI is not set
+CONFIG_WLAN_VENDOR_ATMEL=y
+CONFIG_WLAN_VENDOR_BROADCOM=y
+CONFIG_WLAN_VENDOR_CISCO=y
+CONFIG_WLAN_VENDOR_INTEL=y
+CONFIG_WLAN_VENDOR_INTERSIL=y
+# CONFIG_HOSTAP is not set
+# CONFIG_PRISM54 is not set
+CONFIG_WLAN_VENDOR_MARVELL=y
+CONFIG_WLAN_VENDOR_MEDIATEK=y
+CONFIG_WLAN_VENDOR_RALINK=y
+CONFIG_WLAN_VENDOR_REALTEK=y
+CONFIG_WLAN_VENDOR_RSI=y
+CONFIG_WLAN_VENDOR_ST=y
+CONFIG_WLAN_VENDOR_TI=y
+CONFIG_WLAN_VENDOR_ZYDAS=y
+CONFIG_WLAN_VENDOR_QUANTENNA=y
+
+#
+# Enable WiMAX (Networking options) to see the WiMAX drivers
+#
+# CONFIG_WAN is not set
+# CONFIG_VMXNET3 is not set
+# CONFIG_NETDEVSIM is not set
+CONFIG_NET_FAILOVER=y
+# CONFIG_ISDN is not set
+# CONFIG_NVM is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+# CONFIG_INPUT_SPARSEKMAP is not set
+# CONFIG_INPUT_MATRIXKMAP is not set
+
+#
+# Userland interfaces
+#
+CONFIG_INPUT_MOUSEDEV=y
+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+CONFIG_INPUT_KEYBOARD=y
+# CONFIG_KEYBOARD_ADP5588 is not set
+# CONFIG_KEYBOARD_ADP5589 is not set
+CONFIG_KEYBOARD_ATKBD=y
+# CONFIG_KEYBOARD_QT1050 is not set
+# CONFIG_KEYBOARD_QT1070 is not set
+# CONFIG_KEYBOARD_QT2160 is not set
+# CONFIG_KEYBOARD_DLINK_DIR685 is not set
+# CONFIG_KEYBOARD_LKKBD is not set
+# CONFIG_KEYBOARD_EP93XX is not set
+# CONFIG_KEYBOARD_GPIO is not set
+# CONFIG_KEYBOARD_TCA6416 is not set
+# CONFIG_KEYBOARD_TCA8418 is not set
+# CONFIG_KEYBOARD_MATRIX is not set
+# CONFIG_KEYBOARD_LM8333 is not set
+# CONFIG_KEYBOARD_MAX7359 is not set
+# CONFIG_KEYBOARD_MCS is not set
+# CONFIG_KEYBOARD_MPR121 is not set
+# CONFIG_KEYBOARD_SNVS_PWRKEY is not set
+# CONFIG_KEYBOARD_NEWTON is not set
+# CONFIG_KEYBOARD_OPENCORES is not set
+# CONFIG_KEYBOARD_SAMSUNG is not set
+# CONFIG_KEYBOARD_GOLDFISH_EVENTS is not set
+# CONFIG_KEYBOARD_STOWAWAY is not set
+# CONFIG_KEYBOARD_ST_KEYSCAN is not set
+# CONFIG_KEYBOARD_SUNKBD is not set
+# CONFIG_KEYBOARD_SH_KEYSC is not set
+# CONFIG_KEYBOARD_OMAP4 is not set
+# CONFIG_KEYBOARD_XTKBD is not set
+# CONFIG_KEYBOARD_CAP11XX is not set
+# CONFIG_KEYBOARD_BCM is not set
+CONFIG_INPUT_MOUSE=y
+CONFIG_MOUSE_PS2=y
+CONFIG_MOUSE_PS2_ALPS=y
+CONFIG_MOUSE_PS2_BYD=y
+CONFIG_MOUSE_PS2_LOGIPS2PP=y
+CONFIG_MOUSE_PS2_SYNAPTICS=y
+CONFIG_MOUSE_PS2_SYNAPTICS_SMBUS=y
+CONFIG_MOUSE_PS2_CYPRESS=y
+CONFIG_MOUSE_PS2_TRACKPOINT=y
+# CONFIG_MOUSE_PS2_ELANTECH is not set
+# CONFIG_MOUSE_PS2_SENTELIC is not set
+# CONFIG_MOUSE_PS2_TOUCHKIT is not set
+CONFIG_MOUSE_PS2_FOCALTECH=y
+CONFIG_MOUSE_PS2_SMBUS=y
+# CONFIG_MOUSE_SERIAL is not set
+# CONFIG_MOUSE_APPLETOUCH is not set
+# CONFIG_MOUSE_BCM5974 is not set
+# CONFIG_MOUSE_CYAPA is not set
+# CONFIG_MOUSE_ELAN_I2C is not set
+# CONFIG_MOUSE_VSXXXAA is not set
+# CONFIG_MOUSE_GPIO is not set
+# CONFIG_MOUSE_SYNAPTICS_I2C is not set
+# CONFIG_MOUSE_SYNAPTICS_USB is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+# CONFIG_RMI4_CORE is not set
+
+#
+# Hardware I/O ports
+#
+CONFIG_SERIO=y
+CONFIG_SERIO_SERPORT=y
+# CONFIG_SERIO_PCIPS2 is not set
+CONFIG_SERIO_LIBPS2=y
+# CONFIG_SERIO_RAW is not set
+# CONFIG_SERIO_ALTERA_PS2 is not set
+# CONFIG_SERIO_PS2MULT is not set
+# CONFIG_SERIO_ARC_PS2 is not set
+# CONFIG_SERIO_APBPS2 is not set
+# CONFIG_SERIO_OLPC_APSP is not set
+# CONFIG_SERIO_SUN4I_PS2 is not set
+# CONFIG_USERIO is not set
+# CONFIG_GAMEPORT is not set
+# end of Hardware I/O ports
+# end of Input device support
+
+#
+# Character devices
+#
+CONFIG_TTY=y
+CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+CONFIG_VT_HW_CONSOLE_BINDING=y
+CONFIG_UNIX98_PTYS=y
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=256
+# CONFIG_SERIAL_NONSTANDARD is not set
+# CONFIG_NOZOMI is not set
+# CONFIG_N_GSM is not set
+# CONFIG_TRACE_SINK is not set
+# CONFIG_NULL_TTY is not set
+CONFIG_LDISC_AUTOLOAD=y
+CONFIG_DEVMEM=y
+# CONFIG_DEVKMEM is not set
+
+#
+# Serial drivers
+#
+CONFIG_SERIAL_EARLYCON=y
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y
+# CONFIG_SERIAL_8250_FINTEK is not set
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_DMA=y
+CONFIG_SERIAL_8250_PCI=y
+CONFIG_SERIAL_8250_EXAR=y
+CONFIG_SERIAL_8250_NR_UARTS=4
+CONFIG_SERIAL_8250_RUNTIME_UARTS=4
+# CONFIG_SERIAL_8250_EXTENDED is not set
+# CONFIG_SERIAL_8250_ASPEED_VUART is not set
+CONFIG_SERIAL_8250_DWLIB=y
+CONFIG_SERIAL_8250_DW=y
+# CONFIG_SERIAL_8250_RT288X is not set
+# CONFIG_SERIAL_8250_LPC18XX is not set
+# CONFIG_SERIAL_8250_UNIPHIER is not set
+# CONFIG_SERIAL_8250_INGENIC is not set
+CONFIG_SERIAL_8250_LPSS=y
+CONFIG_SERIAL_8250_MID=y
+CONFIG_SERIAL_OF_PLATFORM=y
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_EARLYCON_RISCV_SBI=y
+# CONFIG_SERIAL_ATMEL is not set
+# CONFIG_SERIAL_CLPS711X is not set
+# CONFIG_SERIAL_MAX3100 is not set
+# CONFIG_SERIAL_MAX310X is not set
+# CONFIG_SERIAL_IMX is not set
+# CONFIG_SERIAL_UARTLITE is not set
+# CONFIG_SERIAL_SH_SCI is not set
+# CONFIG_SERIAL_HS_LPC32XX is not set
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+# CONFIG_SERIAL_JSM is not set
+CONFIG_SERIAL_SIFIVE=y
+CONFIG_SERIAL_SIFIVE_CONSOLE=y
+# CONFIG_SERIAL_SCCNXP is not set
+# CONFIG_SERIAL_SC16IS7XX is not set
+# CONFIG_SERIAL_TIMBERDALE is not set
+# CONFIG_SERIAL_BCM63XX is not set
+# CONFIG_SERIAL_ALTERA_JTAGUART is not set
+# CONFIG_SERIAL_ALTERA_UART is not set
+# CONFIG_SERIAL_IFX6X60 is not set
+# CONFIG_SERIAL_PCH_UART is not set
+# CONFIG_SERIAL_MXS_AUART is not set
+# CONFIG_SERIAL_XILINX_PS_UART is not set
+# CONFIG_SERIAL_MPS2_UART is not set
+# CONFIG_SERIAL_ARC is not set
+# CONFIG_SERIAL_RP2 is not set
+# CONFIG_SERIAL_FSL_LPUART is not set
+# CONFIG_SERIAL_FSL_LINFLEXUART is not set
+# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set
+# CONFIG_SERIAL_ST_ASC is not set
+# CONFIG_SERIAL_STM32 is not set
+# CONFIG_SERIAL_MVEBU_UART is not set
+# CONFIG_SERIAL_OWL is not set
+# CONFIG_SERIAL_RDA is not set
+# CONFIG_SERIAL_MILBEAUT_USIO is not set
+# end of Serial drivers
+
+# CONFIG_SERIAL_DEV_BUS is not set
+# CONFIG_TTY_PRINTK is not set
+CONFIG_HVC_DRIVER=y
+CONFIG_HVC_RISCV_SBI=y
+CONFIG_VIRTIO_CONSOLE=y
+# CONFIG_IPMI_HANDLER is not set
+# CONFIG_ASPEED_KCS_IPMI_BMC is not set
+# CONFIG_NPCM7XX_KCS_IPMI_BMC is not set
+# CONFIG_ASPEED_BT_IPMI_BMC is not set
+CONFIG_HW_RANDOM=y
+# CONFIG_HW_RANDOM_TIMERIOMEM is not set
+CONFIG_HW_RANDOM_VIRTIO=y
+CONFIG_HW_RANDOM_STM32=y
+CONFIG_HW_RANDOM_MESON=y
+CONFIG_HW_RANDOM_CAVIUM=y
+CONFIG_HW_RANDOM_MTK=y
+CONFIG_HW_RANDOM_EXYNOS=y
+# CONFIG_APPLICOM is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+CONFIG_DEVPORT=y
+# CONFIG_XILLYBUS is not set
+# end of Character devices
+
+# CONFIG_RANDOM_TRUST_BOOTLOADER is not set
+
+#
+# I2C support
+#
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_COMPAT=y
+# CONFIG_I2C_CHARDEV is not set
+# CONFIG_I2C_MUX is not set
+CONFIG_I2C_HELPER_AUTO=y
+CONFIG_I2C_ALGOBIT=y
+
+#
+# I2C Hardware Bus support
+#
+
+#
+# PC SMBus host controller drivers
+#
+# CONFIG_I2C_ALI1535 is not set
+# CONFIG_I2C_ALI1563 is not set
+# CONFIG_I2C_ALI15X3 is not set
+# CONFIG_I2C_AMD756 is not set
+# CONFIG_I2C_AMD8111 is not set
+# CONFIG_I2C_HIX5HD2 is not set
+# CONFIG_I2C_I801 is not set
+# CONFIG_I2C_ISCH is not set
+# CONFIG_I2C_PIIX4 is not set
+# CONFIG_I2C_NFORCE2 is not set
+# CONFIG_I2C_NVIDIA_GPU is not set
+# CONFIG_I2C_SIS5595 is not set
+# CONFIG_I2C_SIS630 is not set
+# CONFIG_I2C_SIS96X is not set
+# CONFIG_I2C_VIA is not set
+# CONFIG_I2C_VIAPRO is not set
+
+#
+# I2C system bus drivers (mostly embedded / system-on-chip)
+#
+# CONFIG_I2C_ASPEED is not set
+# CONFIG_I2C_AXXIA is not set
+# CONFIG_I2C_BCM_IPROC is not set
+CONFIG_I2C_BRCMSTB=y
+# CONFIG_I2C_CBUS_GPIO is not set
+# CONFIG_I2C_DESIGNWARE_PLATFORM is not set
+# CONFIG_I2C_DESIGNWARE_PCI is not set
+# CONFIG_I2C_EFM32 is not set
+# CONFIG_I2C_EG20T is not set
+# CONFIG_I2C_EMEV2 is not set
+# CONFIG_I2C_GPIO is not set
+# CONFIG_I2C_IMG is not set
+# CONFIG_I2C_IMX_LPI2C is not set
+# CONFIG_I2C_JZ4780 is not set
+# CONFIG_I2C_LPC2K is not set
+# CONFIG_I2C_MESON is not set
+# CONFIG_I2C_MT65XX is not set
+# CONFIG_I2C_MT7621 is not set
+# CONFIG_I2C_OCORES is not set
+# CONFIG_I2C_OWL is not set
+# CONFIG_I2C_PCA_PLATFORM is not set
+# CONFIG_I2C_RIIC is not set
+# CONFIG_I2C_RK3X is not set
+# CONFIG_I2C_SH_MOBILE is not set
+# CONFIG_I2C_SIMTEC is not set
+# CONFIG_I2C_STM32F4 is not set
+# CONFIG_I2C_STM32F7 is not set
+# CONFIG_I2C_SUN6I_P2WI is not set
+# CONFIG_I2C_SYNQUACER is not set
+# CONFIG_I2C_UNIPHIER is not set
+# CONFIG_I2C_UNIPHIER_F is not set
+# CONFIG_I2C_VERSATILE is not set
+# CONFIG_I2C_THUNDERX is not set
+# CONFIG_I2C_XILINX is not set
+# CONFIG_I2C_XLP9XX is not set
+# CONFIG_I2C_RCAR is not set
+
+#
+# External I2C/SMBus adapter drivers
+#
+# CONFIG_I2C_DIOLAN_U2C is not set
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_ROBOTFUZZ_OSIF is not set
+# CONFIG_I2C_TAOS_EVM is not set
+# CONFIG_I2C_TINY_USB is not set
+
+#
+# Other I2C/SMBus bus drivers
+#
+# end of I2C Hardware Bus support
+
+# CONFIG_I2C_STUB is not set
+# CONFIG_I2C_SLAVE is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# end of I2C support
+
+# CONFIG_I3C is not set
+CONFIG_SPI=y
+# CONFIG_SPI_DEBUG is not set
+CONFIG_SPI_MASTER=y
+# CONFIG_SPI_MEM is not set
+
+#
+# SPI Master Controller Drivers
+#
+# CONFIG_SPI_ALTERA is not set
+# CONFIG_SPI_ATH79 is not set
+# CONFIG_SPI_ARMADA_3700 is not set
+# CONFIG_SPI_ATMEL is not set
+# CONFIG_SPI_AXI_SPI_ENGINE is not set
+# CONFIG_SPI_BCM2835AUX is not set
+# CONFIG_SPI_BCM63XX is not set
+# CONFIG_SPI_BCM63XX_HSSPI is not set
+# CONFIG_SPI_BCM_QSPI is not set
+# CONFIG_SPI_BITBANG is not set
+# CONFIG_SPI_CADENCE is not set
+# CONFIG_SPI_CLPS711X is not set
+# CONFIG_SPI_DESIGNWARE is not set
+# CONFIG_SPI_EP93XX is not set
+# CONFIG_SPI_FSL_LPSPI is not set
+# CONFIG_SPI_FSL_QUADSPI is not set
+# CONFIG_SPI_NXP_FLEXSPI is not set
+# CONFIG_SPI_GPIO is not set
+# CONFIG_SPI_IMG_SPFI is not set
+# CONFIG_SPI_IMX is not set
+# CONFIG_SPI_JCORE is not set
+# CONFIG_SPI_LP8841_RTC is not set
+# CONFIG_SPI_FSL_SPI is not set
+# CONFIG_SPI_FSL_DSPI is not set
+# CONFIG_SPI_MESON_SPICC is not set
+# CONFIG_SPI_MESON_SPIFC is not set
+# CONFIG_SPI_MT65XX is not set
+# CONFIG_SPI_MT7621 is not set
+# CONFIG_SPI_NPCM_FIU is not set
+# CONFIG_SPI_NPCM_PSPI is not set
+# CONFIG_SPI_LANTIQ_SSC is not set
+# CONFIG_SPI_OC_TINY is not set
+# CONFIG_SPI_OMAP24XX is not set
+# CONFIG_SPI_TI_QSPI is not set
+# CONFIG_SPI_OMAP_100K is not set
+# CONFIG_SPI_ORION is not set
+# CONFIG_SPI_PIC32 is not set
+# CONFIG_SPI_PIC32_SQI is not set
+# CONFIG_SPI_PXA2XX is not set
+# CONFIG_SPI_ROCKCHIP is not set
+# CONFIG_SPI_RSPI is not set
+# CONFIG_SPI_S3C64XX is not set
+# CONFIG_SPI_SC18IS602 is not set
+# CONFIG_SPI_SH_MSIOF is not set
+# CONFIG_SPI_SH is not set
+# CONFIG_SPI_SH_HSPI is not set
+CONFIG_SPI_SIFIVE=y
+# CONFIG_SPI_SPRD is not set
+# CONFIG_SPI_SPRD_ADI is not set
+# CONFIG_SPI_STM32 is not set
+# CONFIG_SPI_STM32_QSPI is not set
+# CONFIG_SPI_ST_SSC4 is not set
+# CONFIG_SPI_SUN4I is not set
+# CONFIG_SPI_SUN6I is not set
+# CONFIG_SPI_SYNQUACER is not set
+# CONFIG_SPI_MXIC is not set
+# CONFIG_SPI_TEGRA114 is not set
+# CONFIG_SPI_TEGRA20_SFLASH is not set
+# CONFIG_SPI_TEGRA20_SLINK is not set
+# CONFIG_SPI_THUNDERX is not set
+# CONFIG_SPI_TOPCLIFF_PCH is not set
+# CONFIG_SPI_UNIPHIER is not set
+# CONFIG_SPI_XCOMM is not set
+# CONFIG_SPI_XILINX is not set
+# CONFIG_SPI_XLP is not set
+# CONFIG_SPI_XTENSA_XTFPGA is not set
+# CONFIG_SPI_ZYNQ_QSPI is not set
+# CONFIG_SPI_ZYNQMP_GQSPI is not set
+
+#
+# SPI Protocol Masters
+#
+# CONFIG_SPI_SPIDEV is not set
+# CONFIG_SPI_LOOPBACK_TEST is not set
+# CONFIG_SPI_TLE62X0 is not set
+# CONFIG_SPI_SLAVE is not set
+# CONFIG_SPMI is not set
+# CONFIG_HSI is not set
+# CONFIG_PPS is not set
+
+#
+# PTP clock support
+#
+# CONFIG_PTP_1588_CLOCK is not set
+
+#
+# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks.
+#
+# CONFIG_PTP_1588_CLOCK_PCH is not set
+# end of PTP clock support
+
+# CONFIG_PINCTRL is not set
+# CONFIG_GPIOLIB is not set
+# CONFIG_W1 is not set
+# CONFIG_POWER_AVS is not set
+# CONFIG_POWER_RESET is not set
+CONFIG_POWER_SUPPLY=y
+# CONFIG_POWER_SUPPLY_DEBUG is not set
+CONFIG_POWER_SUPPLY_HWMON=y
+# CONFIG_PDA_POWER is not set
+# CONFIG_TEST_POWER is not set
+# CONFIG_CHARGER_ADP5061 is not set
+# CONFIG_BATTERY_ACT8945A is not set
+# CONFIG_BATTERY_DS2780 is not set
+# CONFIG_BATTERY_DS2781 is not set
+# CONFIG_BATTERY_DS2782 is not set
+# CONFIG_BATTERY_SBS is not set
+# CONFIG_CHARGER_SBS is not set
+# CONFIG_BATTERY_BQ27XXX is not set
+# CONFIG_BATTERY_MAX17040 is not set
+# CONFIG_BATTERY_MAX17042 is not set
+# CONFIG_CHARGER_MAX8903 is not set
+# CONFIG_CHARGER_LP8727 is not set
+# CONFIG_CHARGER_GPIO is not set
+# CONFIG_CHARGER_DETECTOR_MAX14656 is not set
+# CONFIG_CHARGER_BQ2415X is not set
+# CONFIG_CHARGER_BQ24735 is not set
+# CONFIG_CHARGER_BQ25890 is not set
+# CONFIG_CHARGER_SMB347 is not set
+# CONFIG_BATTERY_GAUGE_LTC2941 is not set
+# CONFIG_BATTERY_GOLDFISH is not set
+# CONFIG_CHARGER_RT9455 is not set
+# CONFIG_CHARGER_SC2731 is not set
+CONFIG_HWMON=y
+# CONFIG_HWMON_DEBUG_CHIP is not set
+
+#
+# Native drivers
+#
+# CONFIG_SENSORS_AD7314 is not set
+# CONFIG_SENSORS_AD7414 is not set
+# CONFIG_SENSORS_AD7418 is not set
+# CONFIG_SENSORS_ADM1021 is not set
+# CONFIG_SENSORS_ADM1025 is not set
+# CONFIG_SENSORS_ADM1026 is not set
+# CONFIG_SENSORS_ADM1029 is not set
+# CONFIG_SENSORS_ADM1031 is not set
+# CONFIG_SENSORS_ADM9240 is not set
+# CONFIG_SENSORS_ADT7310 is not set
+# CONFIG_SENSORS_ADT7410 is not set
+# CONFIG_SENSORS_ADT7411 is not set
+# CONFIG_SENSORS_ADT7462 is not set
+# CONFIG_SENSORS_ADT7470 is not set
+# CONFIG_SENSORS_ADT7475 is not set
+# CONFIG_SENSORS_AS370 is not set
+# CONFIG_SENSORS_ASC7621 is not set
+# CONFIG_SENSORS_ASPEED is not set
+# CONFIG_SENSORS_ATXP1 is not set
+# CONFIG_SENSORS_DS620 is not set
+# CONFIG_SENSORS_DS1621 is not set
+# CONFIG_SENSORS_I5K_AMB is not set
+# CONFIG_SENSORS_F71805F is not set
+# CONFIG_SENSORS_F71882FG is not set
+# CONFIG_SENSORS_F75375S is not set
+# CONFIG_SENSORS_GL518SM is not set
+# CONFIG_SENSORS_GL520SM is not set
+# CONFIG_SENSORS_G760A is not set
+# CONFIG_SENSORS_G762 is not set
+# CONFIG_SENSORS_HIH6130 is not set
+# CONFIG_SENSORS_IT87 is not set
+# CONFIG_SENSORS_JC42 is not set
+# CONFIG_SENSORS_POWR1220 is not set
+# CONFIG_SENSORS_LINEAGE is not set
+# CONFIG_SENSORS_LTC2945 is not set
+# CONFIG_SENSORS_LTC2990 is not set
+# CONFIG_SENSORS_LTC4151 is not set
+# CONFIG_SENSORS_LTC4215 is not set
+# CONFIG_SENSORS_LTC4222 is not set
+# CONFIG_SENSORS_LTC4245 is not set
+# CONFIG_SENSORS_LTC4260 is not set
+# CONFIG_SENSORS_LTC4261 is not set
+# CONFIG_SENSORS_MAX1111 is not set
+# CONFIG_SENSORS_MAX16065 is not set
+# CONFIG_SENSORS_MAX1619 is not set
+# CONFIG_SENSORS_MAX1668 is not set
+# CONFIG_SENSORS_MAX197 is not set
+# CONFIG_SENSORS_MAX31722 is not set
+# CONFIG_SENSORS_MAX6621 is not set
+# CONFIG_SENSORS_MAX6639 is not set
+# CONFIG_SENSORS_MAX6642 is not set
+# CONFIG_SENSORS_MAX6650 is not set
+# CONFIG_SENSORS_MAX6697 is not set
+# CONFIG_SENSORS_MAX31790 is not set
+# CONFIG_SENSORS_MCP3021 is not set
+# CONFIG_SENSORS_TC654 is not set
+# CONFIG_SENSORS_ADCXX is not set
+# CONFIG_SENSORS_LM63 is not set
+# CONFIG_SENSORS_LM70 is not set
+# CONFIG_SENSORS_LM73 is not set
+# CONFIG_SENSORS_LM75 is not set
+# CONFIG_SENSORS_LM77 is not set
+# CONFIG_SENSORS_LM78 is not set
+# CONFIG_SENSORS_LM80 is not set
+# CONFIG_SENSORS_LM83 is not set
+# CONFIG_SENSORS_LM85 is not set
+# CONFIG_SENSORS_LM87 is not set
+# CONFIG_SENSORS_LM90 is not set
+# CONFIG_SENSORS_LM92 is not set
+# CONFIG_SENSORS_LM93 is not set
+# CONFIG_SENSORS_LM95234 is not set
+# CONFIG_SENSORS_LM95241 is not set
+# CONFIG_SENSORS_LM95245 is not set
+# CONFIG_SENSORS_PC87360 is not set
+# CONFIG_SENSORS_PC87427 is not set
+# CONFIG_SENSORS_NTC_THERMISTOR is not set
+# CONFIG_SENSORS_NCT6683 is not set
+# CONFIG_SENSORS_NCT6775 is not set
+# CONFIG_SENSORS_NCT7802 is not set
+# CONFIG_SENSORS_NCT7904 is not set
+# CONFIG_SENSORS_NPCM7XX is not set
+# CONFIG_SENSORS_OCC_P8_I2C is not set
+# CONFIG_SENSORS_PCF8591 is not set
+# CONFIG_PMBUS is not set
+# CONFIG_SENSORS_PWM_FAN is not set
+# CONFIG_SENSORS_RASPBERRYPI_HWMON is not set
+# CONFIG_SENSORS_SHT15 is not set
+# CONFIG_SENSORS_SHT21 is not set
+# CONFIG_SENSORS_SHT3x is not set
+# CONFIG_SENSORS_SHTC1 is not set
+# CONFIG_SENSORS_SIS5595 is not set
+# CONFIG_SENSORS_DME1737 is not set
+# CONFIG_SENSORS_EMC1403 is not set
+# CONFIG_SENSORS_EMC2103 is not set
+# CONFIG_SENSORS_EMC6W201 is not set
+# CONFIG_SENSORS_SMSC47M1 is not set
+# CONFIG_SENSORS_SMSC47M192 is not set
+# CONFIG_SENSORS_SMSC47B397 is not set
+# CONFIG_SENSORS_STTS751 is not set
+# CONFIG_SENSORS_SMM665 is not set
+# CONFIG_SENSORS_ADC128D818 is not set
+# CONFIG_SENSORS_ADS7828 is not set
+# CONFIG_SENSORS_ADS7871 is not set
+# CONFIG_SENSORS_AMC6821 is not set
+# CONFIG_SENSORS_INA209 is not set
+# CONFIG_SENSORS_INA2XX is not set
+# CONFIG_SENSORS_INA3221 is not set
+# CONFIG_SENSORS_TC74 is not set
+# CONFIG_SENSORS_THMC50 is not set
+# CONFIG_SENSORS_TMP102 is not set
+# CONFIG_SENSORS_TMP103 is not set
+# CONFIG_SENSORS_TMP108 is not set
+# CONFIG_SENSORS_TMP401 is not set
+# CONFIG_SENSORS_TMP421 is not set
+# CONFIG_SENSORS_VIA686A is not set
+# CONFIG_SENSORS_VT1211 is not set
+# CONFIG_SENSORS_VT8231 is not set
+# CONFIG_SENSORS_W83773G is not set
+# CONFIG_SENSORS_W83781D is not set
+# CONFIG_SENSORS_W83791D is not set
+# CONFIG_SENSORS_W83792D is not set
+# CONFIG_SENSORS_W83793 is not set
+# CONFIG_SENSORS_W83795 is not set
+# CONFIG_SENSORS_W83L785TS is not set
+# CONFIG_SENSORS_W83L786NG is not set
+# CONFIG_SENSORS_W83627HF is not set
+# CONFIG_SENSORS_W83627EHF is not set
+# CONFIG_THERMAL is not set
+# CONFIG_WATCHDOG is not set
+CONFIG_SSB_POSSIBLE=y
+# CONFIG_SSB is not set
+CONFIG_BCMA_POSSIBLE=y
+# CONFIG_BCMA is not set
+
+#
+# Multifunction device drivers
+#
+CONFIG_MFD_CORE=y
+# CONFIG_MFD_ACT8945A is not set
+# CONFIG_MFD_SUN4I_GPADC is not set
+# CONFIG_MFD_AS3711 is not set
+# CONFIG_MFD_AS3722 is not set
+# CONFIG_PMIC_ADP5520 is not set
+# CONFIG_MFD_AAT2870_CORE is not set
+# CONFIG_MFD_AT91_USART is not set
+# CONFIG_MFD_ATMEL_FLEXCOM is not set
+# CONFIG_MFD_ATMEL_HLCDC is not set
+# CONFIG_MFD_BCM590XX is not set
+# CONFIG_MFD_BD9571MWV is not set
+# CONFIG_MFD_AXP20X_I2C is not set
+# CONFIG_MFD_MADERA is not set
+# CONFIG_PMIC_DA903X is not set
+# CONFIG_MFD_DA9052_SPI is not set
+# CONFIG_MFD_DA9052_I2C is not set
+# CONFIG_MFD_DA9055 is not set
+# CONFIG_MFD_DA9062 is not set
+# CONFIG_MFD_DA9063 is not set
+# CONFIG_MFD_DA9150 is not set
+# CONFIG_MFD_DLN2 is not set
+# CONFIG_MFD_EXYNOS_LPASS is not set
+# CONFIG_MFD_MC13XXX_SPI is not set
+# CONFIG_MFD_MC13XXX_I2C is not set
+# CONFIG_MFD_MXS_LRADC is not set
+# CONFIG_MFD_MX25_TSADC is not set
+# CONFIG_MFD_HI6421_PMIC is not set
+# CONFIG_MFD_HI655X_PMIC is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_LPC_ICH is not set
+# CONFIG_LPC_SCH is not set
+# CONFIG_MFD_JANZ_CMODIO is not set
+# CONFIG_MFD_KEMPLD is not set
+# CONFIG_MFD_88PM800 is not set
+# CONFIG_MFD_88PM805 is not set
+# CONFIG_MFD_88PM860X is not set
+# CONFIG_MFD_MAX14577 is not set
+# CONFIG_MFD_MAX77620 is not set
+# CONFIG_MFD_MAX77650 is not set
+# CONFIG_MFD_MAX77686 is not set
+# CONFIG_MFD_MAX77693 is not set
+# CONFIG_MFD_MAX77843 is not set
+# CONFIG_MFD_MAX8907 is not set
+# CONFIG_MFD_MAX8925 is not set
+# CONFIG_MFD_MAX8997 is not set
+# CONFIG_MFD_MAX8998 is not set
+# CONFIG_MFD_MT6397 is not set
+# CONFIG_MFD_MENF21BMC is not set
+# CONFIG_EZX_PCAP is not set
+# CONFIG_MFD_CPCAP is not set
+# CONFIG_MFD_VIPERBOARD is not set
+# CONFIG_MFD_RETU is not set
+# CONFIG_MFD_PCF50633 is not set
+# CONFIG_MFD_PM8XXX is not set
+# CONFIG_MFD_RDC321X is not set
+# CONFIG_MFD_RT5033 is not set
+# CONFIG_MFD_RC5T583 is not set
+# CONFIG_MFD_RK808 is not set
+# CONFIG_MFD_RN5T618 is not set
+# CONFIG_MFD_SEC_CORE is not set
+# CONFIG_MFD_SI476X_CORE is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_MFD_SKY81452 is not set
+# CONFIG_MFD_SMSC is not set
+# CONFIG_MFD_SC27XX_PMIC is not set
+# CONFIG_ABX500_CORE is not set
+# CONFIG_MFD_STMPE is not set
+CONFIG_MFD_SUN6I_PRCM=y
+CONFIG_MFD_SYSCON=y
+# CONFIG_MFD_TI_AM335X_TSCADC is not set
+# CONFIG_MFD_LP3943 is not set
+# CONFIG_MFD_LP8788 is not set
+# CONFIG_MFD_TI_LMU is not set
+# CONFIG_MFD_PALMAS is not set
+# CONFIG_TPS6105X is not set
+# CONFIG_TPS6507X is not set
+# CONFIG_MFD_TPS65086 is not set
+# CONFIG_MFD_TPS65090 is not set
+# CONFIG_MFD_TPS65217 is not set
+# CONFIG_MFD_TI_LP873X is not set
+# CONFIG_MFD_TI_LP87565 is not set
+# CONFIG_MFD_TPS65218 is not set
+# CONFIG_MFD_TPS6586X is not set
+# CONFIG_MFD_TPS65910 is not set
+# CONFIG_MFD_TPS65912_I2C is not set
+# CONFIG_MFD_TPS65912_SPI is not set
+# CONFIG_MFD_TPS80031 is not set
+# CONFIG_TWL4030_CORE is not set
+# CONFIG_TWL6040_CORE is not set
+# CONFIG_MFD_WL1273_CORE is not set
+# CONFIG_MFD_LM3533 is not set
+# CONFIG_MFD_TC3589X is not set
+# CONFIG_MFD_TQMX86 is not set
+# CONFIG_MFD_VX855 is not set
+# CONFIG_MFD_LOCHNAGAR is not set
+# CONFIG_MFD_ARIZONA_I2C is not set
+# CONFIG_MFD_ARIZONA_SPI is not set
+# CONFIG_MFD_WM8400 is not set
+# CONFIG_MFD_WM831X_I2C is not set
+# CONFIG_MFD_WM831X_SPI is not set
+# CONFIG_MFD_WM8350_I2C is not set
+# CONFIG_MFD_WM8994 is not set
+# CONFIG_MFD_STW481X is not set
+# CONFIG_MFD_ROHM_BD718XX is not set
+# CONFIG_MFD_ROHM_BD70528 is not set
+# CONFIG_MFD_STM32_LPTIMER is not set
+# CONFIG_MFD_STM32_TIMERS is not set
+# CONFIG_MFD_STPMIC1 is not set
+# CONFIG_MFD_STMFX is not set
+# end of Multifunction device drivers
+
+# CONFIG_REGULATOR is not set
+# CONFIG_RC_CORE is not set
+# CONFIG_MEDIA_SUPPORT is not set
+
+#
+# Graphics support
+#
+CONFIG_VGA_ARB=y
+CONFIG_VGA_ARB_MAX_GPUS=16
+# CONFIG_IMX_IPUV3_CORE is not set
+CONFIG_DRM=y
+# CONFIG_DRM_DP_AUX_CHARDEV is not set
+# CONFIG_DRM_DEBUG_MM is not set
+# CONFIG_DRM_DEBUG_SELFTEST is not set
+CONFIG_DRM_KMS_HELPER=y
+CONFIG_DRM_KMS_FB_HELPER=y
+CONFIG_DRM_FBDEV_EMULATION=y
+CONFIG_DRM_FBDEV_OVERALLOC=100
+# CONFIG_DRM_FBDEV_LEAK_PHYS_SMEM is not set
+# CONFIG_DRM_LOAD_EDID_FIRMWARE is not set
+# CONFIG_DRM_DP_CEC is not set
+CONFIG_DRM_TTM=y
+
+#
+# I2C encoder or helper chips
+#
+# CONFIG_DRM_I2C_CH7006 is not set
+# CONFIG_DRM_I2C_SIL164 is not set
+# CONFIG_DRM_I2C_NXP_TDA998X is not set
+# CONFIG_DRM_I2C_NXP_TDA9950 is not set
+# end of I2C encoder or helper chips
+
+#
+# ARM devices
+#
+# CONFIG_DRM_KOMEDA is not set
+# end of ARM devices
+
+CONFIG_DRM_RADEON=y
+# CONFIG_DRM_RADEON_USERPTR is not set
+# CONFIG_DRM_AMDGPU is not set
+
+#
+# ACP (Audio CoProcessor) Configuration
+#
+# end of ACP (Audio CoProcessor) Configuration
+
+# CONFIG_DRM_NOUVEAU is not set
+# CONFIG_DRM_VGEM is not set
+# CONFIG_DRM_VKMS is not set
+# CONFIG_DRM_EXYNOS is not set
+# CONFIG_DRM_UDL is not set
+# CONFIG_DRM_AST is not set
+# CONFIG_DRM_MGAG200 is not set
+# CONFIG_DRM_CIRRUS_QEMU is not set
+# CONFIG_DRM_RCAR_DW_HDMI is not set
+# CONFIG_DRM_RCAR_LVDS is not set
+# CONFIG_DRM_QXL is not set
+# CONFIG_DRM_BOCHS is not set
+CONFIG_DRM_VIRTIO_GPU=y
+CONFIG_DRM_PANEL=y
+
+#
+# Display Panels
+#
+# CONFIG_DRM_PANEL_ARM_VERSATILE is not set
+# CONFIG_DRM_PANEL_LVDS is not set
+# CONFIG_DRM_PANEL_SIMPLE is not set
+# CONFIG_DRM_PANEL_ILITEK_IL9322 is not set
+# CONFIG_DRM_PANEL_SAMSUNG_LD9040 is not set
+# CONFIG_DRM_PANEL_LG_LG4573 is not set
+# CONFIG_DRM_PANEL_NOVATEK_NT39016 is not set
+# CONFIG_DRM_PANEL_OLIMEX_LCD_OLINUXINO is not set
+# CONFIG_DRM_PANEL_SAMSUNG_S6E63M0 is not set
+# CONFIG_DRM_PANEL_SAMSUNG_S6E8AA0 is not set
+# CONFIG_DRM_PANEL_SEIKO_43WVF1G is not set
+# CONFIG_DRM_PANEL_SITRONIX_ST7789V is not set
+# CONFIG_DRM_PANEL_TPO_TD028TTEC1 is not set
+# end of Display Panels
+
+CONFIG_DRM_BRIDGE=y
+CONFIG_DRM_PANEL_BRIDGE=y
+
+#
+# Display Interface Bridges
+#
+# CONFIG_DRM_ANALOGIX_ANX78XX is not set
+# CONFIG_DRM_CDNS_DSI is not set
+# CONFIG_DRM_DUMB_VGA_DAC is not set
+# CONFIG_DRM_LVDS_ENCODER is not set
+# CONFIG_DRM_MEGACHIPS_STDPXXXX_GE_B850V3_FW is not set
+# CONFIG_DRM_NXP_PTN3460 is not set
+# CONFIG_DRM_PARADE_PS8622 is not set
+# CONFIG_DRM_SIL_SII8620 is not set
+# CONFIG_DRM_SII902X is not set
+# CONFIG_DRM_SII9234 is not set
+# CONFIG_DRM_THINE_THC63LVD1024 is not set
+# CONFIG_DRM_TOSHIBA_TC358764 is not set
+# CONFIG_DRM_TOSHIBA_TC358767 is not set
+# CONFIG_DRM_TI_TFP410 is not set
+# CONFIG_DRM_TI_SN65DSI86 is not set
+# CONFIG_DRM_I2C_ADV7511 is not set
+# end of Display Interface Bridges
+
+# CONFIG_DRM_V3D is not set
+# CONFIG_DRM_ETNAVIV is not set
+# CONFIG_DRM_ARCPGU is not set
+# CONFIG_DRM_MXSFB is not set
+# CONFIG_DRM_GM12U320 is not set
+# CONFIG_TINYDRM_HX8357D is not set
+# CONFIG_TINYDRM_ILI9225 is not set
+# CONFIG_TINYDRM_ILI9341 is not set
+# CONFIG_TINYDRM_MI0283QT is not set
+# CONFIG_TINYDRM_REPAPER is not set
+# CONFIG_TINYDRM_ST7586 is not set
+# CONFIG_TINYDRM_ST7735R is not set
+# CONFIG_DRM_PL111 is not set
+# CONFIG_DRM_LIMA is not set
+# CONFIG_DRM_PANFROST is not set
+# CONFIG_DRM_ASPEED_GFX is not set
+# CONFIG_DRM_LEGACY is not set
+CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y
+
+#
+# Frame buffer Devices
+#
+CONFIG_FB_CMDLINE=y
+CONFIG_FB_NOTIFY=y
+CONFIG_FB=y
+# CONFIG_FIRMWARE_EDID is not set
+CONFIG_FB_CFB_FILLRECT=y
+CONFIG_FB_CFB_COPYAREA=y
+CONFIG_FB_CFB_IMAGEBLIT=y
+CONFIG_FB_SYS_FILLRECT=y
+CONFIG_FB_SYS_COPYAREA=y
+CONFIG_FB_SYS_IMAGEBLIT=y
+# CONFIG_FB_FOREIGN_ENDIAN is not set
+CONFIG_FB_SYS_FOPS=y
+CONFIG_FB_DEFERRED_IO=y
+# CONFIG_FB_MODE_HELPERS is not set
+# CONFIG_FB_TILEBLITTING is not set
+
+#
+# Frame buffer hardware drivers
+#
+# CONFIG_FB_CIRRUS is not set
+# CONFIG_FB_PM2 is not set
+# CONFIG_FB_CLPS711X is not set
+# CONFIG_FB_IMX is not set
+# CONFIG_FB_CYBER2000 is not set
+# CONFIG_FB_ASILIANT is not set
+# CONFIG_FB_IMSTT is not set
+# CONFIG_FB_GBE is not set
+# CONFIG_FB_PVR2 is not set
+# CONFIG_FB_OPENCORES is not set
+# CONFIG_FB_S1D13XXX is not set
+# CONFIG_FB_ATMEL is not set
+# CONFIG_FB_NVIDIA is not set
+# CONFIG_FB_RIVA is not set
+# CONFIG_FB_I740 is not set
+# CONFIG_FB_MATROX is not set
+# CONFIG_FB_RADEON is not set
+# CONFIG_FB_ATY128 is not set
+# CONFIG_FB_ATY is not set
+# CONFIG_FB_S3 is not set
+# CONFIG_FB_SAVAGE is not set
+# CONFIG_FB_SIS is not set
+# CONFIG_FB_NEOMAGIC is not set
+# CONFIG_FB_KYRO is not set
+# CONFIG_FB_3DFX is not set
+# CONFIG_FB_VOODOO1 is not set
+# CONFIG_FB_VT8623 is not set
+# CONFIG_FB_TRIDENT is not set
+# CONFIG_FB_ARK is not set
+# CONFIG_FB_PM3 is not set
+# CONFIG_FB_CARMINE is not set
+# CONFIG_FB_PXA168 is not set
+# CONFIG_FB_TMIO is not set
+# CONFIG_FB_S3C is not set
+# CONFIG_FB_SMSCUFX is not set
+# CONFIG_FB_UDL is not set
+# CONFIG_FB_IBM_GXT4500 is not set
+# CONFIG_FB_GOLDFISH is not set
+# CONFIG_FB_DA8XX is not set
+# CONFIG_FB_VIRTUAL is not set
+# CONFIG_FB_METRONOME is not set
+# CONFIG_FB_MB862XX is not set
+# CONFIG_FB_BROADSHEET is not set
+# CONFIG_FB_SIMPLE is not set
+# CONFIG_FB_SSD1307 is not set
+# CONFIG_FB_SM712 is not set
+# end of Frame buffer Devices
+
+#
+# Backlight & LCD device support
+#
+# CONFIG_LCD_CLASS_DEVICE is not set
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
+CONFIG_BACKLIGHT_GENERIC=y
+# CONFIG_BACKLIGHT_PM8941_WLED is not set
+# CONFIG_BACKLIGHT_ADP8860 is not set
+# CONFIG_BACKLIGHT_ADP8870 is not set
+# CONFIG_BACKLIGHT_LM3639 is not set
+# CONFIG_BACKLIGHT_GPIO is not set
+# CONFIG_BACKLIGHT_LV5207LP is not set
+# CONFIG_BACKLIGHT_BD6107 is not set
+# CONFIG_BACKLIGHT_ARCXCNN is not set
+# end of Backlight & LCD device support
+
+CONFIG_HDMI=y
+
+#
+# Console display driver support
+#
+CONFIG_VGA_CONSOLE=y
+# CONFIG_VGACON_SOFT_SCROLLBACK is not set
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_DUMMY_CONSOLE_COLUMNS=80
+CONFIG_DUMMY_CONSOLE_ROWS=25
+CONFIG_FRAMEBUFFER_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
+# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
+# CONFIG_FRAMEBUFFER_CONSOLE_DEFERRED_TAKEOVER is not set
+# end of Console display driver support
+
+# CONFIG_LOGO is not set
+# end of Graphics support
+
+# CONFIG_SOUND is not set
+
+#
+# HID support
+#
+CONFIG_HID=y
+# CONFIG_HID_BATTERY_STRENGTH is not set
+# CONFIG_HIDRAW is not set
+# CONFIG_UHID is not set
+CONFIG_HID_GENERIC=y
+
+#
+# Special HID drivers
+#
+# CONFIG_HID_A4TECH is not set
+# CONFIG_HID_ACCUTOUCH is not set
+# CONFIG_HID_ACRUX is not set
+# CONFIG_HID_APPLE is not set
+# CONFIG_HID_APPLEIR is not set
+# CONFIG_HID_AUREAL is not set
+# CONFIG_HID_BELKIN is not set
+# CONFIG_HID_BETOP_FF is not set
+# CONFIG_HID_CHERRY is not set
+# CONFIG_HID_CHICONY is not set
+# CONFIG_HID_COUGAR is not set
+# CONFIG_HID_MACALLY is not set
+# CONFIG_HID_CMEDIA is not set
+# CONFIG_HID_CREATIVE_SB0540 is not set
+# CONFIG_HID_CYPRESS is not set
+# CONFIG_HID_DRAGONRISE is not set
+# CONFIG_HID_EMS_FF is not set
+# CONFIG_HID_ELECOM is not set
+# CONFIG_HID_ELO is not set
+# CONFIG_HID_EZKEY is not set
+# CONFIG_HID_GEMBIRD is not set
+# CONFIG_HID_GFRM is not set
+# CONFIG_HID_HOLTEK is not set
+# CONFIG_HID_KEYTOUCH is not set
+# CONFIG_HID_KYE is not set
+# CONFIG_HID_UCLOGIC is not set
+# CONFIG_HID_WALTOP is not set
+# CONFIG_HID_VIEWSONIC is not set
+# CONFIG_HID_GYRATION is not set
+# CONFIG_HID_ICADE is not set
+# CONFIG_HID_ITE is not set
+# CONFIG_HID_JABRA is not set
+# CONFIG_HID_TWINHAN is not set
+# CONFIG_HID_KENSINGTON is not set
+# CONFIG_HID_LCPOWER is not set
+# CONFIG_HID_LENOVO is not set
+# CONFIG_HID_LOGITECH is not set
+# CONFIG_HID_MAGICMOUSE is not set
+# CONFIG_HID_MALTRON is not set
+# CONFIG_HID_MAYFLASH is not set
+# CONFIG_HID_REDRAGON is not set
+# CONFIG_HID_MICROSOFT is not set
+# CONFIG_HID_MONTEREY is not set
+# CONFIG_HID_MULTITOUCH is not set
+# CONFIG_HID_NTI is not set
+# CONFIG_HID_NTRIG is not set
+# CONFIG_HID_ORTEK is not set
+# CONFIG_HID_PANTHERLORD is not set
+# CONFIG_HID_PENMOUNT is not set
+# CONFIG_HID_PETALYNX is not set
+# CONFIG_HID_PICOLCD is not set
+# CONFIG_HID_PLANTRONICS is not set
+# CONFIG_HID_PRIMAX is not set
+# CONFIG_HID_RETRODE is not set
+# CONFIG_HID_ROCCAT is not set
+# CONFIG_HID_SAITEK is not set
+# CONFIG_HID_SAMSUNG is not set
+# CONFIG_HID_SPEEDLINK is not set
+# CONFIG_HID_STEAM is not set
+# CONFIG_HID_STEELSERIES is not set
+# CONFIG_HID_SUNPLUS is not set
+# CONFIG_HID_RMI is not set
+# CONFIG_HID_GREENASIA is not set
+# CONFIG_HID_SMARTJOYPLUS is not set
+# CONFIG_HID_TIVO is not set
+# CONFIG_HID_TOPSEED is not set
+# CONFIG_HID_THRUSTMASTER is not set
+# CONFIG_HID_UDRAW_PS3 is not set
+# CONFIG_HID_WACOM is not set
+# CONFIG_HID_XINMO is not set
+# CONFIG_HID_ZEROPLUS is not set
+# CONFIG_HID_ZYDACRON is not set
+# CONFIG_HID_SENSOR_HUB is not set
+# CONFIG_HID_ALPS is not set
+# end of Special HID drivers
+
+#
+# USB HID support
+#
+CONFIG_USB_HID=y
+# CONFIG_HID_PID is not set
+# CONFIG_USB_HIDDEV is not set
+# end of USB HID support
+
+#
+# I2C HID support
+#
+# CONFIG_I2C_HID is not set
+# end of I2C HID support
+
+#
+# Intel ISH HID support
+#
+# CONFIG_INTEL_ISH_HID is not set
+# end of Intel ISH HID support
+# end of HID support
+
+CONFIG_USB_OHCI_LITTLE_ENDIAN=y
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_COMMON=y
+# CONFIG_USB_ULPI_BUS is not set
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB=y
+CONFIG_USB_PCI=y
+# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
+
+#
+# Miscellaneous USB options
+#
+CONFIG_USB_DEFAULT_PERSIST=y
+# CONFIG_USB_DYNAMIC_MINORS is not set
+# CONFIG_USB_OTG_WHITELIST is not set
+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
+CONFIG_USB_AUTOSUSPEND_DELAY=2
+# CONFIG_USB_MON is not set
+
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_C67X00_HCD is not set
+CONFIG_USB_XHCI_HCD=y
+# CONFIG_USB_XHCI_DBGCAP is not set
+CONFIG_USB_XHCI_PCI=y
+CONFIG_USB_XHCI_PLATFORM=y
+# CONFIG_USB_XHCI_HISTB is not set
+# CONFIG_USB_XHCI_MTK is not set
+# CONFIG_USB_XHCI_MVEBU is not set
+# CONFIG_USB_XHCI_RCAR is not set
+CONFIG_USB_EHCI_HCD=y
+# CONFIG_USB_EHCI_ROOT_HUB_TT is not set
+CONFIG_USB_EHCI_TT_NEWSCHED=y
+CONFIG_USB_EHCI_PCI=y
+# CONFIG_USB_EHCI_FSL is not set
+# CONFIG_USB_EHCI_HCD_NPCM7XX is not set
+CONFIG_USB_EHCI_HCD_PLATFORM=y
+# CONFIG_USB_OXU210HP_HCD is not set
+# CONFIG_USB_ISP116X_HCD is not set
+# CONFIG_USB_ISP1362_HCD is not set
+# CONFIG_USB_FOTG210_HCD is not set
+# CONFIG_USB_MAX3421_HCD is not set
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_HCD_PCI=y
+CONFIG_USB_OHCI_HCD_PLATFORM=y
+# CONFIG_USB_UHCI_HCD is not set
+# CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
+# CONFIG_USB_HCD_TEST_MODE is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+# CONFIG_USB_WDM is not set
+# CONFIG_USB_TMC is not set
+
+#
+# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
+#
+
+#
+# also be needed; see USB_STORAGE Help for more info
+#
+CONFIG_USB_STORAGE=y
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_REALTEK is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_USBAT is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_SDDR55 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_STORAGE_ALAUDA is not set
+# CONFIG_USB_STORAGE_ONETOUCH is not set
+# CONFIG_USB_STORAGE_KARMA is not set
+# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
+# CONFIG_USB_STORAGE_ENE_UB6250 is not set
+CONFIG_USB_UAS=y
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_MICROTEK is not set
+# CONFIG_USBIP_CORE is not set
+# CONFIG_USB_CDNS3 is not set
+# CONFIG_USB_MTU3 is not set
+# CONFIG_USB_MUSB_HDRC is not set
+# CONFIG_USB_DWC3 is not set
+# CONFIG_USB_DWC2 is not set
+# CONFIG_USB_CHIPIDEA is not set
+# CONFIG_USB_ISP1760 is not set
+
+#
+# USB port drivers
+#
+# CONFIG_USB_SERIAL is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_EMI62 is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_ADUTUX is not set
+# CONFIG_USB_SEVSEG is not set
+# CONFIG_USB_LEGOTOWER is not set
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
+# CONFIG_USB_SISUSBVGA is not set
+# CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
+# CONFIG_USB_TEST is not set
+# CONFIG_USB_EHSET_TEST_FIXTURE is not set
+# CONFIG_USB_ISIGHTFW is not set
+# CONFIG_USB_YUREX is not set
+# CONFIG_USB_EZUSB_FX2 is not set
+# CONFIG_USB_HUB_USB251XB is not set
+# CONFIG_USB_HSIC_USB3503 is not set
+# CONFIG_USB_HSIC_USB4604 is not set
+# CONFIG_USB_LINK_LAYER_TEST is not set
+# CONFIG_USB_CHAOSKEY is not set
+
+#
+# USB Physical Layer drivers
+#
+# CONFIG_NOP_USB_XCEIV is not set
+# CONFIG_USB_GPIO_VBUS is not set
+# CONFIG_USB_ISP1301 is not set
+# end of USB Physical Layer drivers
+
+# CONFIG_USB_GADGET is not set
+# CONFIG_TYPEC is not set
+# CONFIG_USB_ROLE_SWITCH is not set
+CONFIG_MMC=y
+CONFIG_PWRSEQ_EMMC=y
+CONFIG_PWRSEQ_SIMPLE=y
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_BLOCK_MINORS=8
+# CONFIG_SDIO_UART is not set
+# CONFIG_MMC_TEST is not set
+
+#
+# MMC/SD/SDIO Host Controller Drivers
+#
+CONFIG_MMC_DEBUG=y
+# CONFIG_MMC_SDHCI is not set
+# CONFIG_MMC_MESON_MX_SDIO is not set
+# CONFIG_MMC_OMAP_HS is not set
+# CONFIG_MMC_TIFM_SD is not set
+# CONFIG_MMC_GOLDFISH is not set
+CONFIG_MMC_SPI=y
+# CONFIG_MMC_SDHI is not set
+# CONFIG_MMC_UNIPHIER is not set
+# CONFIG_MMC_CB710 is not set
+# CONFIG_MMC_VIA_SDMMC is not set
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_PLTFM=y
+# CONFIG_MMC_DW_BLUEFIELD is not set
+# CONFIG_MMC_DW_EXYNOS is not set
+# CONFIG_MMC_DW_HI3798CV200 is not set
+# CONFIG_MMC_DW_K3 is not set
+# CONFIG_MMC_DW_PCI is not set
+# CONFIG_MMC_SH_MMCIF is not set
+# CONFIG_MMC_VUB300 is not set
+# CONFIG_MMC_USHC is not set
+# CONFIG_MMC_USDHI6ROL0 is not set
+# CONFIG_MMC_CQHCI is not set
+# CONFIG_MMC_TOSHIBA_PCI is not set
+# CONFIG_MMC_BCM2835 is not set
+# CONFIG_MMC_MTK is not set
+# CONFIG_MEMSTICK is not set
+# CONFIG_NEW_LEDS is not set
+# CONFIG_ACCESSIBILITY is not set
+# CONFIG_INFINIBAND is not set
+CONFIG_EDAC_SUPPORT=y
+# CONFIG_EDAC is not set
+# CONFIG_RTC_CLASS is not set
+CONFIG_DMADEVICES=y
+# CONFIG_DMADEVICES_DEBUG is not set
+
+#
+# DMA Devices
+#
+CONFIG_DMA_ENGINE=y
+CONFIG_DMA_VIRTUAL_CHANNELS=y
+CONFIG_DMA_OF=y
+# CONFIG_ALTERA_MSGDMA is not set
+# CONFIG_AXI_DMAC is not set
+# CONFIG_COH901318 is not set
+# CONFIG_DMA_JZ4780 is not set
+# CONFIG_DMA_SA11X0 is not set
+# CONFIG_DMA_SUN6I is not set
+CONFIG_DW_AXI_DMAC=y
+# CONFIG_EP93XX_DMA is not set
+# CONFIG_FSL_EDMA is not set
+# CONFIG_IMG_MDC_DMA is not set
+# CONFIG_INTEL_IDMA64 is not set
+# CONFIG_INTEL_IOP_ADMA is not set
+# CONFIG_K3_DMA is not set
+# CONFIG_MCF_EDMA is not set
+# CONFIG_MMP_PDMA is not set
+# CONFIG_MMP_TDMA is not set
+# CONFIG_MV_XOR is not set
+# CONFIG_MXS_DMA is not set
+# CONFIG_NBPFAXI_DMA is not set
+# CONFIG_PCH_DMA is not set
+# CONFIG_STM32_DMA is not set
+# CONFIG_STM32_DMAMUX is not set
+# CONFIG_STM32_MDMA is not set
+# CONFIG_SPRD_DMA is not set
+# CONFIG_S3C24XX_DMAC is not set
+# CONFIG_TEGRA210_ADMA is not set
+# CONFIG_TIMB_DMA is not set
+# CONFIG_UNIPHIER_MDMAC is not set
+# CONFIG_XGENE_DMA is not set
+# CONFIG_ZX_DMA is not set
+# CONFIG_MTK_HSDMA is not set
+# CONFIG_MTK_CQDMA is not set
+# CONFIG_QCOM_HIDMA_MGMT is not set
+# CONFIG_QCOM_HIDMA is not set
+CONFIG_DW_DMAC_CORE=y
+# CONFIG_DW_DMAC is not set
+# CONFIG_DW_DMAC_PCI is not set
+# CONFIG_DW_EDMA is not set
+# CONFIG_DW_EDMA_PCIE is not set
+CONFIG_HSU_DMA=y
+CONFIG_RENESAS_DMA=y
+CONFIG_SH_DMAE_BASE=y
+# CONFIG_SH_DMAE is not set
+# CONFIG_RCAR_DMAC is not set
+# CONFIG_RENESAS_USB_DMAC is not set
+CONFIG_TI_EDMA=y
+CONFIG_DMA_OMAP=y
+CONFIG_TI_DMA_CROSSBAR=y
+
+#
+# DMA Clients
+#
+# CONFIG_ASYNC_TX_DMA is not set
+CONFIG_DMATEST=y
+CONFIG_DMA_ENGINE_RAID=y
+
+#
+# DMABUF options
+#
+CONFIG_SYNC_FILE=y
+# CONFIG_SW_SYNC is not set
+# CONFIG_UDMABUF is not set
+# CONFIG_DMABUF_SELFTESTS is not set
+# end of DMABUF options
+
+# CONFIG_AUXDISPLAY is not set
+# CONFIG_CHARLCD is not set
+# CONFIG_UIO is not set
+# CONFIG_VIRT_DRIVERS is not set
+CONFIG_VIRTIO=y
+CONFIG_VIRTIO_MENU=y
+CONFIG_VIRTIO_PCI=y
+CONFIG_VIRTIO_PCI_LEGACY=y
+CONFIG_VIRTIO_BALLOON=y
+CONFIG_VIRTIO_INPUT=y
+CONFIG_VIRTIO_MMIO=y
+# CONFIG_VIRTIO_MMIO_CMDLINE_DEVICES is not set
+
+#
+# Microsoft Hyper-V guest support
+#
+# end of Microsoft Hyper-V guest support
+
+# CONFIG_GREYBUS is not set
+# CONFIG_STAGING is not set
+# CONFIG_MFD_CROS_EC is not set
+# CONFIG_CHROME_PLATFORMS is not set
+# CONFIG_MELLANOX_PLATFORM is not set
+# CONFIG_OLPC_XO175 is not set
+CONFIG_CLKDEV_LOOKUP=y
+CONFIG_HAVE_CLK_PREPARE=y
+CONFIG_COMMON_CLK=y
+
+#
+# Common Clock Framework
+#
+# CONFIG_COMMON_CLK_VERSATILE is not set
+# CONFIG_CLK_HSDK is not set
+# CONFIG_COMMON_CLK_MAX77686 is not set
+# CONFIG_COMMON_CLK_MAX9485 is not set
+# CONFIG_COMMON_CLK_HI655X is not set
+# CONFIG_COMMON_CLK_SCMI is not set
+# CONFIG_COMMON_CLK_SCPI is not set
+# CONFIG_COMMON_CLK_SI5341 is not set
+# CONFIG_COMMON_CLK_SI5351 is not set
+# CONFIG_COMMON_CLK_SI514 is not set
+# CONFIG_COMMON_CLK_SI544 is not set
+# CONFIG_COMMON_CLK_SI570 is not set
+# CONFIG_COMMON_CLK_CDCE706 is not set
+# CONFIG_COMMON_CLK_CDCE925 is not set
+# CONFIG_COMMON_CLK_CS2000_CP is not set
+# CONFIG_COMMON_CLK_GEMINI is not set
+# CONFIG_COMMON_CLK_ASPEED is not set
+# CONFIG_COMMON_CLK_S2MPS11 is not set
+# CONFIG_COMMON_CLK_AXI_CLKGEN is not set
+# CONFIG_CLK_QORIQ is not set
+# CONFIG_COMMON_CLK_XGENE is not set
+# CONFIG_COMMON_CLK_OXNAS is not set
+# CONFIG_COMMON_CLK_VC5 is not set
+# CONFIG_COMMON_CLK_FIXED_MMIO is not set
+# CONFIG_CLK_ACTIONS is not set
+CONFIG_CLK_ANALOGBITS_WRPLL_CLN28HPC=y
+# CONFIG_CLK_BCM2835 is not set
+# CONFIG_CLK_BCM_63XX is not set
+# CONFIG_CLK_BCM_63XX_GATE is not set
+# CONFIG_CLK_BCM_KONA is not set
+# CONFIG_CLK_BCM_CYGNUS is not set
+# CONFIG_CLK_BCM_HR2 is not set
+# CONFIG_CLK_BCM_NSP is not set
+# CONFIG_CLK_BCM_NS2 is not set
+# CONFIG_CLK_BCM_SR is not set
+# CONFIG_CLK_RASPBERRYPI is not set
+# CONFIG_COMMON_CLK_HI3516CV300 is not set
+# CONFIG_COMMON_CLK_HI3519 is not set
+# CONFIG_COMMON_CLK_HI3660 is not set
+# CONFIG_COMMON_CLK_HI3670 is not set
+# CONFIG_COMMON_CLK_HI3798CV200 is not set
+# CONFIG_COMMON_CLK_HI6220 is not set
+# CONFIG_RESET_HISI is not set
+# CONFIG_COMMON_CLK_BOSTON is not set
+# CONFIG_COMMON_CLK_KEYSTONE is not set
+
+#
+# Clock driver for MediaTek SoC
+#
+# CONFIG_COMMON_CLK_MT2701 is not set
+# CONFIG_COMMON_CLK_MT2712 is not set
+# CONFIG_COMMON_CLK_MT6779 is not set
+# CONFIG_COMMON_CLK_MT6797 is not set
+# CONFIG_COMMON_CLK_MT7622 is not set
+# CONFIG_COMMON_CLK_MT7629 is not set
+# CONFIG_COMMON_CLK_MT8135 is not set
+# CONFIG_COMMON_CLK_MT8173 is not set
+# CONFIG_COMMON_CLK_MT8183 is not set
+# CONFIG_COMMON_CLK_MT8516 is not set
+# end of Clock driver for MediaTek SoC
+
+# CONFIG_COMMON_CLK_QCOM is not set
+# CONFIG_CLK_RENESAS is not set
+# CONFIG_COMMON_CLK_SAMSUNG is not set
+# CONFIG_S3C2410_COMMON_CLK is not set
+# CONFIG_S3C2412_COMMON_CLK is not set
+# CONFIG_S3C2443_COMMON_CLK is not set
+CONFIG_CLK_SIFIVE=y
+CONFIG_CLK_SIFIVE_FU540_PRCI=y
+# CONFIG_SPRD_COMMON_CLK is not set
+CONFIG_CLK_SUNXI=y
+CONFIG_CLK_SUNXI_CLOCKS=y
+CONFIG_CLK_SUNXI_PRCM_SUN6I=y
+CONFIG_CLK_SUNXI_PRCM_SUN8I=y
+CONFIG_CLK_SUNXI_PRCM_SUN9I=y
+# CONFIG_SUNXI_CCU is not set
+# CONFIG_COMMON_CLK_TI_ADPLL is not set
+# CONFIG_CLK_UNIPHIER is not set
+# end of Common Clock Framework
+
+# CONFIG_HWSPINLOCK is not set
+
+#
+# Clock Source drivers
+#
+CONFIG_TIMER_OF=y
+CONFIG_TIMER_PROBE=y
+# CONFIG_BCM2835_TIMER is not set
+# CONFIG_BCM_KONA_TIMER is not set
+# CONFIG_DAVINCI_TIMER is not set
+# CONFIG_DIGICOLOR_TIMER is not set
+# CONFIG_DW_APB_TIMER is not set
+# CONFIG_FTTMR010_TIMER is not set
+# CONFIG_IXP4XX_TIMER is not set
+# CONFIG_MESON6_TIMER is not set
+# CONFIG_OWL_TIMER is not set
+# CONFIG_RDA_TIMER is not set
+# CONFIG_SUN4I_TIMER is not set
+# CONFIG_SUN5I_HSTIMER is not set
+# CONFIG_TEGRA_TIMER is not set
+# CONFIG_VT8500_TIMER is not set
+# CONFIG_NPCM7XX_TIMER is not set
+# CONFIG_CADENCE_TTC_TIMER is not set
+# CONFIG_ASM9260_TIMER is not set
+# CONFIG_CLKSRC_DBX500_PRCMU is not set
+# CONFIG_CLPS711X_TIMER is not set
+# CONFIG_ATLAS7_TIMER is not set
+# CONFIG_MXS_TIMER is not set
+# CONFIG_PRIMA2_TIMER is not set
+# CONFIG_NSPIRE_TIMER is not set
+# CONFIG_INTEGRATOR_AP_TIMER is not set
+# CONFIG_CLKSRC_PISTACHIO is not set
+# CONFIG_CLKSRC_TI_32K is not set
+# CONFIG_CLKSRC_MPS2 is not set
+# CONFIG_ARC_TIMERS is not set
+# CONFIG_ARM_TIMER_SP804 is not set
+# CONFIG_ARMV7M_SYSTICK is not set
+# CONFIG_ATMEL_PIT is not set
+# CONFIG_ATMEL_ST is not set
+# CONFIG_CLKSRC_SAMSUNG_PWM is not set
+# CONFIG_FSL_FTM_TIMER is not set
+# CONFIG_OXNAS_RPS_TIMER is not set
+# CONFIG_MTK_TIMER is not set
+# CONFIG_SPRD_TIMER is not set
+# CONFIG_CLKSRC_JCORE_PIT is not set
+# CONFIG_SH_TIMER_CMT is not set
+# CONFIG_SH_TIMER_MTU2 is not set
+# CONFIG_RENESAS_OSTM is not set
+# CONFIG_SH_TIMER_TMU is not set
+# CONFIG_EM_TIMER_STI is not set
+# CONFIG_CLKSRC_VERSATILE is not set
+# CONFIG_CLKSRC_PXA is not set
+# CONFIG_H8300_TMR8 is not set
+# CONFIG_H8300_TMR16 is not set
+# CONFIG_H8300_TPU is not set
+# CONFIG_TIMER_IMX_SYS_CTR is not set
+# CONFIG_CLKSRC_ST_LPC is not set
+# CONFIG_ATCPIT100_TIMER is not set
+CONFIG_RISCV_TIMER=y
+# CONFIG_INGENIC_TIMER is not set
+# end of Clock Source drivers
+
+# CONFIG_MAILBOX is not set
+CONFIG_IOMMU_SUPPORT=y
+
+#
+# Generic IOMMU Pagetable Support
+#
+# CONFIG_IOMMU_IO_PGTABLE_LPAE is not set
+# CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set
+# end of Generic IOMMU Pagetable Support
+
+# CONFIG_IOMMU_DEBUGFS is not set
+# CONFIG_QCOM_IOMMU is not set
+
+#
+# Remoteproc drivers
+#
+# CONFIG_REMOTEPROC is not set
+# end of Remoteproc drivers
+
+#
+# Rpmsg drivers
+#
+CONFIG_RPMSG=y
+CONFIG_RPMSG_CHAR=y
+CONFIG_RPMSG_VIRTIO=y
+# end of Rpmsg drivers
+
+# CONFIG_SOUNDWIRE is not set
+
+#
+# SOC (System On Chip) specific Drivers
+#
+
+#
+# Amlogic SoC drivers
+#
+# CONFIG_MESON_CANVAS is not set
+# CONFIG_MESON_CLK_MEASURE is not set
+# CONFIG_MESON_GX_SOCINFO is not set
+# CONFIG_MESON_MX_SOCINFO is not set
+# end of Amlogic SoC drivers
+
+#
+# Aspeed SoC drivers
+#
+CONFIG_SOC_ASPEED=y
+# CONFIG_ASPEED_LPC_CTRL is not set
+# CONFIG_ASPEED_LPC_SNOOP is not set
+# CONFIG_ASPEED_P2A_CTRL is not set
+# end of Aspeed SoC drivers
+
+# CONFIG_AT91_SOC_ID is not set
+
+#
+# Broadcom SoC drivers
+#
+# CONFIG_BCM2835_POWER is not set
+# CONFIG_SOC_BRCMSTB is not set
+# end of Broadcom SoC drivers
+
+#
+# NXP/Freescale QorIQ SoC drivers
+#
+CONFIG_DPAA2_CONSOLE=y
+# end of NXP/Freescale QorIQ SoC drivers
+
+#
+# i.MX SoC drivers
+#
+# end of i.MX SoC drivers
+
+#
+# IXP4xx SoC drivers
+#
+# CONFIG_IXP4XX_QMGR is not set
+# CONFIG_IXP4XX_NPE is not set
+# end of IXP4xx SoC drivers
+
+#
+# MediaTek SoC drivers
+#
+# CONFIG_MTK_CMDQ is not set
+# CONFIG_MTK_INFRACFG is not set
+# CONFIG_MTK_PMIC_WRAP is not set
+# CONFIG_MTK_SCPSYS is not set
+# end of MediaTek SoC drivers
+
+#
+# Qualcomm SoC drivers
+#
+# CONFIG_QCOM_COMMAND_DB is not set
+# CONFIG_QCOM_GENI_SE is not set
+# CONFIG_QCOM_GSBI is not set
+# CONFIG_QCOM_LLCC is not set
+# CONFIG_QCOM_RPMH is not set
+# CONFIG_QCOM_SMD_RPM is not set
+# CONFIG_QCOM_WCNSS_CTRL is not set
+# CONFIG_QCOM_APR is not set
+# end of Qualcomm SoC drivers
+
+# CONFIG_SOC_RENESAS is not set
+CONFIG_ROCKCHIP_GRF=y
+# CONFIG_SOC_SAMSUNG is not set
+# CONFIG_SOC_TI is not set
+# CONFIG_UX500_SOC_ID is not set
+
+#
+# Xilinx SoC drivers
+#
+# CONFIG_XILINX_VCU is not set
+# end of Xilinx SoC drivers
+
+# CONFIG_SOC_ZTE is not set
+# end of SOC (System On Chip) specific Drivers
+
+# CONFIG_PM_DEVFREQ is not set
+# CONFIG_EXTCON is not set
+# CONFIG_MEMORY is not set
+# CONFIG_IIO is not set
+# CONFIG_NTB is not set
+# CONFIG_VME_BUS is not set
+# CONFIG_PWM is not set
+
+#
+# IRQ chip support
+#
+CONFIG_IRQCHIP=y
+# CONFIG_AL_FIC is not set
+# CONFIG_JCORE_AIC is not set
+# CONFIG_RENESAS_INTC_IRQPIN is not set
+# CONFIG_RENESAS_IRQC is not set
+# CONFIG_RENESAS_RZA1_IRQC is not set
+# CONFIG_TS4800_IRQ is not set
+# CONFIG_INGENIC_TCU_IRQ is not set
+# CONFIG_RENESAS_H8S_INTC is not set
+# CONFIG_IRQ_UNIPHIER_AIDET is not set
+# CONFIG_IMX_IRQSTEER is not set
+CONFIG_SIFIVE_PLIC=y
+# end of IRQ chip support
+
+# CONFIG_IPACK_BUS is not set
+CONFIG_RESET_CONTROLLER=y
+# CONFIG_RESET_ATH79 is not set
+# CONFIG_RESET_AXS10X is not set
+# CONFIG_RESET_BERLIN is not set
+# CONFIG_RESET_BRCMSTB is not set
+# CONFIG_RESET_HSDK is not set
+# CONFIG_RESET_IMX7 is not set
+# CONFIG_RESET_LANTIQ is not set
+# CONFIG_RESET_LPC18XX is not set
+# CONFIG_RESET_MESON is not set
+# CONFIG_RESET_MESON_AUDIO_ARB is not set
+# CONFIG_RESET_PISTACHIO is not set
+# CONFIG_RESET_QCOM_AOSS is not set
+# CONFIG_RESET_QCOM_PDC is not set
+# CONFIG_RESET_SCMI is not set
+# CONFIG_RESET_SIMPLE is not set
+# CONFIG_RESET_STM32MP157 is not set
+# CONFIG_RESET_SOCFPGA is not set
+# CONFIG_RESET_SUNXI is not set
+# CONFIG_RESET_TI_SYSCON is not set
+# CONFIG_RESET_UNIPHIER is not set
+# CONFIG_RESET_UNIPHIER_GLUE is not set
+# CONFIG_RESET_ZYNQ is not set
+# CONFIG_COMMON_RESET_HI3660 is not set
+# CONFIG_COMMON_RESET_HI6220 is not set
+
+#
+# PHY Subsystem
+#
+CONFIG_GENERIC_PHY=y
+# CONFIG_PHY_LPC18XX_USB_OTG is not set
+# CONFIG_PHY_XGENE is not set
+# CONFIG_PHY_SUN6I_MIPI_DPHY is not set
+# CONFIG_PHY_SUN9I_USB is not set
+# CONFIG_PHY_MESON8B_USB2 is not set
+# CONFIG_PHY_MESON_GXL_USB2 is not set
+# CONFIG_PHY_MESON_GXL_USB3 is not set
+# CONFIG_PHY_MESON_G12A_USB2 is not set
+# CONFIG_PHY_MESON_G12A_USB3_PCIE is not set
+# CONFIG_PHY_CYGNUS_PCIE is not set
+# CONFIG_PHY_BCM_SR_USB is not set
+# CONFIG_BCM_KONA_USB2_PHY is not set
+# CONFIG_PHY_BCM_NS_USB2 is not set
+# CONFIG_PHY_BCM_NS_USB3 is not set
+# CONFIG_PHY_NS2_USB_DRD is not set
+# CONFIG_PHY_BRCM_SATA is not set
+# CONFIG_PHY_BCM_SR_PCIE is not set
+# CONFIG_PHY_CADENCE_DP is not set
+# CONFIG_PHY_CADENCE_DPHY is not set
+# CONFIG_PHY_CADENCE_SIERRA is not set
+# CONFIG_PHY_FSL_IMX8MQ_USB is not set
+# CONFIG_PHY_MIXEL_MIPI_DPHY is not set
+# CONFIG_PHY_HI6220_USB is not set
+# CONFIG_PHY_HI3660_USB is not set
+# CONFIG_PHY_HISTB_COMBPHY is not set
+# CONFIG_PHY_HISI_INNO_USB2 is not set
+# CONFIG_PHY_LANTIQ_VRX200_PCIE is not set
+# CONFIG_PHY_LANTIQ_RCU_USB2 is not set
+CONFIG_ARMADA375_USBCLUSTER_PHY=y
+CONFIG_PHY_MVEBU_A3700_UTMI=y
+# CONFIG_PHY_MVEBU_A38X_COMPHY is not set
+# CONFIG_PHY_PXA_28NM_HSIC is not set
+# CONFIG_PHY_PXA_28NM_USB2 is not set
+# CONFIG_PHY_OCELOT_SERDES is not set
+CONFIG_PHY_ATH79_USB=y
+# CONFIG_PHY_QCOM_PCIE2 is not set
+# CONFIG_PHY_QCOM_QMP is not set
+# CONFIG_PHY_QCOM_QUSB2 is not set
+# CONFIG_PHY_RALINK_USB is not set
+# CONFIG_PHY_RCAR_GEN3_USB3 is not set
+# CONFIG_PHY_ROCKCHIP_INNO_HDMI is not set
+# CONFIG_PHY_ROCKCHIP_PCIE is not set
+# CONFIG_PHY_ROCKCHIP_TYPEC is not set
+# CONFIG_PHY_EXYNOS_DP_VIDEO is not set
+# CONFIG_PHY_EXYNOS_MIPI_VIDEO is not set
+# CONFIG_PHY_EXYNOS_PCIE is not set
+# CONFIG_PHY_UNIPHIER_USB2 is not set
+# CONFIG_PHY_UNIPHIER_USB3 is not set
+# CONFIG_PHY_UNIPHIER_PCIE is not set
+# CONFIG_PHY_ST_SPEAR1310_MIPHY is not set
+# CONFIG_PHY_ST_SPEAR1340_MIPHY is not set
+# CONFIG_PHY_STIH407_USB is not set
+# CONFIG_PHY_STM32_USBPHYC is not set
+# CONFIG_PHY_TEGRA194_P2U is not set
+# CONFIG_PHY_AM654_SERDES is not set
+# CONFIG_OMAP_CONTROL_PHY is not set
+# CONFIG_TI_PIPE3 is not set
+CONFIG_PHY_TI_GMII_SEL=m
+# end of PHY Subsystem
+
+# CONFIG_POWERCAP is not set
+# CONFIG_MCB is not set
+
+#
+# Performance monitor support
+#
+CONFIG_THEAD_XT_V1_PMU=y
+# end of Performance monitor support
+
+CONFIG_RAS=y
+# CONFIG_THUNDERBOLT is not set
+
+#
+# Android
+#
+# CONFIG_ANDROID is not set
+# end of Android
+
+# CONFIG_LIBNVDIMM is not set
+# CONFIG_DAX is not set
+# CONFIG_NVMEM is not set
+
+#
+# HW tracing support
+#
+# CONFIG_STM is not set
+# CONFIG_INTEL_TH is not set
+# end of HW tracing support
+
+# CONFIG_FPGA is not set
+# CONFIG_FSI is not set
+# CONFIG_TEE is not set
+# CONFIG_SIOX is not set
+# CONFIG_SLIMBUS is not set
+# CONFIG_INTERCONNECT is not set
+# CONFIG_COUNTER is not set
+# end of Device Drivers
+
+#
+# File systems
+#
+# CONFIG_VALIDATE_FS_PARSER is not set
+CONFIG_FS_IOMAP=y
+# CONFIG_EXT2_FS is not set
+# CONFIG_EXT3_FS is not set
+CONFIG_EXT4_FS=y
+CONFIG_EXT4_USE_FOR_EXT2=y
+CONFIG_EXT4_FS_POSIX_ACL=y
+# CONFIG_EXT4_FS_SECURITY is not set
+# CONFIG_EXT4_DEBUG is not set
+CONFIG_JBD2=y
+# CONFIG_JBD2_DEBUG is not set
+CONFIG_FS_MBCACHE=y
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_BTRFS_FS is not set
+# CONFIG_NILFS2_FS is not set
+# CONFIG_F2FS_FS is not set
+# CONFIG_FS_DAX is not set
+CONFIG_FS_POSIX_ACL=y
+CONFIG_EXPORTFS=y
+# CONFIG_EXPORTFS_BLOCK_OPS is not set
+CONFIG_FILE_LOCKING=y
+CONFIG_MANDATORY_FILE_LOCKING=y
+# CONFIG_FS_ENCRYPTION is not set
+# CONFIG_FS_VERITY is not set
+CONFIG_FSNOTIFY=y
+CONFIG_DNOTIFY=y
+CONFIG_INOTIFY_USER=y
+# CONFIG_FANOTIFY is not set
+# CONFIG_QUOTA is not set
+CONFIG_AUTOFS4_FS=y
+CONFIG_AUTOFS_FS=y
+CONFIG_FUSE_FS=y
+# CONFIG_CUSE is not set
+# CONFIG_VIRTIO_FS is not set
+# CONFIG_OVERLAY_FS is not set
+
+#
+# Caches
+#
+# CONFIG_FSCACHE is not set
+# end of Caches
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+# end of CD-ROM/DVD Filesystems
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+# CONFIG_FAT_DEFAULT_UTF8 is not set
+# CONFIG_NTFS_FS is not set
+# end of DOS/FAT/NT Filesystems
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+# CONFIG_PROC_KCORE is not set
+CONFIG_PROC_SYSCTL=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_PROC_CHILDREN=y
+CONFIG_KERNFS=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+CONFIG_TMPFS_POSIX_ACL=y
+CONFIG_TMPFS_XATTR=y
+# CONFIG_HUGETLBFS is not set
+CONFIG_MEMFD_CREATE=y
+CONFIG_ARCH_HAS_GIGANTIC_PAGE=y
+# CONFIG_CONFIGFS_FS is not set
+# end of Pseudo filesystems
+
+CONFIG_MISC_FILESYSTEMS=y
+# CONFIG_ORANGEFS_FS is not set
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_ECRYPT_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_SQUASHFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_QNX6FS_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_PSTORE is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+# CONFIG_EROFS_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V2=y
+CONFIG_NFS_V3=y
+# CONFIG_NFS_V3_ACL is not set
+CONFIG_NFS_V4=y
+# CONFIG_NFS_SWAP is not set
+CONFIG_NFS_V4_1=y
+CONFIG_NFS_V4_2=y
+CONFIG_PNFS_FILE_LAYOUT=y
+CONFIG_PNFS_FLEXFILE_LAYOUT=m
+CONFIG_NFS_V4_1_IMPLEMENTATION_ID_DOMAIN="kernel.org"
+# CONFIG_NFS_V4_1_MIGRATION is not set
+CONFIG_ROOT_NFS=y
+# CONFIG_NFS_USE_LEGACY_DNS is not set
+CONFIG_NFS_USE_KERNEL_DNS=y
+# CONFIG_NFSD is not set
+CONFIG_GRACE_PERIOD=y
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+CONFIG_SUNRPC_GSS=y
+CONFIG_SUNRPC_BACKCHANNEL=y
+# CONFIG_SUNRPC_DEBUG is not set
+# CONFIG_CEPH_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+CONFIG_9P_FS=y
+CONFIG_9P_FS_POSIX_ACL=y
+CONFIG_9P_FS_SECURITY=y
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8859-1"
+# CONFIG_NLS_CODEPAGE_437 is not set
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ASCII is not set
+# CONFIG_NLS_ISO8859_1 is not set
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+# CONFIG_NLS_MAC_ROMAN is not set
+# CONFIG_NLS_MAC_CELTIC is not set
+# CONFIG_NLS_MAC_CENTEURO is not set
+# CONFIG_NLS_MAC_CROATIAN is not set
+# CONFIG_NLS_MAC_CYRILLIC is not set
+# CONFIG_NLS_MAC_GAELIC is not set
+# CONFIG_NLS_MAC_GREEK is not set
+# CONFIG_NLS_MAC_ICELAND is not set
+# CONFIG_NLS_MAC_INUIT is not set
+# CONFIG_NLS_MAC_ROMANIAN is not set
+# CONFIG_NLS_MAC_TURKISH is not set
+# CONFIG_NLS_UTF8 is not set
+# CONFIG_UNICODE is not set
+# end of File systems
+
+#
+# Security options
+#
+CONFIG_KEYS=y
+# CONFIG_KEYS_REQUEST_CACHE is not set
+# CONFIG_PERSISTENT_KEYRINGS is not set
+# CONFIG_BIG_KEYS is not set
+# CONFIG_ENCRYPTED_KEYS is not set
+# CONFIG_KEY_DH_OPERATIONS is not set
+# CONFIG_SECURITY_DMESG_RESTRICT is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITYFS is not set
+CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y
+# CONFIG_HARDENED_USERCOPY is not set
+# CONFIG_STATIC_USERMODEHELPER is not set
+CONFIG_DEFAULT_SECURITY_DAC=y
+CONFIG_LSM="lockdown,yama,loadpin,safesetid,integrity"
+
+#
+# Kernel hardening options
+#
+
+#
+# Memory initialization
+#
+CONFIG_INIT_STACK_NONE=y
+# CONFIG_INIT_ON_ALLOC_DEFAULT_ON is not set
+# CONFIG_INIT_ON_FREE_DEFAULT_ON is not set
+# end of Memory initialization
+# end of Kernel hardening options
+# end of Security options
+
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_ALGAPI2=y
+CONFIG_CRYPTO_AEAD=y
+CONFIG_CRYPTO_AEAD2=y
+CONFIG_CRYPTO_BLKCIPHER=y
+CONFIG_CRYPTO_BLKCIPHER2=y
+CONFIG_CRYPTO_HASH=y
+CONFIG_CRYPTO_HASH2=y
+CONFIG_CRYPTO_RNG2=y
+# CONFIG_CRYPTO_MANAGER is not set
+# CONFIG_CRYPTO_USER is not set
+# CONFIG_CRYPTO_NULL is not set
+CONFIG_CRYPTO_NULL2=y
+# CONFIG_CRYPTO_PCRYPT is not set
+# CONFIG_CRYPTO_CRYPTD is not set
+# CONFIG_CRYPTO_AUTHENC is not set
+# CONFIG_CRYPTO_TEST is not set
+CONFIG_CRYPTO_ENGINE=y
+
+#
+# Public-key cryptography
+#
+# CONFIG_CRYPTO_RSA is not set
+# CONFIG_CRYPTO_DH is not set
+# CONFIG_CRYPTO_ECDH is not set
+# CONFIG_CRYPTO_ECRDSA is not set
+
+#
+# Authenticated Encryption with Associated Data
+#
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_CHACHA20POLY1305 is not set
+# CONFIG_CRYPTO_AEGIS128 is not set
+# CONFIG_CRYPTO_SEQIV is not set
+# CONFIG_CRYPTO_ECHAINIV is not set
+
+#
+# Block modes
+#
+# CONFIG_CRYPTO_CBC is not set
+# CONFIG_CRYPTO_CFB is not set
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_CTS is not set
+# CONFIG_CRYPTO_ECB is not set
+# CONFIG_CRYPTO_LRW is not set
+# CONFIG_CRYPTO_OFB is not set
+# CONFIG_CRYPTO_PCBC is not set
+# CONFIG_CRYPTO_XTS is not set
+# CONFIG_CRYPTO_KEYWRAP is not set
+# CONFIG_CRYPTO_ADIANTUM is not set
+# CONFIG_CRYPTO_ESSIV is not set
+
+#
+# Hash modes
+#
+# CONFIG_CRYPTO_CMAC is not set
+# CONFIG_CRYPTO_HMAC is not set
+# CONFIG_CRYPTO_XCBC is not set
+# CONFIG_CRYPTO_VMAC is not set
+
+#
+# Digest
+#
+CONFIG_CRYPTO_CRC32C=y
+# CONFIG_CRYPTO_CRC32 is not set
+# CONFIG_CRYPTO_XXHASH is not set
+# CONFIG_CRYPTO_CRCT10DIF is not set
+# CONFIG_CRYPTO_GHASH is not set
+# CONFIG_CRYPTO_POLY1305 is not set
+# CONFIG_CRYPTO_MD4 is not set
+# CONFIG_CRYPTO_MD5 is not set
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_RMD128 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+# CONFIG_CRYPTO_RMD256 is not set
+# CONFIG_CRYPTO_RMD320 is not set
+# CONFIG_CRYPTO_SHA1 is not set
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_SHA3 is not set
+# CONFIG_CRYPTO_SM3 is not set
+# CONFIG_CRYPTO_STREEBOG is not set
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_WP512 is not set
+
+#
+# Ciphers
+#
+# CONFIG_CRYPTO_AES is not set
+# CONFIG_CRYPTO_AES_TI is not set
+# CONFIG_CRYPTO_ANUBIS is not set
+# CONFIG_CRYPTO_ARC4 is not set
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+# CONFIG_CRYPTO_DES is not set
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_SALSA20 is not set
+# CONFIG_CRYPTO_CHACHA20 is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_SM4 is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+
+#
+# Compression
+#
+# CONFIG_CRYPTO_DEFLATE is not set
+# CONFIG_CRYPTO_LZO is not set
+# CONFIG_CRYPTO_842 is not set
+# CONFIG_CRYPTO_LZ4 is not set
+# CONFIG_CRYPTO_LZ4HC is not set
+# CONFIG_CRYPTO_ZSTD is not set
+
+#
+# Random Number Generation
+#
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
+# CONFIG_CRYPTO_DRBG_MENU is not set
+# CONFIG_CRYPTO_JITTERENTROPY is not set
+CONFIG_CRYPTO_USER_API=y
+CONFIG_CRYPTO_USER_API_HASH=y
+# CONFIG_CRYPTO_USER_API_SKCIPHER is not set
+# CONFIG_CRYPTO_USER_API_RNG is not set
+# CONFIG_CRYPTO_USER_API_AEAD is not set
+CONFIG_CRYPTO_HW=y
+# CONFIG_CRYPTO_DEV_PICOXCELL is not set
+# CONFIG_CRYPTO_DEV_EXYNOS_RNG is not set
+# CONFIG_CRYPTO_DEV_S5P is not set
+# CONFIG_CRYPTO_DEV_ATMEL_AUTHENC is not set
+# CONFIG_CRYPTO_DEV_ATMEL_AES is not set
+# CONFIG_CRYPTO_DEV_ATMEL_TDES is not set
+# CONFIG_CRYPTO_DEV_ATMEL_SHA is not set
+# CONFIG_CRYPTO_DEV_ATMEL_ECC is not set
+# CONFIG_CRYPTO_DEV_ATMEL_SHA204A is not set
+# CONFIG_CAVIUM_CPT is not set
+# CONFIG_CRYPTO_DEV_NITROX_CNN55XX is not set
+# CONFIG_CRYPTO_DEV_CAVIUM_ZIP is not set
+# CONFIG_CRYPTO_DEV_QCE is not set
+# CONFIG_CRYPTO_DEV_QCOM_RNG is not set
+# CONFIG_CRYPTO_DEV_IMGTEC_HASH is not set
+# CONFIG_CRYPTO_DEV_MEDIATEK is not set
+CONFIG_CRYPTO_DEV_VIRTIO=y
+# CONFIG_CRYPTO_DEV_SAFEXCEL is not set
+# CONFIG_CRYPTO_DEV_CCREE is not set
+# CONFIG_CRYPTO_DEV_HISI_SEC is not set
+# CONFIG_ASYMMETRIC_KEY_TYPE is not set
+
+#
+# Certificates for signature checking
+#
+# CONFIG_SYSTEM_BLACKLIST_KEYRING is not set
+# end of Certificates for signature checking
+
+#
+# Library routines
+#
+# CONFIG_PACKING is not set
+CONFIG_BITREVERSE=y
+CONFIG_GENERIC_STRNCPY_FROM_USER=y
+CONFIG_GENERIC_STRNLEN_USER=y
+CONFIG_GENERIC_NET_UTILS=y
+# CONFIG_CORDIC is not set
+CONFIG_RATIONAL=y
+CONFIG_GENERIC_PCI_IOMAP=y
+# CONFIG_CRC_CCITT is not set
+CONFIG_CRC16=y
+# CONFIG_CRC_T10DIF is not set
+CONFIG_CRC_ITU_T=y
+CONFIG_CRC32=y
+# CONFIG_CRC32_SELFTEST is not set
+CONFIG_CRC32_SLICEBY8=y
+# CONFIG_CRC32_SLICEBY4 is not set
+# CONFIG_CRC32_SARWATE is not set
+# CONFIG_CRC32_BIT is not set
+# CONFIG_CRC64 is not set
+# CONFIG_CRC4 is not set
+CONFIG_CRC7=y
+# CONFIG_LIBCRC32C is not set
+# CONFIG_CRC8 is not set
+# CONFIG_RANDOM32_SELFTEST is not set
+CONFIG_ZLIB_INFLATE=y
+CONFIG_LZO_DECOMPRESS=y
+CONFIG_LZ4_DECOMPRESS=y
+CONFIG_XZ_DEC=y
+CONFIG_XZ_DEC_X86=y
+CONFIG_XZ_DEC_POWERPC=y
+CONFIG_XZ_DEC_IA64=y
+CONFIG_XZ_DEC_ARM=y
+CONFIG_XZ_DEC_ARMTHUMB=y
+CONFIG_XZ_DEC_SPARC=y
+CONFIG_XZ_DEC_BCJ=y
+# CONFIG_XZ_DEC_TEST is not set
+CONFIG_DECOMPRESS_GZIP=y
+CONFIG_DECOMPRESS_BZIP2=y
+CONFIG_DECOMPRESS_LZMA=y
+CONFIG_DECOMPRESS_XZ=y
+CONFIG_DECOMPRESS_LZO=y
+CONFIG_DECOMPRESS_LZ4=y
+CONFIG_GENERIC_ALLOCATOR=y
+CONFIG_INTERVAL_TREE=y
+CONFIG_ASSOCIATIVE_ARRAY=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT_MAP=y
+CONFIG_HAS_DMA=y
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_ARCH_DMA_ADDR_T_64BIT=y
+CONFIG_ARCH_HAS_DMA_WRITE_COMBINE=y
+CONFIG_DMA_DECLARE_COHERENT=y
+CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE=y
+CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU=y
+CONFIG_ARCH_HAS_DMA_PREP_COHERENT=y
+CONFIG_SWIOTLB=y
+CONFIG_DMA_REMAP=y
+CONFIG_DMA_DIRECT_REMAP=y
+# CONFIG_DMA_API_DEBUG is not set
+CONFIG_CPU_RMAP=y
+CONFIG_DQL=y
+CONFIG_GLOB=y
+# CONFIG_GLOB_SELFTEST is not set
+CONFIG_NLATTR=y
+# CONFIG_IRQ_POLL is not set
+CONFIG_LIBFDT=y
+CONFIG_OID_REGISTRY=y
+CONFIG_FONT_SUPPORT=y
+# CONFIG_FONTS is not set
+CONFIG_FONT_8x8=y
+CONFIG_FONT_8x16=y
+CONFIG_SG_POOL=y
+CONFIG_SBITMAP=y
+# CONFIG_PARMAN is not set
+# CONFIG_OBJAGG is not set
+# CONFIG_STRING_SELFTEST is not set
+# end of Library routines
+
+#
+# Kernel hacking
+#
+
+#
+# printk and dmesg options
+#
+CONFIG_PRINTK_TIME=y
+# CONFIG_PRINTK_CALLER is not set
+CONFIG_CONSOLE_LOGLEVEL_DEFAULT=7
+CONFIG_CONSOLE_LOGLEVEL_QUIET=4
+CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4
+# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_DYNAMIC_DEBUG is not set
+# end of printk and dmesg options
+
+#
+# Compile-time checks and compiler options
+#
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=2048
+# CONFIG_STRIP_ASM_SYMS is not set
+# CONFIG_READABLE_ASM is not set
+CONFIG_DEBUG_FS=y
+# CONFIG_HEADERS_INSTALL is not set
+CONFIG_OPTIMIZE_INLINING=y
+# CONFIG_DEBUG_SECTION_MISMATCH is not set
+CONFIG_SECTION_MISMATCH_WARN_ONLY=y
+CONFIG_ARCH_WANT_FRAME_POINTERS=y
+CONFIG_FRAME_POINTER=y
+# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
+# end of Compile-time checks and compiler options
+
+# CONFIG_MAGIC_SYSRQ is not set
+CONFIG_DEBUG_KERNEL=y
+CONFIG_DEBUG_MISC=y
+
+#
+# Memory Debugging
+#
+# CONFIG_PAGE_EXTENSION is not set
+# CONFIG_DEBUG_PAGEALLOC is not set
+# CONFIG_PAGE_OWNER is not set
+# CONFIG_PAGE_POISONING is not set
+# CONFIG_DEBUG_OBJECTS is not set
+# CONFIG_SLUB_DEBUG_ON is not set
+# CONFIG_SLUB_STATS is not set
+# CONFIG_DEBUG_STACK_USAGE is not set
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
+# CONFIG_DEBUG_PER_CPU_MAPS is not set
+CONFIG_CC_HAS_KASAN_GENERIC=y
+CONFIG_KASAN_STACK=1
+# end of Memory Debugging
+
+CONFIG_CC_HAS_SANCOV_TRACE_PC=y
+# CONFIG_DEBUG_SHIRQ is not set
+
+#
+# Debug Lockups and Hangs
+#
+# CONFIG_SOFTLOCKUP_DETECTOR is not set
+CONFIG_DETECT_HUNG_TASK=y
+CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=60
+# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
+CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
+# CONFIG_WQ_WATCHDOG is not set
+# end of Debug Lockups and Hangs
+
+# CONFIG_PANIC_ON_OOPS is not set
+CONFIG_PANIC_ON_OOPS_VALUE=0
+CONFIG_PANIC_TIMEOUT=0
+CONFIG_SCHED_DEBUG=y
+# CONFIG_SCHEDSTATS is not set
+# CONFIG_SCHED_STACK_END_CHECK is not set
+# CONFIG_DEBUG_TIMEKEEPING is not set
+
+#
+# Lock Debugging (spinlocks, mutexes, etc...)
+#
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_RWSEMS is not set
+CONFIG_DEBUG_ATOMIC_SLEEP=y
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_LOCK_TORTURE_TEST is not set
+# CONFIG_WW_MUTEX_SELFTEST is not set
+# end of Lock Debugging (spinlocks, mutexes, etc...)
+
+# CONFIG_STACKTRACE is not set
+# CONFIG_WARN_ALL_UNSEEDED_RANDOM is not set
+# CONFIG_DEBUG_KOBJECT is not set
+CONFIG_DEBUG_BUGVERBOSE=y
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_PLIST is not set
+# CONFIG_DEBUG_SG is not set
+# CONFIG_DEBUG_NOTIFIERS is not set
+# CONFIG_DEBUG_CREDENTIALS is not set
+
+#
+# RCU Debugging
+#
+# CONFIG_RCU_PERF_TEST is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+CONFIG_RCU_CPU_STALL_TIMEOUT=21
+# CONFIG_RCU_TRACE is not set
+# CONFIG_RCU_EQS_DEBUG is not set
+# end of RCU Debugging
+
+# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set
+# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
+# CONFIG_NOTIFIER_ERROR_INJECTION is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_LATENCYTOP is not set
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
+CONFIG_HAVE_DYNAMIC_FTRACE=y
+CONFIG_HAVE_DYNAMIC_FTRACE_WITH_REGS=y
+CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
+CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
+CONFIG_TRACING_SUPPORT=y
+CONFIG_FTRACE=y
+# CONFIG_FUNCTION_TRACER is not set
+# CONFIG_PREEMPTIRQ_EVENTS is not set
+# CONFIG_IRQSOFF_TRACER is not set
+# CONFIG_SCHED_TRACER is not set
+# CONFIG_HWLAT_TRACER is not set
+# CONFIG_ENABLE_DEFAULT_TRACERS is not set
+# CONFIG_FTRACE_SYSCALLS is not set
+# CONFIG_TRACER_SNAPSHOT is not set
+CONFIG_BRANCH_PROFILE_NONE=y
+# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set
+# CONFIG_PROFILE_ALL_BRANCHES is not set
+# CONFIG_STACK_TRACER is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_TRACEPOINT_BENCHMARK is not set
+# CONFIG_PREEMPTIRQ_DELAY_TEST is not set
+CONFIG_RUNTIME_TESTING_MENU=y
+# CONFIG_LKDTM is not set
+# CONFIG_TEST_LIST_SORT is not set
+# CONFIG_TEST_SORT is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_RBTREE_TEST is not set
+# CONFIG_REED_SOLOMON_TEST is not set
+# CONFIG_INTERVAL_TREE_TEST is not set
+# CONFIG_PERCPU_TEST is not set
+# CONFIG_ATOMIC64_SELFTEST is not set
+# CONFIG_TEST_HEXDUMP is not set
+# CONFIG_TEST_STRING_HELPERS is not set
+# CONFIG_TEST_STRSCPY is not set
+# CONFIG_TEST_KSTRTOX is not set
+# CONFIG_TEST_PRINTF is not set
+# CONFIG_TEST_BITMAP is not set
+# CONFIG_TEST_BITFIELD is not set
+# CONFIG_TEST_UUID is not set
+# CONFIG_TEST_XARRAY is not set
+# CONFIG_TEST_OVERFLOW is not set
+# CONFIG_TEST_RHASHTABLE is not set
+# CONFIG_TEST_HASH is not set
+# CONFIG_TEST_IDA is not set
+# CONFIG_TEST_LKM is not set
+# CONFIG_TEST_VMALLOC is not set
+# CONFIG_TEST_USER_COPY is not set
+# CONFIG_TEST_BPF is not set
+# CONFIG_TEST_BLACKHOLE_DEV is not set
+# CONFIG_FIND_BIT_BENCHMARK is not set
+# CONFIG_TEST_FIRMWARE is not set
+# CONFIG_TEST_SYSCTL is not set
+# CONFIG_TEST_UDELAY is not set
+# CONFIG_TEST_STATIC_KEYS is not set
+# CONFIG_TEST_KMOD is not set
+# CONFIG_TEST_MEMCAT_P is not set
+# CONFIG_TEST_STACKINIT is not set
+# CONFIG_TEST_MEMINIT is not set
+# CONFIG_MEMTEST is not set
+# CONFIG_BUG_ON_DATA_CORRUPTION is not set
+# CONFIG_SAMPLES is not set
+# CONFIG_UBSAN is not set
+CONFIG_UBSAN_ALIGNMENT=y
+# end of Kernel hacking
+
+# CONFIG_WARN_MISSING_DOCUMENTS is not set

+ 3811 - 0
recipes-kernel/linux/files/xuantie-c910/qemu-c910_defconfig

@@ -0,0 +1,3811 @@
+#
+# Automatically generated file; DO NOT EDIT.
+# Linux/riscv 5.4.36 Kernel Configuration
+#
+
+#
+# Compiler: riscv64-unknown-linux-gnu-gcc (C-SKY RISCV Tools V1.8.4 B20200702) 8.1.0
+#
+CONFIG_CC_IS_GCC=y
+CONFIG_GCC_VERSION=80100
+CONFIG_CLANG_VERSION=0
+CONFIG_CC_CAN_LINK=y
+CONFIG_CC_HAS_ASM_GOTO=y
+CONFIG_CC_HAS_WARN_MAYBE_UNINITIALIZED=y
+CONFIG_IRQ_WORK=y
+CONFIG_THREAD_INFO_IN_TASK=y
+
+#
+# General setup
+#
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_COMPILE_TEST=y
+CONFIG_LOCALVERSION=""
+CONFIG_BUILD_SALT=""
+CONFIG_DEFAULT_HOSTNAME="(none)"
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_POSIX_MQUEUE_SYSCTL=y
+CONFIG_CROSS_MEMORY_ATTACH=y
+# CONFIG_USELIB is not set
+# CONFIG_AUDIT is not set
+CONFIG_HAVE_ARCH_AUDITSYSCALL=y
+
+#
+# IRQ subsystem
+#
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_IRQ_DOMAIN=y
+CONFIG_IRQ_DOMAIN_HIERARCHY=y
+CONFIG_GENERIC_MSI_IRQ=y
+CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
+CONFIG_SPARSE_IRQ=y
+# CONFIG_GENERIC_IRQ_DEBUGFS is not set
+# end of IRQ subsystem
+
+CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+
+#
+# Timers subsystem
+#
+CONFIG_TICK_ONESHOT=y
+CONFIG_NO_HZ_COMMON=y
+# CONFIG_HZ_PERIODIC is not set
+CONFIG_NO_HZ_IDLE=y
+# CONFIG_NO_HZ is not set
+CONFIG_HIGH_RES_TIMERS=y
+# end of Timers subsystem
+
+CONFIG_PREEMPT_NONE=y
+# CONFIG_PREEMPT_VOLUNTARY is not set
+# CONFIG_PREEMPT is not set
+CONFIG_PREEMPT_COUNT=y
+
+#
+# CPU/Task time and stats accounting
+#
+CONFIG_TICK_CPU_ACCOUNTING=y
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_PSI is not set
+# end of CPU/Task time and stats accounting
+
+CONFIG_CPU_ISOLATION=y
+
+#
+# RCU Subsystem
+#
+CONFIG_TREE_RCU=y
+# CONFIG_RCU_EXPERT is not set
+CONFIG_SRCU=y
+CONFIG_TREE_SRCU=y
+CONFIG_RCU_STALL_COMMON=y
+CONFIG_RCU_NEED_SEGCBLIST=y
+# end of RCU Subsystem
+
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+# CONFIG_IKHEADERS is not set
+CONFIG_LOG_BUF_SHIFT=17
+CONFIG_LOG_CPU_MAX_BUF_SHIFT=12
+CONFIG_PRINTK_SAFE_LOG_BUF_SHIFT=13
+CONFIG_GENERIC_SCHED_CLOCK=y
+
+#
+# Scheduler features
+#
+# end of Scheduler features
+
+CONFIG_ARCH_SUPPORTS_INT128=y
+CONFIG_CGROUPS=y
+# CONFIG_MEMCG is not set
+# CONFIG_BLK_CGROUP is not set
+CONFIG_CGROUP_SCHED=y
+CONFIG_FAIR_GROUP_SCHED=y
+CONFIG_CFS_BANDWIDTH=y
+# CONFIG_RT_GROUP_SCHED is not set
+# CONFIG_CGROUP_PIDS is not set
+# CONFIG_CGROUP_RDMA is not set
+# CONFIG_CGROUP_FREEZER is not set
+# CONFIG_CPUSETS is not set
+# CONFIG_CGROUP_DEVICE is not set
+# CONFIG_CGROUP_CPUACCT is not set
+# CONFIG_CGROUP_PERF is not set
+CONFIG_CGROUP_BPF=y
+# CONFIG_CGROUP_DEBUG is not set
+CONFIG_SOCK_CGROUP_DATA=y
+CONFIG_NAMESPACES=y
+CONFIG_UTS_NS=y
+CONFIG_IPC_NS=y
+CONFIG_USER_NS=y
+CONFIG_PID_NS=y
+CONFIG_NET_NS=y
+CONFIG_CHECKPOINT_RESTORE=y
+# CONFIG_SCHED_AUTOGROUP is not set
+# CONFIG_SYSFS_DEPRECATED is not set
+# CONFIG_RELAY is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_RD_GZIP=y
+CONFIG_RD_BZIP2=y
+CONFIG_RD_LZMA=y
+CONFIG_RD_XZ=y
+CONFIG_RD_LZO=y
+CONFIG_RD_LZ4=y
+CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_SYSCTL=y
+CONFIG_SYSCTL_EXCEPTION_TRACE=y
+CONFIG_BPF=y
+CONFIG_EXPERT=y
+CONFIG_MULTIUSER=y
+# CONFIG_SGETMASK_SYSCALL is not set
+CONFIG_SYSFS_SYSCALL=y
+# CONFIG_SYSCTL_SYSCALL is not set
+CONFIG_FHANDLE=y
+CONFIG_POSIX_TIMERS=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_FUTEX_PI=y
+CONFIG_HAVE_FUTEX_CMPXCHG=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_AIO=y
+CONFIG_IO_URING=y
+CONFIG_ADVISE_SYSCALLS=y
+CONFIG_MEMBARRIER=y
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_ALL is not set
+CONFIG_KALLSYMS_BASE_RELATIVE=y
+CONFIG_BPF_SYSCALL=y
+# CONFIG_USERFAULTFD is not set
+# CONFIG_EMBEDDED is not set
+CONFIG_HAVE_PERF_EVENTS=y
+# CONFIG_PC104 is not set
+
+#
+# Kernel Performance Events And Counters
+#
+CONFIG_PERF_EVENTS=y
+# CONFIG_DEBUG_PERF_USE_VMALLOC is not set
+# end of Kernel Performance Events And Counters
+
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLUB_DEBUG=y
+CONFIG_COMPAT_BRK=y
+# CONFIG_SLAB is not set
+CONFIG_SLUB=y
+# CONFIG_SLOB is not set
+CONFIG_SLAB_MERGE_DEFAULT=y
+# CONFIG_SLAB_FREELIST_RANDOM is not set
+# CONFIG_SLAB_FREELIST_HARDENED is not set
+# CONFIG_SHUFFLE_PAGE_ALLOCATOR is not set
+CONFIG_SLUB_CPU_PARTIAL=y
+# CONFIG_PROFILING is not set
+# end of General setup
+
+CONFIG_64BIT=y
+CONFIG_RISCV=y
+CONFIG_ARCH_MMAP_RND_BITS_MIN=18
+CONFIG_ARCH_MMAP_RND_BITS_MAX=24
+CONFIG_MMU=y
+CONFIG_ZONE_DMA32=y
+CONFIG_VA_BITS=39
+CONFIG_PA_BITS=56
+CONFIG_PAGE_OFFSET=0xffffffe000000000
+CONFIG_ARCH_FLATMEM_ENABLE=y
+CONFIG_ARCH_SPARSEMEM_ENABLE=y
+CONFIG_ARCH_SELECT_MEMORY_MODEL=y
+CONFIG_ARCH_WANT_GENERAL_HUGETLB=y
+CONFIG_SYS_SUPPORTS_HUGETLBFS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_GENERIC_BUG=y
+CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_CSUM=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_FIX_EARLYCON_MEM=y
+CONFIG_PGTABLE_LEVELS=3
+
+#
+# SoC selection
+#
+CONFIG_SOC_SIFIVE=y
+# end of SoC selection
+
+#
+# Platform type
+#
+# CONFIG_ARCH_RV32I is not set
+CONFIG_ARCH_RV64I=y
+# CONFIG_CMODEL_MEDLOW is not set
+CONFIG_CMODEL_MEDANY=y
+CONFIG_MODULE_SECTIONS=y
+# CONFIG_MAXPHYSMEM_2GB is not set
+CONFIG_MAXPHYSMEM_128GB=y
+CONFIG_SMP=y
+CONFIG_NR_CPUS=8
+CONFIG_TUNE_GENERIC=y
+CONFIG_RISCV_ISA_C=y
+
+#
+# supported PMU type
+#
+CONFIG_RISCV_BASE_PMU=y
+# end of supported PMU type
+
+CONFIG_FPU=y
+CONFIG_VECTOR=y
+# end of Platform type
+
+#
+# Kernel features
+#
+# CONFIG_HZ_12 is not set
+# CONFIG_HZ_100 is not set
+CONFIG_HZ_250=y
+# CONFIG_HZ_300 is not set
+# CONFIG_HZ_1000 is not set
+CONFIG_HZ=250
+CONFIG_SCHED_HRTICK=y
+# CONFIG_KEXEC is not set
+# CONFIG_CRASH_DUMP is not set
+# end of Kernel features
+
+#
+# Boot options
+#
+CONFIG_CMDLINE=""
+# end of Boot options
+
+#
+# Power management options
+#
+# CONFIG_PM is not set
+# end of Power management options
+
+#
+# General architecture-dependent options
+#
+CONFIG_HAVE_ARCH_TRACEHOOK=y
+CONFIG_HAVE_DMA_CONTIGUOUS=y
+CONFIG_GENERIC_SMP_IDLE_THREAD=y
+CONFIG_HAVE_ASM_MODVERSIONS=y
+CONFIG_HAVE_CLK=y
+CONFIG_HAVE_PERF_REGS=y
+CONFIG_HAVE_PERF_USER_STACK_DUMP=y
+CONFIG_CC_HAS_STACKPROTECTOR_NONE=y
+CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y
+CONFIG_ARCH_WANT_HUGE_PMD_SHARE=y
+CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
+CONFIG_MODULES_USE_ELF_RELA=y
+CONFIG_ARCH_HAS_ELF_RANDOMIZE=y
+CONFIG_HAVE_ARCH_MMAP_RND_BITS=y
+CONFIG_ARCH_MMAP_RND_BITS=18
+CONFIG_ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT=y
+CONFIG_HAVE_COPY_THREAD_TLS=y
+CONFIG_CLONE_BACKWARDS=y
+CONFIG_64BIT_TIME=y
+# CONFIG_REFCOUNT_FULL is not set
+# CONFIG_LOCK_EVENT_COUNTS is not set
+
+#
+# GCOV-based kernel profiling
+#
+# CONFIG_GCOV_KERNEL is not set
+# end of GCOV-based kernel profiling
+
+CONFIG_PLUGIN_HOSTCC=""
+# end of General architecture-dependent options
+
+CONFIG_RT_MUTEXES=y
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+# CONFIG_MODULE_SIG is not set
+# CONFIG_MODULE_COMPRESS is not set
+# CONFIG_MODULE_ALLOW_MISSING_NAMESPACE_IMPORTS is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_TRIM_UNUSED_KSYMS is not set
+CONFIG_MODULES_TREE_LOOKUP=y
+CONFIG_BLOCK=y
+CONFIG_BLK_SCSI_REQUEST=y
+CONFIG_BLK_DEV_BSG=y
+# CONFIG_BLK_DEV_BSGLIB is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
+# CONFIG_BLK_DEV_ZONED is not set
+# CONFIG_BLK_CMDLINE_PARSER is not set
+# CONFIG_BLK_WBT is not set
+CONFIG_BLK_DEBUG_FS=y
+# CONFIG_BLK_SED_OPAL is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+CONFIG_EFI_PARTITION=y
+# end of Partition Types
+
+CONFIG_BLK_MQ_PCI=y
+CONFIG_BLK_MQ_VIRTIO=y
+
+#
+# IO Schedulers
+#
+CONFIG_MQ_IOSCHED_DEADLINE=y
+CONFIG_MQ_IOSCHED_KYBER=y
+# CONFIG_IOSCHED_BFQ is not set
+# end of IO Schedulers
+
+CONFIG_INLINE_SPIN_UNLOCK_IRQ=y
+CONFIG_INLINE_READ_UNLOCK=y
+CONFIG_INLINE_READ_UNLOCK_IRQ=y
+CONFIG_INLINE_WRITE_UNLOCK=y
+CONFIG_INLINE_WRITE_UNLOCK_IRQ=y
+CONFIG_ARCH_HAS_MMIOWB=y
+CONFIG_MMIOWB=y
+
+#
+# Executable file formats
+#
+CONFIG_BINFMT_ELF=y
+CONFIG_ELFCORE=y
+CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y
+CONFIG_BINFMT_SCRIPT=y
+CONFIG_ARCH_HAS_BINFMT_FLAT=y
+# CONFIG_BINFMT_FLAT is not set
+# CONFIG_BINFMT_MISC is not set
+CONFIG_COREDUMP=y
+# end of Executable file formats
+
+#
+# Memory Management options
+#
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
+CONFIG_HAVE_MEMBLOCK_NODE_MAP=y
+CONFIG_SPLIT_PTLOCK_CPUS=4
+CONFIG_MEMORY_BALLOON=y
+CONFIG_BALLOON_COMPACTION=y
+CONFIG_COMPACTION=y
+CONFIG_MIGRATION=y
+CONFIG_PHYS_ADDR_T_64BIT=y
+# CONFIG_KSM is not set
+CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
+# CONFIG_CLEANCACHE is not set
+# CONFIG_FRONTSWAP is not set
+# CONFIG_CMA is not set
+# CONFIG_ZPOOL is not set
+# CONFIG_ZBUD is not set
+# CONFIG_ZSMALLOC is not set
+# CONFIG_IDLE_PAGE_TRACKING is not set
+# CONFIG_PERCPU_STATS is not set
+# CONFIG_GUP_BENCHMARK is not set
+CONFIG_ARCH_HAS_PTE_SPECIAL=y
+# end of Memory Management options
+
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_DIAG is not set
+CONFIG_UNIX=y
+CONFIG_UNIX_SCM=y
+# CONFIG_UNIX_DIAG is not set
+# CONFIG_TLS is not set
+# CONFIG_XFRM_USER is not set
+# CONFIG_NET_KEY is not set
+# CONFIG_XDP_SOCKETS is not set
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_ADVANCED_ROUTER=y
+# CONFIG_IP_FIB_TRIE_STATS is not set
+# CONFIG_IP_MULTIPLE_TABLES is not set
+# CONFIG_IP_ROUTE_MULTIPATH is not set
+# CONFIG_IP_ROUTE_VERBOSE is not set
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_IP_PNP_RARP=y
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE_DEMUX is not set
+CONFIG_NET_IP_TUNNEL=y
+# CONFIG_IP_MROUTE is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_NET_IPVTI is not set
+# CONFIG_NET_FOU is not set
+# CONFIG_NET_FOU_IP_TUNNELS is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+CONFIG_INET_TUNNEL=y
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+# CONFIG_INET_UDP_DIAG is not set
+# CONFIG_INET_RAW_DIAG is not set
+# CONFIG_INET_DIAG_DESTROY is not set
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+CONFIG_IPV6=y
+# CONFIG_IPV6_ROUTER_PREF is not set
+# CONFIG_IPV6_OPTIMISTIC_DAD is not set
+# CONFIG_INET6_AH is not set
+# CONFIG_INET6_ESP is not set
+# CONFIG_INET6_IPCOMP is not set
+# CONFIG_IPV6_MIP6 is not set
+# CONFIG_IPV6_VTI is not set
+CONFIG_IPV6_SIT=y
+# CONFIG_IPV6_SIT_6RD is not set
+CONFIG_IPV6_NDISC_NODETYPE=y
+# CONFIG_IPV6_TUNNEL is not set
+# CONFIG_IPV6_MULTIPLE_TABLES is not set
+# CONFIG_IPV6_MROUTE is not set
+# CONFIG_IPV6_SEG6_LWTUNNEL is not set
+# CONFIG_IPV6_SEG6_HMAC is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETWORK_PHY_TIMESTAMPING is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_BPFILTER is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_RDS is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_L2TP is not set
+# CONFIG_BRIDGE is not set
+CONFIG_HAVE_NET_DSA=y
+# CONFIG_NET_DSA is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_PHONET is not set
+# CONFIG_6LOWPAN is not set
+# CONFIG_IEEE802154 is not set
+# CONFIG_NET_SCHED is not set
+# CONFIG_DCB is not set
+CONFIG_DNS_RESOLVER=y
+# CONFIG_BATMAN_ADV is not set
+# CONFIG_OPENVSWITCH is not set
+# CONFIG_VSOCKETS is not set
+CONFIG_NETLINK_DIAG=y
+# CONFIG_MPLS is not set
+# CONFIG_NET_NSH is not set
+# CONFIG_HSR is not set
+# CONFIG_NET_SWITCHDEV is not set
+# CONFIG_NET_L3_MASTER_DEV is not set
+# CONFIG_QRTR is not set
+# CONFIG_NET_NCSI is not set
+CONFIG_RPS=y
+CONFIG_RFS_ACCEL=y
+CONFIG_XPS=y
+# CONFIG_CGROUP_NET_PRIO is not set
+# CONFIG_CGROUP_NET_CLASSID is not set
+CONFIG_NET_RX_BUSY_POLL=y
+CONFIG_BQL=y
+# CONFIG_BPF_JIT is not set
+# CONFIG_BPF_STREAM_PARSER is not set
+CONFIG_NET_FLOW_LIMIT=y
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# end of Network testing
+# end of Networking options
+
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+# CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+# CONFIG_AF_KCM is not set
+CONFIG_WIRELESS=y
+# CONFIG_CFG80211 is not set
+
+#
+# CFG80211 needs to be enabled for MAC80211
+#
+CONFIG_MAC80211_STA_HASH_MAX_SIZE=0
+# CONFIG_WIMAX is not set
+# CONFIG_RFKILL is not set
+CONFIG_NET_9P=y
+CONFIG_NET_9P_VIRTIO=y
+CONFIG_NET_9P_DEBUG=y
+# CONFIG_CAIF is not set
+# CONFIG_CEPH_LIB is not set
+# CONFIG_NFC is not set
+# CONFIG_PSAMPLE is not set
+# CONFIG_NET_IFE is not set
+# CONFIG_LWTUNNEL is not set
+CONFIG_DST_CACHE=y
+CONFIG_GRO_CELLS=y
+CONFIG_PAGE_POOL=y
+CONFIG_FAILOVER=y
+CONFIG_HAVE_EBPF_JIT=y
+
+#
+# Device Drivers
+#
+CONFIG_HAVE_PCI=y
+CONFIG_PCI=y
+CONFIG_PCI_DOMAINS=y
+CONFIG_PCI_DOMAINS_GENERIC=y
+CONFIG_PCIEPORTBUS=y
+CONFIG_PCIEAER=y
+# CONFIG_PCIEAER_INJECT is not set
+# CONFIG_PCIE_ECRC is not set
+CONFIG_PCIEASPM=y
+# CONFIG_PCIEASPM_DEBUG is not set
+CONFIG_PCIEASPM_DEFAULT=y
+# CONFIG_PCIEASPM_POWERSAVE is not set
+# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set
+# CONFIG_PCIEASPM_PERFORMANCE is not set
+# CONFIG_PCIE_DPC is not set
+# CONFIG_PCIE_PTM is not set
+# CONFIG_PCIE_BW is not set
+CONFIG_PCI_MSI=y
+CONFIG_PCI_MSI_IRQ_DOMAIN=y
+CONFIG_PCI_QUIRKS=y
+CONFIG_PCI_DEBUG=y
+# CONFIG_PCI_STUB is not set
+CONFIG_PCI_ECAM=y
+# CONFIG_PCI_IOV is not set
+# CONFIG_PCI_PRI is not set
+# CONFIG_PCI_PASID is not set
+# CONFIG_HOTPLUG_PCI is not set
+
+#
+# PCI controller drivers
+#
+# CONFIG_PCI_AARDVARK is not set
+
+#
+# Cadence PCIe controllers support
+#
+# CONFIG_PCIE_CADENCE_HOST is not set
+# end of Cadence PCIe controllers support
+
+# CONFIG_PCIE_XILINX_NWL is not set
+# CONFIG_PCI_FTPCI100 is not set
+# CONFIG_PCI_TEGRA is not set
+# CONFIG_PCIE_RCAR is not set
+CONFIG_PCI_HOST_COMMON=y
+CONFIG_PCI_HOST_GENERIC=y
+CONFIG_PCIE_XILINX=y
+# CONFIG_PCI_XGENE is not set
+# CONFIG_PCI_V3_SEMI is not set
+# CONFIG_PCIE_ALTERA is not set
+# CONFIG_PCI_HOST_THUNDER_PEM is not set
+# CONFIG_PCI_HOST_THUNDER_ECAM is not set
+# CONFIG_PCIE_ROCKCHIP_HOST is not set
+# CONFIG_PCIE_MEDIATEK is not set
+# CONFIG_PCIE_MOBIVEIL is not set
+
+#
+# DesignWare PCI Core Support
+#
+# CONFIG_PCIE_DW_PLAT_HOST is not set
+# CONFIG_PCI_EXYNOS is not set
+# CONFIG_PCI_IMX6 is not set
+# CONFIG_PCIE_SPEAR13XX is not set
+# CONFIG_PCI_LAYERSCAPE is not set
+# CONFIG_PCI_HISI is not set
+# CONFIG_PCIE_QCOM is not set
+# CONFIG_PCIE_ARMADA_8K is not set
+# CONFIG_PCIE_ARTPEC6_HOST is not set
+# CONFIG_PCIE_KIRIN is not set
+# CONFIG_PCIE_HISI_STB is not set
+# CONFIG_PCI_MESON is not set
+# CONFIG_PCIE_TEGRA194 is not set
+# CONFIG_PCIE_UNIPHIER is not set
+# CONFIG_PCIE_AL is not set
+# end of DesignWare PCI Core Support
+# end of PCI controller drivers
+
+#
+# PCI Endpoint
+#
+# CONFIG_PCI_ENDPOINT is not set
+# end of PCI Endpoint
+
+#
+# PCI switch controller drivers
+#
+# CONFIG_PCI_SW_SWITCHTEC is not set
+# end of PCI switch controller drivers
+
+# CONFIG_PCCARD is not set
+# CONFIG_RAPIDIO is not set
+
+#
+# Generic Driver Options
+#
+# CONFIG_UEVENT_HELPER is not set
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+
+#
+# Firmware loader
+#
+CONFIG_FW_LOADER=y
+CONFIG_EXTRA_FIRMWARE=""
+# CONFIG_FW_LOADER_USER_HELPER is not set
+# CONFIG_FW_LOADER_COMPRESS is not set
+# end of Firmware loader
+
+CONFIG_ALLOW_DEV_COREDUMP=y
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set
+# CONFIG_TEST_ASYNC_DRIVER_PROBE is not set
+CONFIG_GENERIC_CPU_DEVICES=y
+CONFIG_REGMAP=y
+CONFIG_REGMAP_MMIO=y
+CONFIG_DMA_SHARED_BUFFER=y
+# CONFIG_DMA_FENCE_TRACE is not set
+CONFIG_GENERIC_ARCH_TOPOLOGY=y
+# end of Generic Driver Options
+
+#
+# Bus devices
+#
+# CONFIG_MOXTET is not set
+# CONFIG_QCOM_EBI2 is not set
+# end of Bus devices
+
+# CONFIG_CONNECTOR is not set
+# CONFIG_GNSS is not set
+# CONFIG_MTD is not set
+CONFIG_DTC=y
+CONFIG_OF=y
+# CONFIG_OF_UNITTEST is not set
+# CONFIG_OF_ALL_DTBS is not set
+CONFIG_OF_FLATTREE=y
+CONFIG_OF_EARLY_FLATTREE=y
+CONFIG_OF_KOBJ=y
+CONFIG_OF_ADDRESS=y
+CONFIG_OF_IRQ=y
+CONFIG_OF_NET=y
+CONFIG_OF_MDIO=y
+CONFIG_OF_RESERVED_MEM=y
+# CONFIG_OF_OVERLAY is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_NULL_BLK is not set
+CONFIG_CDROM=y
+# CONFIG_BLK_DEV_PCIESSD_MTIP32XX is not set
+# CONFIG_BLK_DEV_UMEM is not set
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_LOOP_MIN_COUNT=8
+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
+# CONFIG_BLK_DEV_DRBD is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_SKD is not set
+# CONFIG_BLK_DEV_SX8 is not set
+# CONFIG_BLK_DEV_RAM is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+CONFIG_VIRTIO_BLK=y
+# CONFIG_VIRTIO_BLK_SCSI is not set
+# CONFIG_BLK_DEV_RBD is not set
+# CONFIG_BLK_DEV_RSXX is not set
+
+#
+# NVME Support
+#
+# CONFIG_BLK_DEV_NVME is not set
+# CONFIG_NVME_FC is not set
+# end of NVME Support
+
+#
+# Misc devices
+#
+# CONFIG_AD525X_DPOT is not set
+# CONFIG_DUMMY_IRQ is not set
+# CONFIG_PHANTOM is not set
+# CONFIG_INTEL_MID_PTI is not set
+# CONFIG_TIFM_CORE is not set
+# CONFIG_ICS932S401 is not set
+# CONFIG_ATMEL_SSC is not set
+# CONFIG_ENCLOSURE_SERVICES is not set
+# CONFIG_HP_ILO is not set
+# CONFIG_QCOM_COINCELL is not set
+# CONFIG_QCOM_FASTRPC is not set
+# CONFIG_APDS9802ALS is not set
+# CONFIG_ISL29003 is not set
+# CONFIG_ISL29020 is not set
+# CONFIG_SENSORS_TSL2550 is not set
+# CONFIG_SENSORS_BH1770 is not set
+# CONFIG_SENSORS_APDS990X is not set
+# CONFIG_HMC6352 is not set
+# CONFIG_DS1682 is not set
+# CONFIG_PCH_PHUB is not set
+# CONFIG_LATTICE_ECP3_CONFIG is not set
+# CONFIG_SRAM is not set
+# CONFIG_PCI_ENDPOINT_TEST is not set
+# CONFIG_XILINX_SDFEC is not set
+# CONFIG_PVPANIC is not set
+# CONFIG_C2PORT is not set
+
+#
+# EEPROM support
+#
+# CONFIG_EEPROM_AT24 is not set
+# CONFIG_EEPROM_AT25 is not set
+# CONFIG_EEPROM_LEGACY is not set
+# CONFIG_EEPROM_MAX6875 is not set
+# CONFIG_EEPROM_93CX6 is not set
+# CONFIG_EEPROM_93XX46 is not set
+# CONFIG_EEPROM_IDT_89HPESX is not set
+# CONFIG_EEPROM_EE1004 is not set
+# end of EEPROM support
+
+# CONFIG_CB710_CORE is not set
+
+#
+# Texas Instruments shared transport line discipline
+#
+# CONFIG_TI_ST is not set
+# end of Texas Instruments shared transport line discipline
+
+# CONFIG_SENSORS_LIS3_SPI is not set
+# CONFIG_SENSORS_LIS3_I2C is not set
+# CONFIG_ALTERA_STAPL is not set
+
+#
+# Intel MIC & related support
+#
+
+#
+# Intel MIC Bus Driver
+#
+
+#
+# SCIF Bus Driver
+#
+
+#
+# VOP Bus Driver
+#
+# CONFIG_VOP_BUS is not set
+
+#
+# Intel MIC Host Driver
+#
+
+#
+# Intel MIC Card Driver
+#
+
+#
+# SCIF Driver
+#
+
+#
+# Intel MIC Coprocessor State Management (COSM) Drivers
+#
+
+#
+# VOP Driver
+#
+# end of Intel MIC & related support
+
+# CONFIG_GENWQE is not set
+# CONFIG_ECHO is not set
+# CONFIG_MISC_ALCOR_PCI is not set
+# CONFIG_MISC_RTSX_PCI is not set
+# CONFIG_MISC_RTSX_USB is not set
+# CONFIG_HABANA_AI is not set
+# end of Misc devices
+
+#
+# SCSI device support
+#
+CONFIG_SCSI_MOD=y
+# CONFIG_RAID_ATTRS is not set
+CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
+CONFIG_SCSI_PROC_FS=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+# CONFIG_CHR_DEV_ST is not set
+CONFIG_BLK_DEV_SR=y
+# CONFIG_BLK_DEV_SR_VENDOR is not set
+# CONFIG_CHR_DEV_SG is not set
+# CONFIG_CHR_DEV_SCH is not set
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+# CONFIG_SCSI_SCAN_ASYNC is not set
+
+#
+# SCSI Transports
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+# CONFIG_SCSI_ISCSI_ATTRS is not set
+# CONFIG_SCSI_SAS_ATTRS is not set
+# CONFIG_SCSI_SAS_LIBSAS is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+# end of SCSI Transports
+
+CONFIG_SCSI_LOWLEVEL=y
+# CONFIG_ISCSI_TCP is not set
+# CONFIG_ISCSI_BOOT_SYSFS is not set
+# CONFIG_SCSI_CXGB3_ISCSI is not set
+# CONFIG_SCSI_CXGB4_ISCSI is not set
+# CONFIG_SCSI_BNX2_ISCSI is not set
+# CONFIG_BE2ISCSI is not set
+# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
+# CONFIG_SCSI_HPSA is not set
+# CONFIG_SCSI_3W_9XXX is not set
+# CONFIG_SCSI_3W_SAS is not set
+# CONFIG_SCSI_ACARD is not set
+# CONFIG_SCSI_AACRAID is not set
+# CONFIG_SCSI_AIC7XXX is not set
+# CONFIG_SCSI_AIC79XX is not set
+# CONFIG_SCSI_AIC94XX is not set
+# CONFIG_SCSI_HISI_SAS is not set
+# CONFIG_SCSI_MVSAS is not set
+# CONFIG_SCSI_MVUMI is not set
+# CONFIG_SCSI_ADVANSYS is not set
+# CONFIG_SCSI_ARCMSR is not set
+# CONFIG_SCSI_ESAS2R is not set
+# CONFIG_MEGARAID_NEWGEN is not set
+# CONFIG_MEGARAID_LEGACY is not set
+# CONFIG_MEGARAID_SAS is not set
+# CONFIG_SCSI_MPT3SAS is not set
+# CONFIG_SCSI_MPT2SAS is not set
+# CONFIG_SCSI_SMARTPQI is not set
+# CONFIG_SCSI_UFSHCD is not set
+# CONFIG_SCSI_HPTIOP is not set
+# CONFIG_SCSI_MYRB is not set
+# CONFIG_SCSI_MYRS is not set
+# CONFIG_SCSI_SNIC is not set
+# CONFIG_SCSI_DMX3191D is not set
+# CONFIG_SCSI_FDOMAIN_PCI is not set
+# CONFIG_SCSI_GDTH is not set
+# CONFIG_SCSI_IPS is not set
+# CONFIG_SCSI_INITIO is not set
+# CONFIG_SCSI_INIA100 is not set
+# CONFIG_SCSI_STEX is not set
+# CONFIG_SCSI_SYM53C8XX_2 is not set
+# CONFIG_SCSI_IPR is not set
+# CONFIG_SCSI_QLOGIC_1280 is not set
+# CONFIG_SCSI_QLA_ISCSI is not set
+# CONFIG_SCSI_DC395x is not set
+# CONFIG_SCSI_AM53C974 is not set
+# CONFIG_SCSI_WD719X is not set
+# CONFIG_SCSI_DEBUG is not set
+# CONFIG_SCSI_PMCRAID is not set
+# CONFIG_SCSI_PM8001 is not set
+CONFIG_SCSI_VIRTIO=y
+# CONFIG_SCSI_DH is not set
+# end of SCSI device support
+
+CONFIG_ATA=y
+CONFIG_ATA_VERBOSE_ERROR=y
+CONFIG_SATA_PMP=y
+
+#
+# Controllers with non-SFF native interface
+#
+CONFIG_SATA_AHCI=y
+CONFIG_SATA_MOBILE_LPM_POLICY=0
+CONFIG_SATA_AHCI_PLATFORM=y
+# CONFIG_AHCI_IMX is not set
+# CONFIG_AHCI_CEVA is not set
+# CONFIG_AHCI_QORIQ is not set
+# CONFIG_SATA_GEMINI is not set
+# CONFIG_SATA_INIC162X is not set
+# CONFIG_SATA_ACARD_AHCI is not set
+# CONFIG_SATA_SIL24 is not set
+CONFIG_ATA_SFF=y
+
+#
+# SFF controllers with custom DMA interface
+#
+# CONFIG_PDC_ADMA is not set
+# CONFIG_SATA_QSTOR is not set
+# CONFIG_SATA_SX4 is not set
+CONFIG_ATA_BMDMA=y
+
+#
+# SATA SFF controllers with BMDMA
+#
+# CONFIG_ATA_PIIX is not set
+# CONFIG_SATA_DWC is not set
+# CONFIG_SATA_HIGHBANK is not set
+# CONFIG_SATA_MV is not set
+# CONFIG_SATA_NV is not set
+# CONFIG_SATA_PROMISE is not set
+# CONFIG_SATA_RCAR is not set
+# CONFIG_SATA_SIL is not set
+# CONFIG_SATA_SIS is not set
+# CONFIG_SATA_SVW is not set
+# CONFIG_SATA_ULI is not set
+# CONFIG_SATA_VIA is not set
+# CONFIG_SATA_VITESSE is not set
+
+#
+# PATA SFF controllers with BMDMA
+#
+# CONFIG_PATA_ALI is not set
+# CONFIG_PATA_AMD is not set
+# CONFIG_PATA_ARASAN_CF is not set
+# CONFIG_PATA_ARTOP is not set
+# CONFIG_PATA_ATIIXP is not set
+# CONFIG_PATA_ATP867X is not set
+# CONFIG_PATA_CMD64X is not set
+# CONFIG_PATA_CS5520 is not set
+# CONFIG_PATA_CS5530 is not set
+# CONFIG_PATA_CS5536 is not set
+# CONFIG_PATA_CYPRESS is not set
+# CONFIG_PATA_EFAR is not set
+# CONFIG_PATA_HPT366 is not set
+# CONFIG_PATA_HPT37X is not set
+# CONFIG_PATA_HPT3X2N is not set
+# CONFIG_PATA_HPT3X3 is not set
+# CONFIG_PATA_IT8213 is not set
+# CONFIG_PATA_IT821X is not set
+# CONFIG_PATA_JMICRON is not set
+# CONFIG_PATA_MARVELL is not set
+# CONFIG_PATA_NETCELL is not set
+# CONFIG_PATA_NINJA32 is not set
+# CONFIG_PATA_NS87415 is not set
+# CONFIG_PATA_OLDPIIX is not set
+# CONFIG_PATA_OPTIDMA is not set
+# CONFIG_PATA_PDC2027X is not set
+# CONFIG_PATA_PDC_OLD is not set
+# CONFIG_PATA_RADISYS is not set
+# CONFIG_PATA_RDC is not set
+# CONFIG_PATA_SC1200 is not set
+# CONFIG_PATA_SCH is not set
+# CONFIG_PATA_SERVERWORKS is not set
+# CONFIG_PATA_SIL680 is not set
+# CONFIG_PATA_SIS is not set
+# CONFIG_PATA_TOSHIBA is not set
+# CONFIG_PATA_TRIFLEX is not set
+# CONFIG_PATA_VIA is not set
+# CONFIG_PATA_WINBOND is not set
+
+#
+# PIO-only SFF controllers
+#
+# CONFIG_PATA_CMD640_PCI is not set
+# CONFIG_PATA_MPIIX is not set
+# CONFIG_PATA_NS87410 is not set
+# CONFIG_PATA_OPTI is not set
+# CONFIG_PATA_PLATFORM is not set
+# CONFIG_PATA_RZ1000 is not set
+
+#
+# Generic fallback / legacy drivers
+#
+# CONFIG_ATA_GENERIC is not set
+# CONFIG_PATA_LEGACY is not set
+# CONFIG_MD is not set
+# CONFIG_TARGET_CORE is not set
+# CONFIG_FUSION is not set
+
+#
+# IEEE 1394 (FireWire) support
+#
+# CONFIG_FIREWIRE is not set
+# CONFIG_FIREWIRE_NOSY is not set
+# end of IEEE 1394 (FireWire) support
+
+CONFIG_NETDEVICES=y
+CONFIG_MII=y
+CONFIG_NET_CORE=y
+# CONFIG_BONDING is not set
+# CONFIG_DUMMY is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_NET_FC is not set
+# CONFIG_NET_TEAM is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_IPVLAN is not set
+# CONFIG_VXLAN is not set
+# CONFIG_GENEVE is not set
+# CONFIG_GTP is not set
+# CONFIG_MACSEC is not set
+# CONFIG_NETCONSOLE is not set
+# CONFIG_TUN is not set
+# CONFIG_TUN_VNET_CROSS_LE is not set
+# CONFIG_VETH is not set
+CONFIG_VIRTIO_NET=y
+# CONFIG_NLMON is not set
+# CONFIG_ARCNET is not set
+
+#
+# CAIF transport drivers
+#
+
+#
+# Distributed Switch Architecture drivers
+#
+# end of Distributed Switch Architecture drivers
+
+CONFIG_ETHERNET=y
+CONFIG_NET_VENDOR_3COM=y
+# CONFIG_VORTEX is not set
+# CONFIG_TYPHOON is not set
+CONFIG_NET_VENDOR_ADAPTEC=y
+# CONFIG_ADAPTEC_STARFIRE is not set
+CONFIG_NET_VENDOR_AGERE=y
+# CONFIG_ET131X is not set
+CONFIG_NET_VENDOR_ALACRITECH=y
+# CONFIG_SLICOSS is not set
+CONFIG_NET_VENDOR_ALTEON=y
+# CONFIG_ACENIC is not set
+# CONFIG_ALTERA_TSE is not set
+CONFIG_NET_VENDOR_AMAZON=y
+# CONFIG_ENA_ETHERNET is not set
+CONFIG_NET_VENDOR_AMD=y
+# CONFIG_AMD8111_ETH is not set
+# CONFIG_PCNET32 is not set
+# CONFIG_AMD_XGBE is not set
+# CONFIG_NET_XGENE is not set
+# CONFIG_NET_XGENE_V2 is not set
+CONFIG_NET_VENDOR_AQUANTIA=y
+# CONFIG_AQTION is not set
+CONFIG_NET_VENDOR_ARC=y
+# CONFIG_ARC_EMAC is not set
+CONFIG_NET_VENDOR_ATHEROS=y
+# CONFIG_ATL2 is not set
+# CONFIG_ATL1 is not set
+# CONFIG_ATL1E is not set
+# CONFIG_ATL1C is not set
+# CONFIG_ALX is not set
+CONFIG_NET_VENDOR_AURORA=y
+# CONFIG_AURORA_NB8800 is not set
+CONFIG_NET_VENDOR_BROADCOM=y
+# CONFIG_B44 is not set
+# CONFIG_BCMGENET is not set
+# CONFIG_BNX2 is not set
+# CONFIG_CNIC is not set
+# CONFIG_TIGON3 is not set
+# CONFIG_BNX2X is not set
+# CONFIG_BGMAC_PLATFORM is not set
+# CONFIG_SYSTEMPORT is not set
+# CONFIG_BNXT is not set
+CONFIG_NET_VENDOR_BROCADE=y
+# CONFIG_BNA is not set
+CONFIG_NET_VENDOR_CADENCE=y
+CONFIG_MACB=y
+CONFIG_MACB_USE_HWSTAMP=y
+# CONFIG_MACB_PCI is not set
+# CONFIG_NET_CALXEDA_XGMAC is not set
+CONFIG_NET_VENDOR_CAVIUM=y
+# CONFIG_THUNDER_NIC_PF is not set
+# CONFIG_THUNDER_NIC_VF is not set
+# CONFIG_THUNDER_NIC_BGX is not set
+# CONFIG_THUNDER_NIC_RGX is not set
+# CONFIG_CAVIUM_PTP is not set
+# CONFIG_LIQUIDIO is not set
+# CONFIG_LIQUIDIO_VF is not set
+CONFIG_NET_VENDOR_CHELSIO=y
+# CONFIG_CHELSIO_T1 is not set
+# CONFIG_CHELSIO_T3 is not set
+# CONFIG_CHELSIO_T4 is not set
+# CONFIG_CHELSIO_T4VF is not set
+CONFIG_NET_VENDOR_CISCO=y
+# CONFIG_ENIC is not set
+CONFIG_NET_VENDOR_CORTINA=y
+# CONFIG_GEMINI_ETHERNET is not set
+# CONFIG_CX_ECAT is not set
+# CONFIG_DNET is not set
+CONFIG_NET_VENDOR_DEC=y
+# CONFIG_NET_TULIP is not set
+CONFIG_NET_VENDOR_DLINK=y
+# CONFIG_DL2K is not set
+# CONFIG_SUNDANCE is not set
+CONFIG_NET_VENDOR_EMULEX=y
+# CONFIG_BE2NET is not set
+CONFIG_NET_VENDOR_EZCHIP=y
+# CONFIG_EZCHIP_NPS_MANAGEMENT_ENET is not set
+CONFIG_NET_VENDOR_FARADAY=y
+CONFIG_NET_VENDOR_FREESCALE=y
+# CONFIG_FEC is not set
+# CONFIG_FSL_FMAN is not set
+# CONFIG_FSL_PQ_MDIO is not set
+# CONFIG_FSL_XGMAC_MDIO is not set
+# CONFIG_GIANFAR is not set
+# CONFIG_FSL_ENETC is not set
+# CONFIG_FSL_ENETC_VF is not set
+# CONFIG_FSL_ENETC_MDIO is not set
+CONFIG_NET_VENDOR_GOOGLE=y
+# CONFIG_GVE is not set
+CONFIG_NET_VENDOR_HISILICON=y
+# CONFIG_HIX5HD2_GMAC is not set
+# CONFIG_HISI_FEMAC is not set
+# CONFIG_HIP04_ETH is not set
+# CONFIG_HNS is not set
+# CONFIG_HNS_DSAF is not set
+# CONFIG_HNS_ENET is not set
+# CONFIG_HNS3 is not set
+CONFIG_NET_VENDOR_HP=y
+# CONFIG_HP100 is not set
+CONFIG_NET_VENDOR_HUAWEI=y
+CONFIG_NET_VENDOR_I825XX=y
+CONFIG_NET_VENDOR_INTEL=y
+# CONFIG_E100 is not set
+# CONFIG_E1000 is not set
+CONFIG_E1000E=y
+# CONFIG_IGB is not set
+# CONFIG_IGBVF is not set
+# CONFIG_IXGB is not set
+# CONFIG_IXGBE is not set
+# CONFIG_IXGBEVF is not set
+# CONFIG_I40E is not set
+# CONFIG_I40EVF is not set
+# CONFIG_ICE is not set
+# CONFIG_FM10K is not set
+# CONFIG_IGC is not set
+# CONFIG_JME is not set
+CONFIG_NET_VENDOR_MARVELL=y
+# CONFIG_MV643XX_ETH is not set
+# CONFIG_MVMDIO is not set
+# CONFIG_MVNETA is not set
+# CONFIG_MVPP2 is not set
+# CONFIG_PXA168_ETH is not set
+# CONFIG_SKGE is not set
+# CONFIG_SKY2 is not set
+# CONFIG_OCTEONTX2_AF is not set
+CONFIG_NET_VENDOR_MELLANOX=y
+# CONFIG_MLX4_EN is not set
+# CONFIG_MLX5_CORE is not set
+# CONFIG_MLXSW_CORE is not set
+# CONFIG_MLXFW is not set
+CONFIG_NET_VENDOR_MICREL=y
+# CONFIG_KS8842 is not set
+# CONFIG_KS8851 is not set
+# CONFIG_KS8851_MLL is not set
+# CONFIG_KSZ884X_PCI is not set
+CONFIG_NET_VENDOR_MICROCHIP=y
+# CONFIG_ENC28J60 is not set
+# CONFIG_ENCX24J600 is not set
+# CONFIG_LAN743X is not set
+CONFIG_NET_VENDOR_MICROSEMI=y
+CONFIG_NET_VENDOR_MYRI=y
+# CONFIG_MYRI10GE is not set
+# CONFIG_FEALNX is not set
+CONFIG_NET_VENDOR_NATSEMI=y
+# CONFIG_NATSEMI is not set
+# CONFIG_NS83820 is not set
+CONFIG_NET_VENDOR_NETERION=y
+# CONFIG_S2IO is not set
+# CONFIG_VXGE is not set
+CONFIG_NET_VENDOR_NETRONOME=y
+# CONFIG_NFP is not set
+CONFIG_NET_VENDOR_NI=y
+# CONFIG_NI_XGE_MANAGEMENT_ENET is not set
+CONFIG_NET_VENDOR_8390=y
+# CONFIG_AX88796 is not set
+# CONFIG_NE2K_PCI is not set
+CONFIG_NET_VENDOR_NVIDIA=y
+# CONFIG_FORCEDETH is not set
+# CONFIG_LPC_ENET is not set
+CONFIG_NET_VENDOR_OKI=y
+# CONFIG_PCH_GBE is not set
+# CONFIG_ETHOC is not set
+CONFIG_NET_VENDOR_PACKET_ENGINES=y
+# CONFIG_HAMACHI is not set
+# CONFIG_YELLOWFIN is not set
+CONFIG_NET_VENDOR_PENSANDO=y
+# CONFIG_IONIC is not set
+CONFIG_NET_VENDOR_QLOGIC=y
+# CONFIG_QLA3XXX is not set
+# CONFIG_QLCNIC is not set
+# CONFIG_NETXEN_NIC is not set
+# CONFIG_QED is not set
+CONFIG_NET_VENDOR_QUALCOMM=y
+# CONFIG_QCA7000_SPI is not set
+# CONFIG_QCOM_EMAC is not set
+# CONFIG_RMNET is not set
+CONFIG_NET_VENDOR_RDC=y
+# CONFIG_R6040 is not set
+CONFIG_NET_VENDOR_REALTEK=y
+# CONFIG_8139CP is not set
+# CONFIG_8139TOO is not set
+CONFIG_R8169=y
+CONFIG_NET_VENDOR_RENESAS=y
+# CONFIG_SH_ETH is not set
+# CONFIG_RAVB is not set
+CONFIG_NET_VENDOR_ROCKER=y
+CONFIG_NET_VENDOR_SAMSUNG=y
+# CONFIG_SXGBE_ETH is not set
+CONFIG_NET_VENDOR_SEEQ=y
+CONFIG_NET_VENDOR_SOLARFLARE=y
+# CONFIG_SFC is not set
+# CONFIG_SFC_FALCON is not set
+CONFIG_NET_VENDOR_SILAN=y
+# CONFIG_SC92031 is not set
+CONFIG_NET_VENDOR_SIS=y
+# CONFIG_SIS900 is not set
+# CONFIG_SIS190 is not set
+CONFIG_NET_VENDOR_SMSC=y
+# CONFIG_EPIC100 is not set
+# CONFIG_SMSC911X is not set
+# CONFIG_SMSC9420 is not set
+CONFIG_NET_VENDOR_SOCIONEXT=y
+# CONFIG_SNI_AVE is not set
+# CONFIG_SNI_NETSEC is not set
+CONFIG_NET_VENDOR_STMICRO=y
+CONFIG_STMMAC_ETH=y
+# CONFIG_STMMAC_SELFTESTS is not set
+CONFIG_STMMAC_PLATFORM=y
+# CONFIG_DWMAC_DWC_QOS_ETH is not set
+CONFIG_DWMAC_GENERIC=y
+# CONFIG_DWMAC_ANARION is not set
+# CONFIG_DWMAC_IPQ806X is not set
+# CONFIG_DWMAC_LPC18XX is not set
+# CONFIG_DWMAC_MEDIATEK is not set
+# CONFIG_DWMAC_MESON is not set
+# CONFIG_DWMAC_OXNAS is not set
+# CONFIG_DWMAC_QCOM_ETHQOS is not set
+# CONFIG_DWMAC_ROCKCHIP is not set
+# CONFIG_DWMAC_SOCFPGA is not set
+# CONFIG_DWMAC_STI is not set
+# CONFIG_DWMAC_STM32 is not set
+# CONFIG_DWMAC_SUNXI is not set
+# CONFIG_DWMAC_SUN8I is not set
+CONFIG_STMMAC_PCI=y
+CONFIG_NET_VENDOR_SUN=y
+# CONFIG_HAPPYMEAL is not set
+# CONFIG_SUNGEM is not set
+# CONFIG_CASSINI is not set
+# CONFIG_NIU is not set
+CONFIG_NET_VENDOR_SYNOPSYS=y
+# CONFIG_DWC_XLGMAC is not set
+CONFIG_NET_VENDOR_TEHUTI=y
+# CONFIG_TEHUTI is not set
+CONFIG_NET_VENDOR_TI=y
+# CONFIG_TI_DAVINCI_EMAC is not set
+# CONFIG_TI_DAVINCI_MDIO is not set
+# CONFIG_TI_CPSW_PHY_SEL is not set
+# CONFIG_TI_CPSW is not set
+# CONFIG_TI_CPTS is not set
+# CONFIG_TLAN is not set
+CONFIG_NET_VENDOR_VIA=y
+# CONFIG_VIA_RHINE is not set
+# CONFIG_VIA_VELOCITY is not set
+CONFIG_NET_VENDOR_WIZNET=y
+# CONFIG_WIZNET_W5100 is not set
+# CONFIG_WIZNET_W5300 is not set
+CONFIG_NET_VENDOR_XILINX=y
+# CONFIG_XILINX_AXI_EMAC is not set
+# CONFIG_XILINX_LL_TEMAC is not set
+# CONFIG_FDDI is not set
+# CONFIG_HIPPI is not set
+CONFIG_MDIO_DEVICE=y
+CONFIG_MDIO_BUS=y
+# CONFIG_MDIO_ASPEED is not set
+# CONFIG_MDIO_BCM_IPROC is not set
+# CONFIG_MDIO_BCM_UNIMAC is not set
+# CONFIG_MDIO_BITBANG is not set
+# CONFIG_MDIO_BUS_MUX_BCM_IPROC is not set
+# CONFIG_MDIO_BUS_MUX_MESON_G12A is not set
+# CONFIG_MDIO_BUS_MUX_MMIOREG is not set
+# CONFIG_MDIO_BUS_MUX_MULTIPLEXER is not set
+# CONFIG_MDIO_HISI_FEMAC is not set
+# CONFIG_MDIO_MOXART is not set
+# CONFIG_MDIO_MSCC_MIIM is not set
+# CONFIG_MDIO_OCTEON is not set
+# CONFIG_MDIO_SUN4I is not set
+# CONFIG_MDIO_THUNDER is not set
+# CONFIG_MDIO_XGENE is not set
+CONFIG_PHYLINK=y
+CONFIG_PHYLIB=y
+CONFIG_SWPHY=y
+
+#
+# MII PHY device drivers
+#
+# CONFIG_SFP is not set
+# CONFIG_ADIN_PHY is not set
+# CONFIG_AMD_PHY is not set
+# CONFIG_AQUANTIA_PHY is not set
+# CONFIG_AX88796B_PHY is not set
+# CONFIG_AT803X_PHY is not set
+# CONFIG_BCM63XX_PHY is not set
+# CONFIG_BCM7XXX_PHY is not set
+# CONFIG_BCM87XX_PHY is not set
+# CONFIG_BROADCOM_PHY is not set
+# CONFIG_CICADA_PHY is not set
+# CONFIG_CORTINA_PHY is not set
+# CONFIG_DAVICOM_PHY is not set
+# CONFIG_DP83822_PHY is not set
+# CONFIG_DP83TC811_PHY is not set
+# CONFIG_DP83848_PHY is not set
+# CONFIG_DP83867_PHY is not set
+CONFIG_FIXED_PHY=y
+# CONFIG_ICPLUS_PHY is not set
+# CONFIG_INTEL_XWAY_PHY is not set
+# CONFIG_LSI_ET1011C_PHY is not set
+# CONFIG_LXT_PHY is not set
+# CONFIG_MARVELL_PHY is not set
+# CONFIG_MARVELL_10G_PHY is not set
+# CONFIG_MESON_GXL_PHY is not set
+# CONFIG_MICREL_PHY is not set
+# CONFIG_MICROCHIP_PHY is not set
+# CONFIG_MICROCHIP_T1_PHY is not set
+CONFIG_MICROSEMI_PHY=y
+# CONFIG_NATIONAL_PHY is not set
+# CONFIG_NXP_TJA11XX_PHY is not set
+# CONFIG_QSEMI_PHY is not set
+CONFIG_REALTEK_PHY=y
+# CONFIG_RENESAS_PHY is not set
+# CONFIG_ROCKCHIP_PHY is not set
+# CONFIG_SMSC_PHY is not set
+# CONFIG_STE10XP is not set
+# CONFIG_TERANETICS_PHY is not set
+# CONFIG_VITESSE_PHY is not set
+# CONFIG_XILINX_GMII2RGMII is not set
+# CONFIG_MICREL_KS8995MA is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+CONFIG_USB_NET_DRIVERS=y
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_RTL8150 is not set
+# CONFIG_USB_RTL8152 is not set
+# CONFIG_USB_LAN78XX is not set
+# CONFIG_USB_USBNET is not set
+# CONFIG_USB_IPHETH is not set
+CONFIG_WLAN=y
+# CONFIG_WIRELESS_WDS is not set
+CONFIG_WLAN_VENDOR_ADMTEK=y
+CONFIG_WLAN_VENDOR_ATH=y
+# CONFIG_ATH_DEBUG is not set
+# CONFIG_ATH5K_PCI is not set
+CONFIG_WLAN_VENDOR_ATMEL=y
+CONFIG_WLAN_VENDOR_BROADCOM=y
+CONFIG_WLAN_VENDOR_CISCO=y
+CONFIG_WLAN_VENDOR_INTEL=y
+CONFIG_WLAN_VENDOR_INTERSIL=y
+# CONFIG_HOSTAP is not set
+# CONFIG_PRISM54 is not set
+CONFIG_WLAN_VENDOR_MARVELL=y
+CONFIG_WLAN_VENDOR_MEDIATEK=y
+CONFIG_WLAN_VENDOR_RALINK=y
+CONFIG_WLAN_VENDOR_REALTEK=y
+CONFIG_WLAN_VENDOR_RSI=y
+CONFIG_WLAN_VENDOR_ST=y
+CONFIG_WLAN_VENDOR_TI=y
+CONFIG_WLAN_VENDOR_ZYDAS=y
+CONFIG_WLAN_VENDOR_QUANTENNA=y
+
+#
+# Enable WiMAX (Networking options) to see the WiMAX drivers
+#
+# CONFIG_WAN is not set
+# CONFIG_VMXNET3 is not set
+# CONFIG_NETDEVSIM is not set
+CONFIG_NET_FAILOVER=y
+# CONFIG_ISDN is not set
+# CONFIG_NVM is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+# CONFIG_INPUT_SPARSEKMAP is not set
+# CONFIG_INPUT_MATRIXKMAP is not set
+
+#
+# Userland interfaces
+#
+CONFIG_INPUT_MOUSEDEV=y
+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+CONFIG_INPUT_KEYBOARD=y
+# CONFIG_KEYBOARD_ADP5588 is not set
+# CONFIG_KEYBOARD_ADP5589 is not set
+CONFIG_KEYBOARD_ATKBD=y
+# CONFIG_KEYBOARD_QT1050 is not set
+# CONFIG_KEYBOARD_QT1070 is not set
+# CONFIG_KEYBOARD_QT2160 is not set
+# CONFIG_KEYBOARD_DLINK_DIR685 is not set
+# CONFIG_KEYBOARD_LKKBD is not set
+# CONFIG_KEYBOARD_EP93XX is not set
+# CONFIG_KEYBOARD_GPIO is not set
+# CONFIG_KEYBOARD_TCA6416 is not set
+# CONFIG_KEYBOARD_TCA8418 is not set
+# CONFIG_KEYBOARD_MATRIX is not set
+# CONFIG_KEYBOARD_LM8333 is not set
+# CONFIG_KEYBOARD_MAX7359 is not set
+# CONFIG_KEYBOARD_MCS is not set
+# CONFIG_KEYBOARD_MPR121 is not set
+# CONFIG_KEYBOARD_SNVS_PWRKEY is not set
+# CONFIG_KEYBOARD_NEWTON is not set
+# CONFIG_KEYBOARD_OPENCORES is not set
+# CONFIG_KEYBOARD_SAMSUNG is not set
+# CONFIG_KEYBOARD_GOLDFISH_EVENTS is not set
+# CONFIG_KEYBOARD_STOWAWAY is not set
+# CONFIG_KEYBOARD_ST_KEYSCAN is not set
+# CONFIG_KEYBOARD_SUNKBD is not set
+# CONFIG_KEYBOARD_SH_KEYSC is not set
+# CONFIG_KEYBOARD_OMAP4 is not set
+# CONFIG_KEYBOARD_XTKBD is not set
+# CONFIG_KEYBOARD_CAP11XX is not set
+# CONFIG_KEYBOARD_BCM is not set
+CONFIG_INPUT_MOUSE=y
+CONFIG_MOUSE_PS2=y
+CONFIG_MOUSE_PS2_ALPS=y
+CONFIG_MOUSE_PS2_BYD=y
+CONFIG_MOUSE_PS2_LOGIPS2PP=y
+CONFIG_MOUSE_PS2_SYNAPTICS=y
+CONFIG_MOUSE_PS2_SYNAPTICS_SMBUS=y
+CONFIG_MOUSE_PS2_CYPRESS=y
+CONFIG_MOUSE_PS2_TRACKPOINT=y
+# CONFIG_MOUSE_PS2_ELANTECH is not set
+# CONFIG_MOUSE_PS2_SENTELIC is not set
+# CONFIG_MOUSE_PS2_TOUCHKIT is not set
+CONFIG_MOUSE_PS2_FOCALTECH=y
+CONFIG_MOUSE_PS2_SMBUS=y
+# CONFIG_MOUSE_SERIAL is not set
+# CONFIG_MOUSE_APPLETOUCH is not set
+# CONFIG_MOUSE_BCM5974 is not set
+# CONFIG_MOUSE_CYAPA is not set
+# CONFIG_MOUSE_ELAN_I2C is not set
+# CONFIG_MOUSE_VSXXXAA is not set
+# CONFIG_MOUSE_GPIO is not set
+# CONFIG_MOUSE_SYNAPTICS_I2C is not set
+# CONFIG_MOUSE_SYNAPTICS_USB is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+# CONFIG_RMI4_CORE is not set
+
+#
+# Hardware I/O ports
+#
+CONFIG_SERIO=y
+CONFIG_SERIO_SERPORT=y
+# CONFIG_SERIO_PCIPS2 is not set
+CONFIG_SERIO_LIBPS2=y
+# CONFIG_SERIO_RAW is not set
+# CONFIG_SERIO_ALTERA_PS2 is not set
+# CONFIG_SERIO_PS2MULT is not set
+# CONFIG_SERIO_ARC_PS2 is not set
+# CONFIG_SERIO_APBPS2 is not set
+# CONFIG_SERIO_OLPC_APSP is not set
+# CONFIG_SERIO_SUN4I_PS2 is not set
+# CONFIG_USERIO is not set
+# CONFIG_GAMEPORT is not set
+# end of Hardware I/O ports
+# end of Input device support
+
+#
+# Character devices
+#
+CONFIG_TTY=y
+CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+CONFIG_VT_HW_CONSOLE_BINDING=y
+CONFIG_UNIX98_PTYS=y
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=256
+# CONFIG_SERIAL_NONSTANDARD is not set
+# CONFIG_NOZOMI is not set
+# CONFIG_N_GSM is not set
+# CONFIG_TRACE_SINK is not set
+# CONFIG_NULL_TTY is not set
+CONFIG_LDISC_AUTOLOAD=y
+CONFIG_DEVMEM=y
+# CONFIG_DEVKMEM is not set
+
+#
+# Serial drivers
+#
+CONFIG_SERIAL_EARLYCON=y
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y
+# CONFIG_SERIAL_8250_FINTEK is not set
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_DMA=y
+CONFIG_SERIAL_8250_PCI=y
+CONFIG_SERIAL_8250_EXAR=y
+CONFIG_SERIAL_8250_NR_UARTS=4
+CONFIG_SERIAL_8250_RUNTIME_UARTS=4
+# CONFIG_SERIAL_8250_EXTENDED is not set
+# CONFIG_SERIAL_8250_ASPEED_VUART is not set
+CONFIG_SERIAL_8250_DWLIB=y
+CONFIG_SERIAL_8250_DW=y
+# CONFIG_SERIAL_8250_RT288X is not set
+# CONFIG_SERIAL_8250_LPC18XX is not set
+# CONFIG_SERIAL_8250_UNIPHIER is not set
+# CONFIG_SERIAL_8250_INGENIC is not set
+CONFIG_SERIAL_8250_LPSS=y
+CONFIG_SERIAL_8250_MID=y
+CONFIG_SERIAL_OF_PLATFORM=y
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_EARLYCON_RISCV_SBI=y
+# CONFIG_SERIAL_ATMEL is not set
+# CONFIG_SERIAL_CLPS711X is not set
+# CONFIG_SERIAL_MAX3100 is not set
+# CONFIG_SERIAL_MAX310X is not set
+# CONFIG_SERIAL_IMX is not set
+# CONFIG_SERIAL_UARTLITE is not set
+# CONFIG_SERIAL_SH_SCI is not set
+# CONFIG_SERIAL_HS_LPC32XX is not set
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+# CONFIG_SERIAL_JSM is not set
+CONFIG_SERIAL_SIFIVE=y
+CONFIG_SERIAL_SIFIVE_CONSOLE=y
+# CONFIG_SERIAL_SCCNXP is not set
+# CONFIG_SERIAL_SC16IS7XX is not set
+# CONFIG_SERIAL_TIMBERDALE is not set
+# CONFIG_SERIAL_BCM63XX is not set
+# CONFIG_SERIAL_ALTERA_JTAGUART is not set
+# CONFIG_SERIAL_ALTERA_UART is not set
+# CONFIG_SERIAL_IFX6X60 is not set
+# CONFIG_SERIAL_PCH_UART is not set
+# CONFIG_SERIAL_MXS_AUART is not set
+# CONFIG_SERIAL_XILINX_PS_UART is not set
+# CONFIG_SERIAL_MPS2_UART is not set
+# CONFIG_SERIAL_ARC is not set
+# CONFIG_SERIAL_RP2 is not set
+# CONFIG_SERIAL_FSL_LPUART is not set
+# CONFIG_SERIAL_FSL_LINFLEXUART is not set
+# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set
+# CONFIG_SERIAL_ST_ASC is not set
+# CONFIG_SERIAL_STM32 is not set
+# CONFIG_SERIAL_MVEBU_UART is not set
+# CONFIG_SERIAL_OWL is not set
+# CONFIG_SERIAL_RDA is not set
+# CONFIG_SERIAL_MILBEAUT_USIO is not set
+# end of Serial drivers
+
+# CONFIG_SERIAL_DEV_BUS is not set
+# CONFIG_TTY_PRINTK is not set
+CONFIG_HVC_DRIVER=y
+CONFIG_HVC_RISCV_SBI=y
+CONFIG_VIRTIO_CONSOLE=y
+# CONFIG_IPMI_HANDLER is not set
+# CONFIG_ASPEED_KCS_IPMI_BMC is not set
+# CONFIG_NPCM7XX_KCS_IPMI_BMC is not set
+# CONFIG_ASPEED_BT_IPMI_BMC is not set
+CONFIG_HW_RANDOM=y
+# CONFIG_HW_RANDOM_TIMERIOMEM is not set
+CONFIG_HW_RANDOM_VIRTIO=y
+CONFIG_HW_RANDOM_STM32=y
+CONFIG_HW_RANDOM_MESON=y
+CONFIG_HW_RANDOM_CAVIUM=y
+CONFIG_HW_RANDOM_MTK=y
+CONFIG_HW_RANDOM_EXYNOS=y
+# CONFIG_APPLICOM is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+CONFIG_DEVPORT=y
+# CONFIG_XILLYBUS is not set
+# end of Character devices
+
+# CONFIG_RANDOM_TRUST_BOOTLOADER is not set
+
+#
+# I2C support
+#
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_COMPAT=y
+# CONFIG_I2C_CHARDEV is not set
+# CONFIG_I2C_MUX is not set
+CONFIG_I2C_HELPER_AUTO=y
+CONFIG_I2C_ALGOBIT=y
+
+#
+# I2C Hardware Bus support
+#
+
+#
+# PC SMBus host controller drivers
+#
+# CONFIG_I2C_ALI1535 is not set
+# CONFIG_I2C_ALI1563 is not set
+# CONFIG_I2C_ALI15X3 is not set
+# CONFIG_I2C_AMD756 is not set
+# CONFIG_I2C_AMD8111 is not set
+# CONFIG_I2C_HIX5HD2 is not set
+# CONFIG_I2C_I801 is not set
+# CONFIG_I2C_ISCH is not set
+# CONFIG_I2C_PIIX4 is not set
+# CONFIG_I2C_NFORCE2 is not set
+# CONFIG_I2C_NVIDIA_GPU is not set
+# CONFIG_I2C_SIS5595 is not set
+# CONFIG_I2C_SIS630 is not set
+# CONFIG_I2C_SIS96X is not set
+# CONFIG_I2C_VIA is not set
+# CONFIG_I2C_VIAPRO is not set
+
+#
+# I2C system bus drivers (mostly embedded / system-on-chip)
+#
+# CONFIG_I2C_ASPEED is not set
+# CONFIG_I2C_AXXIA is not set
+# CONFIG_I2C_BCM_IPROC is not set
+CONFIG_I2C_BRCMSTB=y
+# CONFIG_I2C_CBUS_GPIO is not set
+# CONFIG_I2C_DESIGNWARE_PLATFORM is not set
+# CONFIG_I2C_DESIGNWARE_PCI is not set
+# CONFIG_I2C_EFM32 is not set
+# CONFIG_I2C_EG20T is not set
+# CONFIG_I2C_EMEV2 is not set
+# CONFIG_I2C_GPIO is not set
+# CONFIG_I2C_IMG is not set
+# CONFIG_I2C_IMX_LPI2C is not set
+# CONFIG_I2C_JZ4780 is not set
+# CONFIG_I2C_LPC2K is not set
+# CONFIG_I2C_MESON is not set
+# CONFIG_I2C_MT65XX is not set
+# CONFIG_I2C_MT7621 is not set
+# CONFIG_I2C_OCORES is not set
+# CONFIG_I2C_OWL is not set
+# CONFIG_I2C_PCA_PLATFORM is not set
+# CONFIG_I2C_RIIC is not set
+# CONFIG_I2C_RK3X is not set
+# CONFIG_I2C_SH_MOBILE is not set
+# CONFIG_I2C_SIMTEC is not set
+# CONFIG_I2C_STM32F4 is not set
+# CONFIG_I2C_STM32F7 is not set
+# CONFIG_I2C_SUN6I_P2WI is not set
+# CONFIG_I2C_SYNQUACER is not set
+# CONFIG_I2C_UNIPHIER is not set
+# CONFIG_I2C_UNIPHIER_F is not set
+# CONFIG_I2C_VERSATILE is not set
+# CONFIG_I2C_THUNDERX is not set
+# CONFIG_I2C_XILINX is not set
+# CONFIG_I2C_XLP9XX is not set
+# CONFIG_I2C_RCAR is not set
+
+#
+# External I2C/SMBus adapter drivers
+#
+# CONFIG_I2C_DIOLAN_U2C is not set
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_ROBOTFUZZ_OSIF is not set
+# CONFIG_I2C_TAOS_EVM is not set
+# CONFIG_I2C_TINY_USB is not set
+
+#
+# Other I2C/SMBus bus drivers
+#
+# end of I2C Hardware Bus support
+
+# CONFIG_I2C_STUB is not set
+# CONFIG_I2C_SLAVE is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# end of I2C support
+
+# CONFIG_I3C is not set
+CONFIG_SPI=y
+# CONFIG_SPI_DEBUG is not set
+CONFIG_SPI_MASTER=y
+# CONFIG_SPI_MEM is not set
+
+#
+# SPI Master Controller Drivers
+#
+# CONFIG_SPI_ALTERA is not set
+# CONFIG_SPI_ATH79 is not set
+# CONFIG_SPI_ARMADA_3700 is not set
+# CONFIG_SPI_ATMEL is not set
+# CONFIG_SPI_AXI_SPI_ENGINE is not set
+# CONFIG_SPI_BCM2835AUX is not set
+# CONFIG_SPI_BCM63XX is not set
+# CONFIG_SPI_BCM63XX_HSSPI is not set
+# CONFIG_SPI_BCM_QSPI is not set
+# CONFIG_SPI_BITBANG is not set
+# CONFIG_SPI_CADENCE is not set
+# CONFIG_SPI_CLPS711X is not set
+# CONFIG_SPI_DESIGNWARE is not set
+# CONFIG_SPI_EP93XX is not set
+# CONFIG_SPI_FSL_LPSPI is not set
+# CONFIG_SPI_FSL_QUADSPI is not set
+# CONFIG_SPI_NXP_FLEXSPI is not set
+# CONFIG_SPI_GPIO is not set
+# CONFIG_SPI_IMG_SPFI is not set
+# CONFIG_SPI_IMX is not set
+# CONFIG_SPI_JCORE is not set
+# CONFIG_SPI_LP8841_RTC is not set
+# CONFIG_SPI_FSL_SPI is not set
+# CONFIG_SPI_FSL_DSPI is not set
+# CONFIG_SPI_MESON_SPICC is not set
+# CONFIG_SPI_MESON_SPIFC is not set
+# CONFIG_SPI_MT65XX is not set
+# CONFIG_SPI_MT7621 is not set
+# CONFIG_SPI_NPCM_FIU is not set
+# CONFIG_SPI_NPCM_PSPI is not set
+# CONFIG_SPI_LANTIQ_SSC is not set
+# CONFIG_SPI_OC_TINY is not set
+# CONFIG_SPI_OMAP24XX is not set
+# CONFIG_SPI_TI_QSPI is not set
+# CONFIG_SPI_OMAP_100K is not set
+# CONFIG_SPI_ORION is not set
+# CONFIG_SPI_PIC32 is not set
+# CONFIG_SPI_PIC32_SQI is not set
+# CONFIG_SPI_PXA2XX is not set
+# CONFIG_SPI_ROCKCHIP is not set
+# CONFIG_SPI_RSPI is not set
+# CONFIG_SPI_S3C64XX is not set
+# CONFIG_SPI_SC18IS602 is not set
+# CONFIG_SPI_SH_MSIOF is not set
+# CONFIG_SPI_SH is not set
+# CONFIG_SPI_SH_HSPI is not set
+CONFIG_SPI_SIFIVE=y
+# CONFIG_SPI_SPRD is not set
+# CONFIG_SPI_SPRD_ADI is not set
+# CONFIG_SPI_STM32 is not set
+# CONFIG_SPI_STM32_QSPI is not set
+# CONFIG_SPI_ST_SSC4 is not set
+# CONFIG_SPI_SUN4I is not set
+# CONFIG_SPI_SUN6I is not set
+# CONFIG_SPI_SYNQUACER is not set
+# CONFIG_SPI_MXIC is not set
+# CONFIG_SPI_TEGRA114 is not set
+# CONFIG_SPI_TEGRA20_SFLASH is not set
+# CONFIG_SPI_TEGRA20_SLINK is not set
+# CONFIG_SPI_THUNDERX is not set
+# CONFIG_SPI_TOPCLIFF_PCH is not set
+# CONFIG_SPI_UNIPHIER is not set
+# CONFIG_SPI_XCOMM is not set
+# CONFIG_SPI_XILINX is not set
+# CONFIG_SPI_XLP is not set
+# CONFIG_SPI_XTENSA_XTFPGA is not set
+# CONFIG_SPI_ZYNQ_QSPI is not set
+# CONFIG_SPI_ZYNQMP_GQSPI is not set
+
+#
+# SPI Protocol Masters
+#
+# CONFIG_SPI_SPIDEV is not set
+# CONFIG_SPI_LOOPBACK_TEST is not set
+# CONFIG_SPI_TLE62X0 is not set
+# CONFIG_SPI_SLAVE is not set
+# CONFIG_SPMI is not set
+# CONFIG_HSI is not set
+# CONFIG_PPS is not set
+
+#
+# PTP clock support
+#
+# CONFIG_PTP_1588_CLOCK is not set
+
+#
+# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks.
+#
+# CONFIG_PTP_1588_CLOCK_PCH is not set
+# end of PTP clock support
+
+# CONFIG_PINCTRL is not set
+# CONFIG_GPIOLIB is not set
+# CONFIG_W1 is not set
+# CONFIG_POWER_AVS is not set
+# CONFIG_POWER_RESET is not set
+CONFIG_POWER_SUPPLY=y
+# CONFIG_POWER_SUPPLY_DEBUG is not set
+CONFIG_POWER_SUPPLY_HWMON=y
+# CONFIG_PDA_POWER is not set
+# CONFIG_TEST_POWER is not set
+# CONFIG_CHARGER_ADP5061 is not set
+# CONFIG_BATTERY_ACT8945A is not set
+# CONFIG_BATTERY_DS2780 is not set
+# CONFIG_BATTERY_DS2781 is not set
+# CONFIG_BATTERY_DS2782 is not set
+# CONFIG_BATTERY_SBS is not set
+# CONFIG_CHARGER_SBS is not set
+# CONFIG_BATTERY_BQ27XXX is not set
+# CONFIG_BATTERY_MAX17040 is not set
+# CONFIG_BATTERY_MAX17042 is not set
+# CONFIG_CHARGER_MAX8903 is not set
+# CONFIG_CHARGER_LP8727 is not set
+# CONFIG_CHARGER_GPIO is not set
+# CONFIG_CHARGER_DETECTOR_MAX14656 is not set
+# CONFIG_CHARGER_BQ2415X is not set
+# CONFIG_CHARGER_BQ24735 is not set
+# CONFIG_CHARGER_BQ25890 is not set
+# CONFIG_CHARGER_SMB347 is not set
+# CONFIG_BATTERY_GAUGE_LTC2941 is not set
+# CONFIG_BATTERY_GOLDFISH is not set
+# CONFIG_CHARGER_RT9455 is not set
+# CONFIG_CHARGER_SC2731 is not set
+CONFIG_HWMON=y
+# CONFIG_HWMON_DEBUG_CHIP is not set
+
+#
+# Native drivers
+#
+# CONFIG_SENSORS_AD7314 is not set
+# CONFIG_SENSORS_AD7414 is not set
+# CONFIG_SENSORS_AD7418 is not set
+# CONFIG_SENSORS_ADM1021 is not set
+# CONFIG_SENSORS_ADM1025 is not set
+# CONFIG_SENSORS_ADM1026 is not set
+# CONFIG_SENSORS_ADM1029 is not set
+# CONFIG_SENSORS_ADM1031 is not set
+# CONFIG_SENSORS_ADM9240 is not set
+# CONFIG_SENSORS_ADT7310 is not set
+# CONFIG_SENSORS_ADT7410 is not set
+# CONFIG_SENSORS_ADT7411 is not set
+# CONFIG_SENSORS_ADT7462 is not set
+# CONFIG_SENSORS_ADT7470 is not set
+# CONFIG_SENSORS_ADT7475 is not set
+# CONFIG_SENSORS_AS370 is not set
+# CONFIG_SENSORS_ASC7621 is not set
+# CONFIG_SENSORS_ASPEED is not set
+# CONFIG_SENSORS_ATXP1 is not set
+# CONFIG_SENSORS_DS620 is not set
+# CONFIG_SENSORS_DS1621 is not set
+# CONFIG_SENSORS_I5K_AMB is not set
+# CONFIG_SENSORS_F71805F is not set
+# CONFIG_SENSORS_F71882FG is not set
+# CONFIG_SENSORS_F75375S is not set
+# CONFIG_SENSORS_GL518SM is not set
+# CONFIG_SENSORS_GL520SM is not set
+# CONFIG_SENSORS_G760A is not set
+# CONFIG_SENSORS_G762 is not set
+# CONFIG_SENSORS_HIH6130 is not set
+# CONFIG_SENSORS_IT87 is not set
+# CONFIG_SENSORS_JC42 is not set
+# CONFIG_SENSORS_POWR1220 is not set
+# CONFIG_SENSORS_LINEAGE is not set
+# CONFIG_SENSORS_LTC2945 is not set
+# CONFIG_SENSORS_LTC2990 is not set
+# CONFIG_SENSORS_LTC4151 is not set
+# CONFIG_SENSORS_LTC4215 is not set
+# CONFIG_SENSORS_LTC4222 is not set
+# CONFIG_SENSORS_LTC4245 is not set
+# CONFIG_SENSORS_LTC4260 is not set
+# CONFIG_SENSORS_LTC4261 is not set
+# CONFIG_SENSORS_MAX1111 is not set
+# CONFIG_SENSORS_MAX16065 is not set
+# CONFIG_SENSORS_MAX1619 is not set
+# CONFIG_SENSORS_MAX1668 is not set
+# CONFIG_SENSORS_MAX197 is not set
+# CONFIG_SENSORS_MAX31722 is not set
+# CONFIG_SENSORS_MAX6621 is not set
+# CONFIG_SENSORS_MAX6639 is not set
+# CONFIG_SENSORS_MAX6642 is not set
+# CONFIG_SENSORS_MAX6650 is not set
+# CONFIG_SENSORS_MAX6697 is not set
+# CONFIG_SENSORS_MAX31790 is not set
+# CONFIG_SENSORS_MCP3021 is not set
+# CONFIG_SENSORS_TC654 is not set
+# CONFIG_SENSORS_ADCXX is not set
+# CONFIG_SENSORS_LM63 is not set
+# CONFIG_SENSORS_LM70 is not set
+# CONFIG_SENSORS_LM73 is not set
+# CONFIG_SENSORS_LM75 is not set
+# CONFIG_SENSORS_LM77 is not set
+# CONFIG_SENSORS_LM78 is not set
+# CONFIG_SENSORS_LM80 is not set
+# CONFIG_SENSORS_LM83 is not set
+# CONFIG_SENSORS_LM85 is not set
+# CONFIG_SENSORS_LM87 is not set
+# CONFIG_SENSORS_LM90 is not set
+# CONFIG_SENSORS_LM92 is not set
+# CONFIG_SENSORS_LM93 is not set
+# CONFIG_SENSORS_LM95234 is not set
+# CONFIG_SENSORS_LM95241 is not set
+# CONFIG_SENSORS_LM95245 is not set
+# CONFIG_SENSORS_PC87360 is not set
+# CONFIG_SENSORS_PC87427 is not set
+# CONFIG_SENSORS_NTC_THERMISTOR is not set
+# CONFIG_SENSORS_NCT6683 is not set
+# CONFIG_SENSORS_NCT6775 is not set
+# CONFIG_SENSORS_NCT7802 is not set
+# CONFIG_SENSORS_NCT7904 is not set
+# CONFIG_SENSORS_NPCM7XX is not set
+# CONFIG_SENSORS_OCC_P8_I2C is not set
+# CONFIG_SENSORS_PCF8591 is not set
+# CONFIG_PMBUS is not set
+# CONFIG_SENSORS_PWM_FAN is not set
+# CONFIG_SENSORS_RASPBERRYPI_HWMON is not set
+# CONFIG_SENSORS_SHT15 is not set
+# CONFIG_SENSORS_SHT21 is not set
+# CONFIG_SENSORS_SHT3x is not set
+# CONFIG_SENSORS_SHTC1 is not set
+# CONFIG_SENSORS_SIS5595 is not set
+# CONFIG_SENSORS_DME1737 is not set
+# CONFIG_SENSORS_EMC1403 is not set
+# CONFIG_SENSORS_EMC2103 is not set
+# CONFIG_SENSORS_EMC6W201 is not set
+# CONFIG_SENSORS_SMSC47M1 is not set
+# CONFIG_SENSORS_SMSC47M192 is not set
+# CONFIG_SENSORS_SMSC47B397 is not set
+# CONFIG_SENSORS_STTS751 is not set
+# CONFIG_SENSORS_SMM665 is not set
+# CONFIG_SENSORS_ADC128D818 is not set
+# CONFIG_SENSORS_ADS7828 is not set
+# CONFIG_SENSORS_ADS7871 is not set
+# CONFIG_SENSORS_AMC6821 is not set
+# CONFIG_SENSORS_INA209 is not set
+# CONFIG_SENSORS_INA2XX is not set
+# CONFIG_SENSORS_INA3221 is not set
+# CONFIG_SENSORS_TC74 is not set
+# CONFIG_SENSORS_THMC50 is not set
+# CONFIG_SENSORS_TMP102 is not set
+# CONFIG_SENSORS_TMP103 is not set
+# CONFIG_SENSORS_TMP108 is not set
+# CONFIG_SENSORS_TMP401 is not set
+# CONFIG_SENSORS_TMP421 is not set
+# CONFIG_SENSORS_VIA686A is not set
+# CONFIG_SENSORS_VT1211 is not set
+# CONFIG_SENSORS_VT8231 is not set
+# CONFIG_SENSORS_W83773G is not set
+# CONFIG_SENSORS_W83781D is not set
+# CONFIG_SENSORS_W83791D is not set
+# CONFIG_SENSORS_W83792D is not set
+# CONFIG_SENSORS_W83793 is not set
+# CONFIG_SENSORS_W83795 is not set
+# CONFIG_SENSORS_W83L785TS is not set
+# CONFIG_SENSORS_W83L786NG is not set
+# CONFIG_SENSORS_W83627HF is not set
+# CONFIG_SENSORS_W83627EHF is not set
+# CONFIG_THERMAL is not set
+# CONFIG_WATCHDOG is not set
+CONFIG_SSB_POSSIBLE=y
+# CONFIG_SSB is not set
+CONFIG_BCMA_POSSIBLE=y
+# CONFIG_BCMA is not set
+
+#
+# Multifunction device drivers
+#
+CONFIG_MFD_CORE=y
+# CONFIG_MFD_ACT8945A is not set
+# CONFIG_MFD_SUN4I_GPADC is not set
+# CONFIG_MFD_AS3711 is not set
+# CONFIG_MFD_AS3722 is not set
+# CONFIG_PMIC_ADP5520 is not set
+# CONFIG_MFD_AAT2870_CORE is not set
+# CONFIG_MFD_AT91_USART is not set
+# CONFIG_MFD_ATMEL_FLEXCOM is not set
+# CONFIG_MFD_ATMEL_HLCDC is not set
+# CONFIG_MFD_BCM590XX is not set
+# CONFIG_MFD_BD9571MWV is not set
+# CONFIG_MFD_AXP20X_I2C is not set
+# CONFIG_MFD_MADERA is not set
+# CONFIG_PMIC_DA903X is not set
+# CONFIG_MFD_DA9052_SPI is not set
+# CONFIG_MFD_DA9052_I2C is not set
+# CONFIG_MFD_DA9055 is not set
+# CONFIG_MFD_DA9062 is not set
+# CONFIG_MFD_DA9063 is not set
+# CONFIG_MFD_DA9150 is not set
+# CONFIG_MFD_DLN2 is not set
+# CONFIG_MFD_EXYNOS_LPASS is not set
+# CONFIG_MFD_MC13XXX_SPI is not set
+# CONFIG_MFD_MC13XXX_I2C is not set
+# CONFIG_MFD_MXS_LRADC is not set
+# CONFIG_MFD_MX25_TSADC is not set
+# CONFIG_MFD_HI6421_PMIC is not set
+# CONFIG_MFD_HI655X_PMIC is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_LPC_ICH is not set
+# CONFIG_LPC_SCH is not set
+# CONFIG_MFD_JANZ_CMODIO is not set
+# CONFIG_MFD_KEMPLD is not set
+# CONFIG_MFD_88PM800 is not set
+# CONFIG_MFD_88PM805 is not set
+# CONFIG_MFD_88PM860X is not set
+# CONFIG_MFD_MAX14577 is not set
+# CONFIG_MFD_MAX77620 is not set
+# CONFIG_MFD_MAX77650 is not set
+# CONFIG_MFD_MAX77686 is not set
+# CONFIG_MFD_MAX77693 is not set
+# CONFIG_MFD_MAX77843 is not set
+# CONFIG_MFD_MAX8907 is not set
+# CONFIG_MFD_MAX8925 is not set
+# CONFIG_MFD_MAX8997 is not set
+# CONFIG_MFD_MAX8998 is not set
+# CONFIG_MFD_MT6397 is not set
+# CONFIG_MFD_MENF21BMC is not set
+# CONFIG_EZX_PCAP is not set
+# CONFIG_MFD_CPCAP is not set
+# CONFIG_MFD_VIPERBOARD is not set
+# CONFIG_MFD_RETU is not set
+# CONFIG_MFD_PCF50633 is not set
+# CONFIG_MFD_PM8XXX is not set
+# CONFIG_MFD_RDC321X is not set
+# CONFIG_MFD_RT5033 is not set
+# CONFIG_MFD_RC5T583 is not set
+# CONFIG_MFD_RK808 is not set
+# CONFIG_MFD_RN5T618 is not set
+# CONFIG_MFD_SEC_CORE is not set
+# CONFIG_MFD_SI476X_CORE is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_MFD_SKY81452 is not set
+# CONFIG_MFD_SMSC is not set
+# CONFIG_MFD_SC27XX_PMIC is not set
+# CONFIG_ABX500_CORE is not set
+# CONFIG_MFD_STMPE is not set
+CONFIG_MFD_SUN6I_PRCM=y
+CONFIG_MFD_SYSCON=y
+# CONFIG_MFD_TI_AM335X_TSCADC is not set
+# CONFIG_MFD_LP3943 is not set
+# CONFIG_MFD_LP8788 is not set
+# CONFIG_MFD_TI_LMU is not set
+# CONFIG_MFD_PALMAS is not set
+# CONFIG_TPS6105X is not set
+# CONFIG_TPS6507X is not set
+# CONFIG_MFD_TPS65086 is not set
+# CONFIG_MFD_TPS65090 is not set
+# CONFIG_MFD_TPS65217 is not set
+# CONFIG_MFD_TI_LP873X is not set
+# CONFIG_MFD_TI_LP87565 is not set
+# CONFIG_MFD_TPS65218 is not set
+# CONFIG_MFD_TPS6586X is not set
+# CONFIG_MFD_TPS65910 is not set
+# CONFIG_MFD_TPS65912_I2C is not set
+# CONFIG_MFD_TPS65912_SPI is not set
+# CONFIG_MFD_TPS80031 is not set
+# CONFIG_TWL4030_CORE is not set
+# CONFIG_TWL6040_CORE is not set
+# CONFIG_MFD_WL1273_CORE is not set
+# CONFIG_MFD_LM3533 is not set
+# CONFIG_MFD_TC3589X is not set
+# CONFIG_MFD_TQMX86 is not set
+# CONFIG_MFD_VX855 is not set
+# CONFIG_MFD_LOCHNAGAR is not set
+# CONFIG_MFD_ARIZONA_I2C is not set
+# CONFIG_MFD_ARIZONA_SPI is not set
+# CONFIG_MFD_WM8400 is not set
+# CONFIG_MFD_WM831X_I2C is not set
+# CONFIG_MFD_WM831X_SPI is not set
+# CONFIG_MFD_WM8350_I2C is not set
+# CONFIG_MFD_WM8994 is not set
+# CONFIG_MFD_STW481X is not set
+# CONFIG_MFD_ROHM_BD718XX is not set
+# CONFIG_MFD_ROHM_BD70528 is not set
+# CONFIG_MFD_STM32_LPTIMER is not set
+# CONFIG_MFD_STM32_TIMERS is not set
+# CONFIG_MFD_STPMIC1 is not set
+# CONFIG_MFD_STMFX is not set
+# end of Multifunction device drivers
+
+# CONFIG_REGULATOR is not set
+# CONFIG_RC_CORE is not set
+# CONFIG_MEDIA_SUPPORT is not set
+
+#
+# Graphics support
+#
+CONFIG_VGA_ARB=y
+CONFIG_VGA_ARB_MAX_GPUS=16
+# CONFIG_IMX_IPUV3_CORE is not set
+CONFIG_DRM=y
+# CONFIG_DRM_DP_AUX_CHARDEV is not set
+# CONFIG_DRM_DEBUG_MM is not set
+# CONFIG_DRM_DEBUG_SELFTEST is not set
+CONFIG_DRM_KMS_HELPER=y
+CONFIG_DRM_KMS_FB_HELPER=y
+CONFIG_DRM_FBDEV_EMULATION=y
+CONFIG_DRM_FBDEV_OVERALLOC=100
+# CONFIG_DRM_FBDEV_LEAK_PHYS_SMEM is not set
+# CONFIG_DRM_LOAD_EDID_FIRMWARE is not set
+# CONFIG_DRM_DP_CEC is not set
+CONFIG_DRM_TTM=y
+
+#
+# I2C encoder or helper chips
+#
+# CONFIG_DRM_I2C_CH7006 is not set
+# CONFIG_DRM_I2C_SIL164 is not set
+# CONFIG_DRM_I2C_NXP_TDA998X is not set
+# CONFIG_DRM_I2C_NXP_TDA9950 is not set
+# end of I2C encoder or helper chips
+
+#
+# ARM devices
+#
+# CONFIG_DRM_KOMEDA is not set
+# end of ARM devices
+
+CONFIG_DRM_RADEON=y
+# CONFIG_DRM_RADEON_USERPTR is not set
+# CONFIG_DRM_AMDGPU is not set
+
+#
+# ACP (Audio CoProcessor) Configuration
+#
+# end of ACP (Audio CoProcessor) Configuration
+
+# CONFIG_DRM_NOUVEAU is not set
+# CONFIG_DRM_VGEM is not set
+# CONFIG_DRM_VKMS is not set
+# CONFIG_DRM_EXYNOS is not set
+# CONFIG_DRM_UDL is not set
+# CONFIG_DRM_AST is not set
+# CONFIG_DRM_MGAG200 is not set
+# CONFIG_DRM_CIRRUS_QEMU is not set
+# CONFIG_DRM_RCAR_DW_HDMI is not set
+# CONFIG_DRM_RCAR_LVDS is not set
+# CONFIG_DRM_QXL is not set
+# CONFIG_DRM_BOCHS is not set
+CONFIG_DRM_VIRTIO_GPU=y
+CONFIG_DRM_PANEL=y
+
+#
+# Display Panels
+#
+# CONFIG_DRM_PANEL_ARM_VERSATILE is not set
+# CONFIG_DRM_PANEL_LVDS is not set
+# CONFIG_DRM_PANEL_SIMPLE is not set
+# CONFIG_DRM_PANEL_ILITEK_IL9322 is not set
+# CONFIG_DRM_PANEL_SAMSUNG_LD9040 is not set
+# CONFIG_DRM_PANEL_LG_LG4573 is not set
+# CONFIG_DRM_PANEL_NOVATEK_NT39016 is not set
+# CONFIG_DRM_PANEL_OLIMEX_LCD_OLINUXINO is not set
+# CONFIG_DRM_PANEL_SAMSUNG_S6E63M0 is not set
+# CONFIG_DRM_PANEL_SAMSUNG_S6E8AA0 is not set
+# CONFIG_DRM_PANEL_SEIKO_43WVF1G is not set
+# CONFIG_DRM_PANEL_SITRONIX_ST7789V is not set
+# CONFIG_DRM_PANEL_TPO_TD028TTEC1 is not set
+# end of Display Panels
+
+CONFIG_DRM_BRIDGE=y
+CONFIG_DRM_PANEL_BRIDGE=y
+
+#
+# Display Interface Bridges
+#
+# CONFIG_DRM_ANALOGIX_ANX78XX is not set
+# CONFIG_DRM_CDNS_DSI is not set
+# CONFIG_DRM_DUMB_VGA_DAC is not set
+# CONFIG_DRM_LVDS_ENCODER is not set
+# CONFIG_DRM_MEGACHIPS_STDPXXXX_GE_B850V3_FW is not set
+# CONFIG_DRM_NXP_PTN3460 is not set
+# CONFIG_DRM_PARADE_PS8622 is not set
+# CONFIG_DRM_SIL_SII8620 is not set
+# CONFIG_DRM_SII902X is not set
+# CONFIG_DRM_SII9234 is not set
+# CONFIG_DRM_THINE_THC63LVD1024 is not set
+# CONFIG_DRM_TOSHIBA_TC358764 is not set
+# CONFIG_DRM_TOSHIBA_TC358767 is not set
+# CONFIG_DRM_TI_TFP410 is not set
+# CONFIG_DRM_TI_SN65DSI86 is not set
+# CONFIG_DRM_I2C_ADV7511 is not set
+# end of Display Interface Bridges
+
+# CONFIG_DRM_V3D is not set
+# CONFIG_DRM_ETNAVIV is not set
+# CONFIG_DRM_ARCPGU is not set
+# CONFIG_DRM_MXSFB is not set
+# CONFIG_DRM_GM12U320 is not set
+# CONFIG_TINYDRM_HX8357D is not set
+# CONFIG_TINYDRM_ILI9225 is not set
+# CONFIG_TINYDRM_ILI9341 is not set
+# CONFIG_TINYDRM_MI0283QT is not set
+# CONFIG_TINYDRM_REPAPER is not set
+# CONFIG_TINYDRM_ST7586 is not set
+# CONFIG_TINYDRM_ST7735R is not set
+# CONFIG_DRM_PL111 is not set
+# CONFIG_DRM_LIMA is not set
+# CONFIG_DRM_PANFROST is not set
+# CONFIG_DRM_ASPEED_GFX is not set
+# CONFIG_DRM_LEGACY is not set
+CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y
+
+#
+# Frame buffer Devices
+#
+CONFIG_FB_CMDLINE=y
+CONFIG_FB_NOTIFY=y
+CONFIG_FB=y
+# CONFIG_FIRMWARE_EDID is not set
+CONFIG_FB_CFB_FILLRECT=y
+CONFIG_FB_CFB_COPYAREA=y
+CONFIG_FB_CFB_IMAGEBLIT=y
+CONFIG_FB_SYS_FILLRECT=y
+CONFIG_FB_SYS_COPYAREA=y
+CONFIG_FB_SYS_IMAGEBLIT=y
+# CONFIG_FB_FOREIGN_ENDIAN is not set
+CONFIG_FB_SYS_FOPS=y
+CONFIG_FB_DEFERRED_IO=y
+# CONFIG_FB_MODE_HELPERS is not set
+# CONFIG_FB_TILEBLITTING is not set
+
+#
+# Frame buffer hardware drivers
+#
+# CONFIG_FB_CIRRUS is not set
+# CONFIG_FB_PM2 is not set
+# CONFIG_FB_CLPS711X is not set
+# CONFIG_FB_IMX is not set
+# CONFIG_FB_CYBER2000 is not set
+# CONFIG_FB_ASILIANT is not set
+# CONFIG_FB_IMSTT is not set
+# CONFIG_FB_GBE is not set
+# CONFIG_FB_PVR2 is not set
+# CONFIG_FB_OPENCORES is not set
+# CONFIG_FB_S1D13XXX is not set
+# CONFIG_FB_ATMEL is not set
+# CONFIG_FB_NVIDIA is not set
+# CONFIG_FB_RIVA is not set
+# CONFIG_FB_I740 is not set
+# CONFIG_FB_MATROX is not set
+# CONFIG_FB_RADEON is not set
+# CONFIG_FB_ATY128 is not set
+# CONFIG_FB_ATY is not set
+# CONFIG_FB_S3 is not set
+# CONFIG_FB_SAVAGE is not set
+# CONFIG_FB_SIS is not set
+# CONFIG_FB_NEOMAGIC is not set
+# CONFIG_FB_KYRO is not set
+# CONFIG_FB_3DFX is not set
+# CONFIG_FB_VOODOO1 is not set
+# CONFIG_FB_VT8623 is not set
+# CONFIG_FB_TRIDENT is not set
+# CONFIG_FB_ARK is not set
+# CONFIG_FB_PM3 is not set
+# CONFIG_FB_CARMINE is not set
+# CONFIG_FB_PXA168 is not set
+# CONFIG_FB_TMIO is not set
+# CONFIG_FB_S3C is not set
+# CONFIG_FB_SMSCUFX is not set
+# CONFIG_FB_UDL is not set
+# CONFIG_FB_IBM_GXT4500 is not set
+# CONFIG_FB_GOLDFISH is not set
+# CONFIG_FB_DA8XX is not set
+# CONFIG_FB_VIRTUAL is not set
+# CONFIG_FB_METRONOME is not set
+# CONFIG_FB_MB862XX is not set
+# CONFIG_FB_BROADSHEET is not set
+# CONFIG_FB_SIMPLE is not set
+# CONFIG_FB_SSD1307 is not set
+# CONFIG_FB_SM712 is not set
+# end of Frame buffer Devices
+
+#
+# Backlight & LCD device support
+#
+# CONFIG_LCD_CLASS_DEVICE is not set
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
+CONFIG_BACKLIGHT_GENERIC=y
+# CONFIG_BACKLIGHT_PM8941_WLED is not set
+# CONFIG_BACKLIGHT_ADP8860 is not set
+# CONFIG_BACKLIGHT_ADP8870 is not set
+# CONFIG_BACKLIGHT_LM3639 is not set
+# CONFIG_BACKLIGHT_GPIO is not set
+# CONFIG_BACKLIGHT_LV5207LP is not set
+# CONFIG_BACKLIGHT_BD6107 is not set
+# CONFIG_BACKLIGHT_ARCXCNN is not set
+# end of Backlight & LCD device support
+
+CONFIG_HDMI=y
+
+#
+# Console display driver support
+#
+CONFIG_VGA_CONSOLE=y
+# CONFIG_VGACON_SOFT_SCROLLBACK is not set
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_DUMMY_CONSOLE_COLUMNS=80
+CONFIG_DUMMY_CONSOLE_ROWS=25
+CONFIG_FRAMEBUFFER_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
+# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
+# CONFIG_FRAMEBUFFER_CONSOLE_DEFERRED_TAKEOVER is not set
+# end of Console display driver support
+
+# CONFIG_LOGO is not set
+# end of Graphics support
+
+# CONFIG_SOUND is not set
+
+#
+# HID support
+#
+CONFIG_HID=y
+# CONFIG_HID_BATTERY_STRENGTH is not set
+# CONFIG_HIDRAW is not set
+# CONFIG_UHID is not set
+CONFIG_HID_GENERIC=y
+
+#
+# Special HID drivers
+#
+# CONFIG_HID_A4TECH is not set
+# CONFIG_HID_ACCUTOUCH is not set
+# CONFIG_HID_ACRUX is not set
+# CONFIG_HID_APPLE is not set
+# CONFIG_HID_APPLEIR is not set
+# CONFIG_HID_AUREAL is not set
+# CONFIG_HID_BELKIN is not set
+# CONFIG_HID_BETOP_FF is not set
+# CONFIG_HID_CHERRY is not set
+# CONFIG_HID_CHICONY is not set
+# CONFIG_HID_COUGAR is not set
+# CONFIG_HID_MACALLY is not set
+# CONFIG_HID_CMEDIA is not set
+# CONFIG_HID_CREATIVE_SB0540 is not set
+# CONFIG_HID_CYPRESS is not set
+# CONFIG_HID_DRAGONRISE is not set
+# CONFIG_HID_EMS_FF is not set
+# CONFIG_HID_ELECOM is not set
+# CONFIG_HID_ELO is not set
+# CONFIG_HID_EZKEY is not set
+# CONFIG_HID_GEMBIRD is not set
+# CONFIG_HID_GFRM is not set
+# CONFIG_HID_HOLTEK is not set
+# CONFIG_HID_KEYTOUCH is not set
+# CONFIG_HID_KYE is not set
+# CONFIG_HID_UCLOGIC is not set
+# CONFIG_HID_WALTOP is not set
+# CONFIG_HID_VIEWSONIC is not set
+# CONFIG_HID_GYRATION is not set
+# CONFIG_HID_ICADE is not set
+# CONFIG_HID_ITE is not set
+# CONFIG_HID_JABRA is not set
+# CONFIG_HID_TWINHAN is not set
+# CONFIG_HID_KENSINGTON is not set
+# CONFIG_HID_LCPOWER is not set
+# CONFIG_HID_LENOVO is not set
+# CONFIG_HID_LOGITECH is not set
+# CONFIG_HID_MAGICMOUSE is not set
+# CONFIG_HID_MALTRON is not set
+# CONFIG_HID_MAYFLASH is not set
+# CONFIG_HID_REDRAGON is not set
+# CONFIG_HID_MICROSOFT is not set
+# CONFIG_HID_MONTEREY is not set
+# CONFIG_HID_MULTITOUCH is not set
+# CONFIG_HID_NTI is not set
+# CONFIG_HID_NTRIG is not set
+# CONFIG_HID_ORTEK is not set
+# CONFIG_HID_PANTHERLORD is not set
+# CONFIG_HID_PENMOUNT is not set
+# CONFIG_HID_PETALYNX is not set
+# CONFIG_HID_PICOLCD is not set
+# CONFIG_HID_PLANTRONICS is not set
+# CONFIG_HID_PRIMAX is not set
+# CONFIG_HID_RETRODE is not set
+# CONFIG_HID_ROCCAT is not set
+# CONFIG_HID_SAITEK is not set
+# CONFIG_HID_SAMSUNG is not set
+# CONFIG_HID_SPEEDLINK is not set
+# CONFIG_HID_STEAM is not set
+# CONFIG_HID_STEELSERIES is not set
+# CONFIG_HID_SUNPLUS is not set
+# CONFIG_HID_RMI is not set
+# CONFIG_HID_GREENASIA is not set
+# CONFIG_HID_SMARTJOYPLUS is not set
+# CONFIG_HID_TIVO is not set
+# CONFIG_HID_TOPSEED is not set
+# CONFIG_HID_THRUSTMASTER is not set
+# CONFIG_HID_UDRAW_PS3 is not set
+# CONFIG_HID_WACOM is not set
+# CONFIG_HID_XINMO is not set
+# CONFIG_HID_ZEROPLUS is not set
+# CONFIG_HID_ZYDACRON is not set
+# CONFIG_HID_SENSOR_HUB is not set
+# CONFIG_HID_ALPS is not set
+# end of Special HID drivers
+
+#
+# USB HID support
+#
+CONFIG_USB_HID=y
+# CONFIG_HID_PID is not set
+# CONFIG_USB_HIDDEV is not set
+# end of USB HID support
+
+#
+# I2C HID support
+#
+# CONFIG_I2C_HID is not set
+# end of I2C HID support
+
+#
+# Intel ISH HID support
+#
+# CONFIG_INTEL_ISH_HID is not set
+# end of Intel ISH HID support
+# end of HID support
+
+CONFIG_USB_OHCI_LITTLE_ENDIAN=y
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_COMMON=y
+# CONFIG_USB_ULPI_BUS is not set
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB=y
+CONFIG_USB_PCI=y
+# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
+
+#
+# Miscellaneous USB options
+#
+CONFIG_USB_DEFAULT_PERSIST=y
+# CONFIG_USB_DYNAMIC_MINORS is not set
+# CONFIG_USB_OTG_WHITELIST is not set
+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
+CONFIG_USB_AUTOSUSPEND_DELAY=2
+# CONFIG_USB_MON is not set
+
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_C67X00_HCD is not set
+CONFIG_USB_XHCI_HCD=y
+# CONFIG_USB_XHCI_DBGCAP is not set
+CONFIG_USB_XHCI_PCI=y
+CONFIG_USB_XHCI_PLATFORM=y
+# CONFIG_USB_XHCI_HISTB is not set
+# CONFIG_USB_XHCI_MTK is not set
+# CONFIG_USB_XHCI_MVEBU is not set
+# CONFIG_USB_XHCI_RCAR is not set
+CONFIG_USB_EHCI_HCD=y
+# CONFIG_USB_EHCI_ROOT_HUB_TT is not set
+CONFIG_USB_EHCI_TT_NEWSCHED=y
+CONFIG_USB_EHCI_PCI=y
+# CONFIG_USB_EHCI_FSL is not set
+# CONFIG_USB_EHCI_HCD_NPCM7XX is not set
+CONFIG_USB_EHCI_HCD_PLATFORM=y
+# CONFIG_USB_OXU210HP_HCD is not set
+# CONFIG_USB_ISP116X_HCD is not set
+# CONFIG_USB_ISP1362_HCD is not set
+# CONFIG_USB_FOTG210_HCD is not set
+# CONFIG_USB_MAX3421_HCD is not set
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_HCD_PCI=y
+CONFIG_USB_OHCI_HCD_PLATFORM=y
+# CONFIG_USB_UHCI_HCD is not set
+# CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
+# CONFIG_USB_HCD_TEST_MODE is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+# CONFIG_USB_WDM is not set
+# CONFIG_USB_TMC is not set
+
+#
+# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
+#
+
+#
+# also be needed; see USB_STORAGE Help for more info
+#
+CONFIG_USB_STORAGE=y
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_REALTEK is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_USBAT is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_SDDR55 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_STORAGE_ALAUDA is not set
+# CONFIG_USB_STORAGE_ONETOUCH is not set
+# CONFIG_USB_STORAGE_KARMA is not set
+# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
+# CONFIG_USB_STORAGE_ENE_UB6250 is not set
+CONFIG_USB_UAS=y
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_MICROTEK is not set
+# CONFIG_USBIP_CORE is not set
+# CONFIG_USB_CDNS3 is not set
+# CONFIG_USB_MTU3 is not set
+# CONFIG_USB_MUSB_HDRC is not set
+# CONFIG_USB_DWC3 is not set
+# CONFIG_USB_DWC2 is not set
+# CONFIG_USB_CHIPIDEA is not set
+# CONFIG_USB_ISP1760 is not set
+
+#
+# USB port drivers
+#
+# CONFIG_USB_SERIAL is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_EMI62 is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_ADUTUX is not set
+# CONFIG_USB_SEVSEG is not set
+# CONFIG_USB_LEGOTOWER is not set
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
+# CONFIG_USB_SISUSBVGA is not set
+# CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
+# CONFIG_USB_TEST is not set
+# CONFIG_USB_EHSET_TEST_FIXTURE is not set
+# CONFIG_USB_ISIGHTFW is not set
+# CONFIG_USB_YUREX is not set
+# CONFIG_USB_EZUSB_FX2 is not set
+# CONFIG_USB_HUB_USB251XB is not set
+# CONFIG_USB_HSIC_USB3503 is not set
+# CONFIG_USB_HSIC_USB4604 is not set
+# CONFIG_USB_LINK_LAYER_TEST is not set
+# CONFIG_USB_CHAOSKEY is not set
+
+#
+# USB Physical Layer drivers
+#
+# CONFIG_NOP_USB_XCEIV is not set
+# CONFIG_USB_GPIO_VBUS is not set
+# CONFIG_USB_ISP1301 is not set
+# end of USB Physical Layer drivers
+
+# CONFIG_USB_GADGET is not set
+# CONFIG_TYPEC is not set
+# CONFIG_USB_ROLE_SWITCH is not set
+CONFIG_MMC=y
+CONFIG_PWRSEQ_EMMC=y
+CONFIG_PWRSEQ_SIMPLE=y
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_BLOCK_MINORS=8
+# CONFIG_SDIO_UART is not set
+# CONFIG_MMC_TEST is not set
+
+#
+# MMC/SD/SDIO Host Controller Drivers
+#
+CONFIG_MMC_DEBUG=y
+# CONFIG_MMC_SDHCI is not set
+# CONFIG_MMC_MESON_MX_SDIO is not set
+# CONFIG_MMC_OMAP_HS is not set
+# CONFIG_MMC_TIFM_SD is not set
+# CONFIG_MMC_GOLDFISH is not set
+CONFIG_MMC_SPI=y
+# CONFIG_MMC_SDHI is not set
+# CONFIG_MMC_UNIPHIER is not set
+# CONFIG_MMC_CB710 is not set
+# CONFIG_MMC_VIA_SDMMC is not set
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_PLTFM=y
+# CONFIG_MMC_DW_BLUEFIELD is not set
+# CONFIG_MMC_DW_EXYNOS is not set
+# CONFIG_MMC_DW_HI3798CV200 is not set
+# CONFIG_MMC_DW_K3 is not set
+# CONFIG_MMC_DW_PCI is not set
+# CONFIG_MMC_SH_MMCIF is not set
+# CONFIG_MMC_VUB300 is not set
+# CONFIG_MMC_USHC is not set
+# CONFIG_MMC_USDHI6ROL0 is not set
+# CONFIG_MMC_CQHCI is not set
+# CONFIG_MMC_TOSHIBA_PCI is not set
+# CONFIG_MMC_BCM2835 is not set
+# CONFIG_MMC_MTK is not set
+# CONFIG_MEMSTICK is not set
+# CONFIG_NEW_LEDS is not set
+# CONFIG_ACCESSIBILITY is not set
+# CONFIG_INFINIBAND is not set
+CONFIG_EDAC_SUPPORT=y
+# CONFIG_EDAC is not set
+# CONFIG_RTC_CLASS is not set
+CONFIG_DMADEVICES=y
+# CONFIG_DMADEVICES_DEBUG is not set
+
+#
+# DMA Devices
+#
+CONFIG_DMA_ENGINE=y
+CONFIG_DMA_VIRTUAL_CHANNELS=y
+CONFIG_DMA_OF=y
+# CONFIG_ALTERA_MSGDMA is not set
+# CONFIG_AXI_DMAC is not set
+# CONFIG_COH901318 is not set
+# CONFIG_DMA_JZ4780 is not set
+# CONFIG_DMA_SA11X0 is not set
+# CONFIG_DMA_SUN6I is not set
+CONFIG_DW_AXI_DMAC=y
+# CONFIG_EP93XX_DMA is not set
+# CONFIG_FSL_EDMA is not set
+# CONFIG_IMG_MDC_DMA is not set
+# CONFIG_INTEL_IDMA64 is not set
+# CONFIG_INTEL_IOP_ADMA is not set
+# CONFIG_K3_DMA is not set
+# CONFIG_MCF_EDMA is not set
+# CONFIG_MMP_PDMA is not set
+# CONFIG_MMP_TDMA is not set
+# CONFIG_MV_XOR is not set
+# CONFIG_MXS_DMA is not set
+# CONFIG_NBPFAXI_DMA is not set
+# CONFIG_PCH_DMA is not set
+# CONFIG_STM32_DMA is not set
+# CONFIG_STM32_DMAMUX is not set
+# CONFIG_STM32_MDMA is not set
+# CONFIG_SPRD_DMA is not set
+# CONFIG_S3C24XX_DMAC is not set
+# CONFIG_TEGRA210_ADMA is not set
+# CONFIG_TIMB_DMA is not set
+# CONFIG_UNIPHIER_MDMAC is not set
+# CONFIG_XGENE_DMA is not set
+# CONFIG_ZX_DMA is not set
+# CONFIG_MTK_HSDMA is not set
+# CONFIG_MTK_CQDMA is not set
+# CONFIG_QCOM_HIDMA_MGMT is not set
+# CONFIG_QCOM_HIDMA is not set
+CONFIG_DW_DMAC_CORE=y
+# CONFIG_DW_DMAC is not set
+# CONFIG_DW_DMAC_PCI is not set
+# CONFIG_DW_EDMA is not set
+# CONFIG_DW_EDMA_PCIE is not set
+CONFIG_HSU_DMA=y
+CONFIG_RENESAS_DMA=y
+CONFIG_SH_DMAE_BASE=y
+# CONFIG_SH_DMAE is not set
+# CONFIG_RCAR_DMAC is not set
+# CONFIG_RENESAS_USB_DMAC is not set
+CONFIG_TI_EDMA=y
+CONFIG_DMA_OMAP=y
+CONFIG_TI_DMA_CROSSBAR=y
+
+#
+# DMA Clients
+#
+# CONFIG_ASYNC_TX_DMA is not set
+CONFIG_DMATEST=y
+CONFIG_DMA_ENGINE_RAID=y
+
+#
+# DMABUF options
+#
+CONFIG_SYNC_FILE=y
+# CONFIG_SW_SYNC is not set
+# CONFIG_UDMABUF is not set
+# CONFIG_DMABUF_SELFTESTS is not set
+# end of DMABUF options
+
+# CONFIG_AUXDISPLAY is not set
+# CONFIG_CHARLCD is not set
+# CONFIG_UIO is not set
+# CONFIG_VIRT_DRIVERS is not set
+CONFIG_VIRTIO=y
+CONFIG_VIRTIO_MENU=y
+CONFIG_VIRTIO_PCI=y
+CONFIG_VIRTIO_PCI_LEGACY=y
+CONFIG_VIRTIO_BALLOON=y
+CONFIG_VIRTIO_INPUT=y
+CONFIG_VIRTIO_MMIO=y
+# CONFIG_VIRTIO_MMIO_CMDLINE_DEVICES is not set
+
+#
+# Microsoft Hyper-V guest support
+#
+# end of Microsoft Hyper-V guest support
+
+# CONFIG_GREYBUS is not set
+# CONFIG_STAGING is not set
+# CONFIG_MFD_CROS_EC is not set
+# CONFIG_CHROME_PLATFORMS is not set
+# CONFIG_MELLANOX_PLATFORM is not set
+# CONFIG_OLPC_XO175 is not set
+CONFIG_CLKDEV_LOOKUP=y
+CONFIG_HAVE_CLK_PREPARE=y
+CONFIG_COMMON_CLK=y
+
+#
+# Common Clock Framework
+#
+# CONFIG_COMMON_CLK_VERSATILE is not set
+# CONFIG_CLK_HSDK is not set
+# CONFIG_COMMON_CLK_MAX77686 is not set
+# CONFIG_COMMON_CLK_MAX9485 is not set
+# CONFIG_COMMON_CLK_HI655X is not set
+# CONFIG_COMMON_CLK_SCMI is not set
+# CONFIG_COMMON_CLK_SCPI is not set
+# CONFIG_COMMON_CLK_SI5341 is not set
+# CONFIG_COMMON_CLK_SI5351 is not set
+# CONFIG_COMMON_CLK_SI514 is not set
+# CONFIG_COMMON_CLK_SI544 is not set
+# CONFIG_COMMON_CLK_SI570 is not set
+# CONFIG_COMMON_CLK_CDCE706 is not set
+# CONFIG_COMMON_CLK_CDCE925 is not set
+# CONFIG_COMMON_CLK_CS2000_CP is not set
+# CONFIG_COMMON_CLK_GEMINI is not set
+# CONFIG_COMMON_CLK_ASPEED is not set
+# CONFIG_COMMON_CLK_S2MPS11 is not set
+# CONFIG_COMMON_CLK_AXI_CLKGEN is not set
+# CONFIG_CLK_QORIQ is not set
+# CONFIG_COMMON_CLK_XGENE is not set
+# CONFIG_COMMON_CLK_OXNAS is not set
+# CONFIG_COMMON_CLK_VC5 is not set
+# CONFIG_COMMON_CLK_FIXED_MMIO is not set
+# CONFIG_CLK_ACTIONS is not set
+CONFIG_CLK_ANALOGBITS_WRPLL_CLN28HPC=y
+# CONFIG_CLK_BCM2835 is not set
+# CONFIG_CLK_BCM_63XX is not set
+# CONFIG_CLK_BCM_63XX_GATE is not set
+# CONFIG_CLK_BCM_KONA is not set
+# CONFIG_CLK_BCM_CYGNUS is not set
+# CONFIG_CLK_BCM_HR2 is not set
+# CONFIG_CLK_BCM_NSP is not set
+# CONFIG_CLK_BCM_NS2 is not set
+# CONFIG_CLK_BCM_SR is not set
+# CONFIG_CLK_RASPBERRYPI is not set
+# CONFIG_COMMON_CLK_HI3516CV300 is not set
+# CONFIG_COMMON_CLK_HI3519 is not set
+# CONFIG_COMMON_CLK_HI3660 is not set
+# CONFIG_COMMON_CLK_HI3670 is not set
+# CONFIG_COMMON_CLK_HI3798CV200 is not set
+# CONFIG_COMMON_CLK_HI6220 is not set
+# CONFIG_RESET_HISI is not set
+# CONFIG_COMMON_CLK_BOSTON is not set
+# CONFIG_COMMON_CLK_KEYSTONE is not set
+
+#
+# Clock driver for MediaTek SoC
+#
+# CONFIG_COMMON_CLK_MT2701 is not set
+# CONFIG_COMMON_CLK_MT2712 is not set
+# CONFIG_COMMON_CLK_MT6779 is not set
+# CONFIG_COMMON_CLK_MT6797 is not set
+# CONFIG_COMMON_CLK_MT7622 is not set
+# CONFIG_COMMON_CLK_MT7629 is not set
+# CONFIG_COMMON_CLK_MT8135 is not set
+# CONFIG_COMMON_CLK_MT8173 is not set
+# CONFIG_COMMON_CLK_MT8183 is not set
+# CONFIG_COMMON_CLK_MT8516 is not set
+# end of Clock driver for MediaTek SoC
+
+# CONFIG_COMMON_CLK_QCOM is not set
+# CONFIG_CLK_RENESAS is not set
+# CONFIG_COMMON_CLK_SAMSUNG is not set
+# CONFIG_S3C2410_COMMON_CLK is not set
+# CONFIG_S3C2412_COMMON_CLK is not set
+# CONFIG_S3C2443_COMMON_CLK is not set
+CONFIG_CLK_SIFIVE=y
+CONFIG_CLK_SIFIVE_FU540_PRCI=y
+# CONFIG_SPRD_COMMON_CLK is not set
+CONFIG_CLK_SUNXI=y
+CONFIG_CLK_SUNXI_CLOCKS=y
+CONFIG_CLK_SUNXI_PRCM_SUN6I=y
+CONFIG_CLK_SUNXI_PRCM_SUN8I=y
+CONFIG_CLK_SUNXI_PRCM_SUN9I=y
+# CONFIG_SUNXI_CCU is not set
+# CONFIG_COMMON_CLK_TI_ADPLL is not set
+# CONFIG_CLK_UNIPHIER is not set
+# end of Common Clock Framework
+
+# CONFIG_HWSPINLOCK is not set
+
+#
+# Clock Source drivers
+#
+CONFIG_TIMER_OF=y
+CONFIG_TIMER_PROBE=y
+# CONFIG_BCM2835_TIMER is not set
+# CONFIG_BCM_KONA_TIMER is not set
+# CONFIG_DAVINCI_TIMER is not set
+# CONFIG_DIGICOLOR_TIMER is not set
+# CONFIG_DW_APB_TIMER is not set
+# CONFIG_FTTMR010_TIMER is not set
+# CONFIG_IXP4XX_TIMER is not set
+# CONFIG_MESON6_TIMER is not set
+# CONFIG_OWL_TIMER is not set
+# CONFIG_RDA_TIMER is not set
+# CONFIG_SUN4I_TIMER is not set
+# CONFIG_SUN5I_HSTIMER is not set
+# CONFIG_TEGRA_TIMER is not set
+# CONFIG_VT8500_TIMER is not set
+# CONFIG_NPCM7XX_TIMER is not set
+# CONFIG_CADENCE_TTC_TIMER is not set
+# CONFIG_ASM9260_TIMER is not set
+# CONFIG_CLKSRC_DBX500_PRCMU is not set
+# CONFIG_CLPS711X_TIMER is not set
+# CONFIG_ATLAS7_TIMER is not set
+# CONFIG_MXS_TIMER is not set
+# CONFIG_PRIMA2_TIMER is not set
+# CONFIG_NSPIRE_TIMER is not set
+# CONFIG_INTEGRATOR_AP_TIMER is not set
+# CONFIG_CLKSRC_PISTACHIO is not set
+# CONFIG_CLKSRC_TI_32K is not set
+# CONFIG_CLKSRC_MPS2 is not set
+# CONFIG_ARC_TIMERS is not set
+# CONFIG_ARM_TIMER_SP804 is not set
+# CONFIG_ARMV7M_SYSTICK is not set
+# CONFIG_ATMEL_PIT is not set
+# CONFIG_ATMEL_ST is not set
+# CONFIG_CLKSRC_SAMSUNG_PWM is not set
+# CONFIG_FSL_FTM_TIMER is not set
+# CONFIG_OXNAS_RPS_TIMER is not set
+# CONFIG_MTK_TIMER is not set
+# CONFIG_SPRD_TIMER is not set
+# CONFIG_CLKSRC_JCORE_PIT is not set
+# CONFIG_SH_TIMER_CMT is not set
+# CONFIG_SH_TIMER_MTU2 is not set
+# CONFIG_RENESAS_OSTM is not set
+# CONFIG_SH_TIMER_TMU is not set
+# CONFIG_EM_TIMER_STI is not set
+# CONFIG_CLKSRC_VERSATILE is not set
+# CONFIG_CLKSRC_PXA is not set
+# CONFIG_H8300_TMR8 is not set
+# CONFIG_H8300_TMR16 is not set
+# CONFIG_H8300_TPU is not set
+# CONFIG_TIMER_IMX_SYS_CTR is not set
+# CONFIG_CLKSRC_ST_LPC is not set
+# CONFIG_ATCPIT100_TIMER is not set
+CONFIG_RISCV_TIMER=y
+# CONFIG_INGENIC_TIMER is not set
+# end of Clock Source drivers
+
+# CONFIG_MAILBOX is not set
+CONFIG_IOMMU_SUPPORT=y
+
+#
+# Generic IOMMU Pagetable Support
+#
+# CONFIG_IOMMU_IO_PGTABLE_LPAE is not set
+# CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set
+# end of Generic IOMMU Pagetable Support
+
+# CONFIG_IOMMU_DEBUGFS is not set
+# CONFIG_QCOM_IOMMU is not set
+
+#
+# Remoteproc drivers
+#
+# CONFIG_REMOTEPROC is not set
+# end of Remoteproc drivers
+
+#
+# Rpmsg drivers
+#
+CONFIG_RPMSG=y
+CONFIG_RPMSG_CHAR=y
+CONFIG_RPMSG_VIRTIO=y
+# end of Rpmsg drivers
+
+# CONFIG_SOUNDWIRE is not set
+
+#
+# SOC (System On Chip) specific Drivers
+#
+
+#
+# Amlogic SoC drivers
+#
+# CONFIG_MESON_CANVAS is not set
+# CONFIG_MESON_CLK_MEASURE is not set
+# CONFIG_MESON_GX_SOCINFO is not set
+# CONFIG_MESON_MX_SOCINFO is not set
+# end of Amlogic SoC drivers
+
+#
+# Aspeed SoC drivers
+#
+CONFIG_SOC_ASPEED=y
+# CONFIG_ASPEED_LPC_CTRL is not set
+# CONFIG_ASPEED_LPC_SNOOP is not set
+# CONFIG_ASPEED_P2A_CTRL is not set
+# end of Aspeed SoC drivers
+
+# CONFIG_AT91_SOC_ID is not set
+
+#
+# Broadcom SoC drivers
+#
+# CONFIG_BCM2835_POWER is not set
+# CONFIG_SOC_BRCMSTB is not set
+# end of Broadcom SoC drivers
+
+#
+# NXP/Freescale QorIQ SoC drivers
+#
+CONFIG_DPAA2_CONSOLE=y
+# end of NXP/Freescale QorIQ SoC drivers
+
+#
+# i.MX SoC drivers
+#
+# end of i.MX SoC drivers
+
+#
+# IXP4xx SoC drivers
+#
+# CONFIG_IXP4XX_QMGR is not set
+# CONFIG_IXP4XX_NPE is not set
+# end of IXP4xx SoC drivers
+
+#
+# MediaTek SoC drivers
+#
+# CONFIG_MTK_CMDQ is not set
+# CONFIG_MTK_INFRACFG is not set
+# CONFIG_MTK_PMIC_WRAP is not set
+# CONFIG_MTK_SCPSYS is not set
+# end of MediaTek SoC drivers
+
+#
+# Qualcomm SoC drivers
+#
+# CONFIG_QCOM_COMMAND_DB is not set
+# CONFIG_QCOM_GENI_SE is not set
+# CONFIG_QCOM_GSBI is not set
+# CONFIG_QCOM_LLCC is not set
+# CONFIG_QCOM_RPMH is not set
+# CONFIG_QCOM_SMD_RPM is not set
+# CONFIG_QCOM_WCNSS_CTRL is not set
+# CONFIG_QCOM_APR is not set
+# end of Qualcomm SoC drivers
+
+# CONFIG_SOC_RENESAS is not set
+CONFIG_ROCKCHIP_GRF=y
+# CONFIG_SOC_SAMSUNG is not set
+# CONFIG_SOC_TI is not set
+# CONFIG_UX500_SOC_ID is not set
+
+#
+# Xilinx SoC drivers
+#
+# CONFIG_XILINX_VCU is not set
+# end of Xilinx SoC drivers
+
+# CONFIG_SOC_ZTE is not set
+# end of SOC (System On Chip) specific Drivers
+
+# CONFIG_PM_DEVFREQ is not set
+# CONFIG_EXTCON is not set
+# CONFIG_MEMORY is not set
+# CONFIG_IIO is not set
+# CONFIG_NTB is not set
+# CONFIG_VME_BUS is not set
+# CONFIG_PWM is not set
+
+#
+# IRQ chip support
+#
+CONFIG_IRQCHIP=y
+# CONFIG_AL_FIC is not set
+# CONFIG_JCORE_AIC is not set
+# CONFIG_RENESAS_INTC_IRQPIN is not set
+# CONFIG_RENESAS_IRQC is not set
+# CONFIG_RENESAS_RZA1_IRQC is not set
+# CONFIG_TS4800_IRQ is not set
+# CONFIG_INGENIC_TCU_IRQ is not set
+# CONFIG_RENESAS_H8S_INTC is not set
+# CONFIG_IRQ_UNIPHIER_AIDET is not set
+# CONFIG_IMX_IRQSTEER is not set
+CONFIG_SIFIVE_PLIC=y
+# end of IRQ chip support
+
+# CONFIG_IPACK_BUS is not set
+CONFIG_RESET_CONTROLLER=y
+# CONFIG_RESET_ATH79 is not set
+# CONFIG_RESET_AXS10X is not set
+# CONFIG_RESET_BERLIN is not set
+# CONFIG_RESET_BRCMSTB is not set
+# CONFIG_RESET_HSDK is not set
+# CONFIG_RESET_IMX7 is not set
+# CONFIG_RESET_LANTIQ is not set
+# CONFIG_RESET_LPC18XX is not set
+# CONFIG_RESET_MESON is not set
+# CONFIG_RESET_MESON_AUDIO_ARB is not set
+# CONFIG_RESET_PISTACHIO is not set
+# CONFIG_RESET_QCOM_AOSS is not set
+# CONFIG_RESET_QCOM_PDC is not set
+# CONFIG_RESET_SCMI is not set
+# CONFIG_RESET_SIMPLE is not set
+# CONFIG_RESET_STM32MP157 is not set
+# CONFIG_RESET_SOCFPGA is not set
+# CONFIG_RESET_SUNXI is not set
+# CONFIG_RESET_TI_SYSCON is not set
+# CONFIG_RESET_UNIPHIER is not set
+# CONFIG_RESET_UNIPHIER_GLUE is not set
+# CONFIG_RESET_ZYNQ is not set
+# CONFIG_COMMON_RESET_HI3660 is not set
+# CONFIG_COMMON_RESET_HI6220 is not set
+
+#
+# PHY Subsystem
+#
+CONFIG_GENERIC_PHY=y
+# CONFIG_PHY_LPC18XX_USB_OTG is not set
+# CONFIG_PHY_XGENE is not set
+# CONFIG_PHY_SUN6I_MIPI_DPHY is not set
+# CONFIG_PHY_SUN9I_USB is not set
+# CONFIG_PHY_MESON8B_USB2 is not set
+# CONFIG_PHY_MESON_GXL_USB2 is not set
+# CONFIG_PHY_MESON_GXL_USB3 is not set
+# CONFIG_PHY_MESON_G12A_USB2 is not set
+# CONFIG_PHY_MESON_G12A_USB3_PCIE is not set
+# CONFIG_PHY_CYGNUS_PCIE is not set
+# CONFIG_PHY_BCM_SR_USB is not set
+# CONFIG_BCM_KONA_USB2_PHY is not set
+# CONFIG_PHY_BCM_NS_USB2 is not set
+# CONFIG_PHY_BCM_NS_USB3 is not set
+# CONFIG_PHY_NS2_USB_DRD is not set
+# CONFIG_PHY_BRCM_SATA is not set
+# CONFIG_PHY_BCM_SR_PCIE is not set
+# CONFIG_PHY_CADENCE_DP is not set
+# CONFIG_PHY_CADENCE_DPHY is not set
+# CONFIG_PHY_CADENCE_SIERRA is not set
+# CONFIG_PHY_FSL_IMX8MQ_USB is not set
+# CONFIG_PHY_MIXEL_MIPI_DPHY is not set
+# CONFIG_PHY_HI6220_USB is not set
+# CONFIG_PHY_HI3660_USB is not set
+# CONFIG_PHY_HISTB_COMBPHY is not set
+# CONFIG_PHY_HISI_INNO_USB2 is not set
+# CONFIG_PHY_LANTIQ_VRX200_PCIE is not set
+# CONFIG_PHY_LANTIQ_RCU_USB2 is not set
+CONFIG_ARMADA375_USBCLUSTER_PHY=y
+CONFIG_PHY_MVEBU_A3700_UTMI=y
+# CONFIG_PHY_MVEBU_A38X_COMPHY is not set
+# CONFIG_PHY_PXA_28NM_HSIC is not set
+# CONFIG_PHY_PXA_28NM_USB2 is not set
+# CONFIG_PHY_OCELOT_SERDES is not set
+CONFIG_PHY_ATH79_USB=y
+# CONFIG_PHY_QCOM_PCIE2 is not set
+# CONFIG_PHY_QCOM_QMP is not set
+# CONFIG_PHY_QCOM_QUSB2 is not set
+# CONFIG_PHY_RALINK_USB is not set
+# CONFIG_PHY_RCAR_GEN3_USB3 is not set
+# CONFIG_PHY_ROCKCHIP_INNO_HDMI is not set
+# CONFIG_PHY_ROCKCHIP_PCIE is not set
+# CONFIG_PHY_ROCKCHIP_TYPEC is not set
+# CONFIG_PHY_EXYNOS_DP_VIDEO is not set
+# CONFIG_PHY_EXYNOS_MIPI_VIDEO is not set
+# CONFIG_PHY_EXYNOS_PCIE is not set
+# CONFIG_PHY_UNIPHIER_USB2 is not set
+# CONFIG_PHY_UNIPHIER_USB3 is not set
+# CONFIG_PHY_UNIPHIER_PCIE is not set
+# CONFIG_PHY_ST_SPEAR1310_MIPHY is not set
+# CONFIG_PHY_ST_SPEAR1340_MIPHY is not set
+# CONFIG_PHY_STIH407_USB is not set
+# CONFIG_PHY_STM32_USBPHYC is not set
+# CONFIG_PHY_TEGRA194_P2U is not set
+# CONFIG_PHY_AM654_SERDES is not set
+# CONFIG_OMAP_CONTROL_PHY is not set
+# CONFIG_TI_PIPE3 is not set
+CONFIG_PHY_TI_GMII_SEL=m
+# end of PHY Subsystem
+
+# CONFIG_POWERCAP is not set
+# CONFIG_MCB is not set
+
+#
+# Performance monitor support
+#
+CONFIG_THEAD_XT_V1_PMU=y
+# end of Performance monitor support
+
+CONFIG_RAS=y
+# CONFIG_THUNDERBOLT is not set
+
+#
+# Android
+#
+# CONFIG_ANDROID is not set
+# end of Android
+
+# CONFIG_LIBNVDIMM is not set
+# CONFIG_DAX is not set
+# CONFIG_NVMEM is not set
+
+#
+# HW tracing support
+#
+# CONFIG_STM is not set
+# CONFIG_INTEL_TH is not set
+# end of HW tracing support
+
+# CONFIG_FPGA is not set
+# CONFIG_FSI is not set
+# CONFIG_TEE is not set
+# CONFIG_SIOX is not set
+# CONFIG_SLIMBUS is not set
+# CONFIG_INTERCONNECT is not set
+# CONFIG_COUNTER is not set
+# end of Device Drivers
+
+#
+# File systems
+#
+# CONFIG_VALIDATE_FS_PARSER is not set
+CONFIG_FS_IOMAP=y
+# CONFIG_EXT2_FS is not set
+# CONFIG_EXT3_FS is not set
+CONFIG_EXT4_FS=y
+CONFIG_EXT4_USE_FOR_EXT2=y
+CONFIG_EXT4_FS_POSIX_ACL=y
+# CONFIG_EXT4_FS_SECURITY is not set
+# CONFIG_EXT4_DEBUG is not set
+CONFIG_JBD2=y
+# CONFIG_JBD2_DEBUG is not set
+CONFIG_FS_MBCACHE=y
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_BTRFS_FS is not set
+# CONFIG_NILFS2_FS is not set
+# CONFIG_F2FS_FS is not set
+# CONFIG_FS_DAX is not set
+CONFIG_FS_POSIX_ACL=y
+CONFIG_EXPORTFS=y
+# CONFIG_EXPORTFS_BLOCK_OPS is not set
+CONFIG_FILE_LOCKING=y
+CONFIG_MANDATORY_FILE_LOCKING=y
+# CONFIG_FS_ENCRYPTION is not set
+# CONFIG_FS_VERITY is not set
+CONFIG_FSNOTIFY=y
+CONFIG_DNOTIFY=y
+CONFIG_INOTIFY_USER=y
+# CONFIG_FANOTIFY is not set
+# CONFIG_QUOTA is not set
+CONFIG_AUTOFS4_FS=y
+CONFIG_AUTOFS_FS=y
+CONFIG_FUSE_FS=y
+# CONFIG_CUSE is not set
+# CONFIG_VIRTIO_FS is not set
+# CONFIG_OVERLAY_FS is not set
+
+#
+# Caches
+#
+# CONFIG_FSCACHE is not set
+# end of Caches
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+# end of CD-ROM/DVD Filesystems
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+# CONFIG_FAT_DEFAULT_UTF8 is not set
+# CONFIG_NTFS_FS is not set
+# end of DOS/FAT/NT Filesystems
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+# CONFIG_PROC_KCORE is not set
+CONFIG_PROC_SYSCTL=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_PROC_CHILDREN=y
+CONFIG_KERNFS=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+CONFIG_TMPFS_POSIX_ACL=y
+CONFIG_TMPFS_XATTR=y
+# CONFIG_HUGETLBFS is not set
+CONFIG_MEMFD_CREATE=y
+CONFIG_ARCH_HAS_GIGANTIC_PAGE=y
+# CONFIG_CONFIGFS_FS is not set
+# end of Pseudo filesystems
+
+CONFIG_MISC_FILESYSTEMS=y
+# CONFIG_ORANGEFS_FS is not set
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_ECRYPT_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_SQUASHFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_QNX6FS_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_PSTORE is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+# CONFIG_EROFS_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V2=y
+CONFIG_NFS_V3=y
+# CONFIG_NFS_V3_ACL is not set
+CONFIG_NFS_V4=y
+# CONFIG_NFS_SWAP is not set
+CONFIG_NFS_V4_1=y
+CONFIG_NFS_V4_2=y
+CONFIG_PNFS_FILE_LAYOUT=y
+CONFIG_PNFS_FLEXFILE_LAYOUT=m
+CONFIG_NFS_V4_1_IMPLEMENTATION_ID_DOMAIN="kernel.org"
+# CONFIG_NFS_V4_1_MIGRATION is not set
+CONFIG_ROOT_NFS=y
+# CONFIG_NFS_USE_LEGACY_DNS is not set
+CONFIG_NFS_USE_KERNEL_DNS=y
+# CONFIG_NFSD is not set
+CONFIG_GRACE_PERIOD=y
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+CONFIG_SUNRPC_GSS=y
+CONFIG_SUNRPC_BACKCHANNEL=y
+# CONFIG_SUNRPC_DEBUG is not set
+# CONFIG_CEPH_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+CONFIG_9P_FS=y
+CONFIG_9P_FS_POSIX_ACL=y
+CONFIG_9P_FS_SECURITY=y
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8859-1"
+# CONFIG_NLS_CODEPAGE_437 is not set
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ASCII is not set
+# CONFIG_NLS_ISO8859_1 is not set
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+# CONFIG_NLS_MAC_ROMAN is not set
+# CONFIG_NLS_MAC_CELTIC is not set
+# CONFIG_NLS_MAC_CENTEURO is not set
+# CONFIG_NLS_MAC_CROATIAN is not set
+# CONFIG_NLS_MAC_CYRILLIC is not set
+# CONFIG_NLS_MAC_GAELIC is not set
+# CONFIG_NLS_MAC_GREEK is not set
+# CONFIG_NLS_MAC_ICELAND is not set
+# CONFIG_NLS_MAC_INUIT is not set
+# CONFIG_NLS_MAC_ROMANIAN is not set
+# CONFIG_NLS_MAC_TURKISH is not set
+# CONFIG_NLS_UTF8 is not set
+# CONFIG_UNICODE is not set
+# end of File systems
+
+#
+# Security options
+#
+CONFIG_KEYS=y
+# CONFIG_KEYS_REQUEST_CACHE is not set
+# CONFIG_PERSISTENT_KEYRINGS is not set
+# CONFIG_BIG_KEYS is not set
+# CONFIG_ENCRYPTED_KEYS is not set
+# CONFIG_KEY_DH_OPERATIONS is not set
+# CONFIG_SECURITY_DMESG_RESTRICT is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITYFS is not set
+CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y
+# CONFIG_HARDENED_USERCOPY is not set
+# CONFIG_STATIC_USERMODEHELPER is not set
+CONFIG_DEFAULT_SECURITY_DAC=y
+CONFIG_LSM="lockdown,yama,loadpin,safesetid,integrity"
+
+#
+# Kernel hardening options
+#
+
+#
+# Memory initialization
+#
+CONFIG_INIT_STACK_NONE=y
+# CONFIG_INIT_ON_ALLOC_DEFAULT_ON is not set
+# CONFIG_INIT_ON_FREE_DEFAULT_ON is not set
+# end of Memory initialization
+# end of Kernel hardening options
+# end of Security options
+
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_ALGAPI2=y
+CONFIG_CRYPTO_AEAD=y
+CONFIG_CRYPTO_AEAD2=y
+CONFIG_CRYPTO_BLKCIPHER=y
+CONFIG_CRYPTO_BLKCIPHER2=y
+CONFIG_CRYPTO_HASH=y
+CONFIG_CRYPTO_HASH2=y
+CONFIG_CRYPTO_RNG2=y
+# CONFIG_CRYPTO_MANAGER is not set
+# CONFIG_CRYPTO_USER is not set
+# CONFIG_CRYPTO_NULL is not set
+CONFIG_CRYPTO_NULL2=y
+# CONFIG_CRYPTO_PCRYPT is not set
+# CONFIG_CRYPTO_CRYPTD is not set
+# CONFIG_CRYPTO_AUTHENC is not set
+# CONFIG_CRYPTO_TEST is not set
+CONFIG_CRYPTO_ENGINE=y
+
+#
+# Public-key cryptography
+#
+# CONFIG_CRYPTO_RSA is not set
+# CONFIG_CRYPTO_DH is not set
+# CONFIG_CRYPTO_ECDH is not set
+# CONFIG_CRYPTO_ECRDSA is not set
+
+#
+# Authenticated Encryption with Associated Data
+#
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_CHACHA20POLY1305 is not set
+# CONFIG_CRYPTO_AEGIS128 is not set
+# CONFIG_CRYPTO_SEQIV is not set
+# CONFIG_CRYPTO_ECHAINIV is not set
+
+#
+# Block modes
+#
+# CONFIG_CRYPTO_CBC is not set
+# CONFIG_CRYPTO_CFB is not set
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_CTS is not set
+# CONFIG_CRYPTO_ECB is not set
+# CONFIG_CRYPTO_LRW is not set
+# CONFIG_CRYPTO_OFB is not set
+# CONFIG_CRYPTO_PCBC is not set
+# CONFIG_CRYPTO_XTS is not set
+# CONFIG_CRYPTO_KEYWRAP is not set
+# CONFIG_CRYPTO_ADIANTUM is not set
+# CONFIG_CRYPTO_ESSIV is not set
+
+#
+# Hash modes
+#
+# CONFIG_CRYPTO_CMAC is not set
+# CONFIG_CRYPTO_HMAC is not set
+# CONFIG_CRYPTO_XCBC is not set
+# CONFIG_CRYPTO_VMAC is not set
+
+#
+# Digest
+#
+CONFIG_CRYPTO_CRC32C=y
+# CONFIG_CRYPTO_CRC32 is not set
+# CONFIG_CRYPTO_XXHASH is not set
+# CONFIG_CRYPTO_CRCT10DIF is not set
+# CONFIG_CRYPTO_GHASH is not set
+# CONFIG_CRYPTO_POLY1305 is not set
+# CONFIG_CRYPTO_MD4 is not set
+# CONFIG_CRYPTO_MD5 is not set
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_RMD128 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+# CONFIG_CRYPTO_RMD256 is not set
+# CONFIG_CRYPTO_RMD320 is not set
+# CONFIG_CRYPTO_SHA1 is not set
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_SHA3 is not set
+# CONFIG_CRYPTO_SM3 is not set
+# CONFIG_CRYPTO_STREEBOG is not set
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_WP512 is not set
+
+#
+# Ciphers
+#
+# CONFIG_CRYPTO_AES is not set
+# CONFIG_CRYPTO_AES_TI is not set
+# CONFIG_CRYPTO_ANUBIS is not set
+# CONFIG_CRYPTO_ARC4 is not set
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+# CONFIG_CRYPTO_DES is not set
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_SALSA20 is not set
+# CONFIG_CRYPTO_CHACHA20 is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_SM4 is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+
+#
+# Compression
+#
+# CONFIG_CRYPTO_DEFLATE is not set
+# CONFIG_CRYPTO_LZO is not set
+# CONFIG_CRYPTO_842 is not set
+# CONFIG_CRYPTO_LZ4 is not set
+# CONFIG_CRYPTO_LZ4HC is not set
+# CONFIG_CRYPTO_ZSTD is not set
+
+#
+# Random Number Generation
+#
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
+# CONFIG_CRYPTO_DRBG_MENU is not set
+# CONFIG_CRYPTO_JITTERENTROPY is not set
+CONFIG_CRYPTO_USER_API=y
+CONFIG_CRYPTO_USER_API_HASH=y
+# CONFIG_CRYPTO_USER_API_SKCIPHER is not set
+# CONFIG_CRYPTO_USER_API_RNG is not set
+# CONFIG_CRYPTO_USER_API_AEAD is not set
+CONFIG_CRYPTO_HW=y
+# CONFIG_CRYPTO_DEV_PICOXCELL is not set
+# CONFIG_CRYPTO_DEV_EXYNOS_RNG is not set
+# CONFIG_CRYPTO_DEV_S5P is not set
+# CONFIG_CRYPTO_DEV_ATMEL_AUTHENC is not set
+# CONFIG_CRYPTO_DEV_ATMEL_AES is not set
+# CONFIG_CRYPTO_DEV_ATMEL_TDES is not set
+# CONFIG_CRYPTO_DEV_ATMEL_SHA is not set
+# CONFIG_CRYPTO_DEV_ATMEL_ECC is not set
+# CONFIG_CRYPTO_DEV_ATMEL_SHA204A is not set
+# CONFIG_CAVIUM_CPT is not set
+# CONFIG_CRYPTO_DEV_NITROX_CNN55XX is not set
+# CONFIG_CRYPTO_DEV_CAVIUM_ZIP is not set
+# CONFIG_CRYPTO_DEV_QCE is not set
+# CONFIG_CRYPTO_DEV_QCOM_RNG is not set
+# CONFIG_CRYPTO_DEV_IMGTEC_HASH is not set
+# CONFIG_CRYPTO_DEV_MEDIATEK is not set
+CONFIG_CRYPTO_DEV_VIRTIO=y
+# CONFIG_CRYPTO_DEV_SAFEXCEL is not set
+# CONFIG_CRYPTO_DEV_CCREE is not set
+# CONFIG_CRYPTO_DEV_HISI_SEC is not set
+# CONFIG_ASYMMETRIC_KEY_TYPE is not set
+
+#
+# Certificates for signature checking
+#
+# CONFIG_SYSTEM_BLACKLIST_KEYRING is not set
+# end of Certificates for signature checking
+
+#
+# Library routines
+#
+# CONFIG_PACKING is not set
+CONFIG_BITREVERSE=y
+CONFIG_GENERIC_STRNCPY_FROM_USER=y
+CONFIG_GENERIC_STRNLEN_USER=y
+CONFIG_GENERIC_NET_UTILS=y
+# CONFIG_CORDIC is not set
+CONFIG_RATIONAL=y
+CONFIG_GENERIC_PCI_IOMAP=y
+# CONFIG_CRC_CCITT is not set
+CONFIG_CRC16=y
+# CONFIG_CRC_T10DIF is not set
+CONFIG_CRC_ITU_T=y
+CONFIG_CRC32=y
+# CONFIG_CRC32_SELFTEST is not set
+CONFIG_CRC32_SLICEBY8=y
+# CONFIG_CRC32_SLICEBY4 is not set
+# CONFIG_CRC32_SARWATE is not set
+# CONFIG_CRC32_BIT is not set
+# CONFIG_CRC64 is not set
+# CONFIG_CRC4 is not set
+CONFIG_CRC7=y
+# CONFIG_LIBCRC32C is not set
+# CONFIG_CRC8 is not set
+# CONFIG_RANDOM32_SELFTEST is not set
+CONFIG_ZLIB_INFLATE=y
+CONFIG_LZO_DECOMPRESS=y
+CONFIG_LZ4_DECOMPRESS=y
+CONFIG_XZ_DEC=y
+CONFIG_XZ_DEC_X86=y
+CONFIG_XZ_DEC_POWERPC=y
+CONFIG_XZ_DEC_IA64=y
+CONFIG_XZ_DEC_ARM=y
+CONFIG_XZ_DEC_ARMTHUMB=y
+CONFIG_XZ_DEC_SPARC=y
+CONFIG_XZ_DEC_BCJ=y
+# CONFIG_XZ_DEC_TEST is not set
+CONFIG_DECOMPRESS_GZIP=y
+CONFIG_DECOMPRESS_BZIP2=y
+CONFIG_DECOMPRESS_LZMA=y
+CONFIG_DECOMPRESS_XZ=y
+CONFIG_DECOMPRESS_LZO=y
+CONFIG_DECOMPRESS_LZ4=y
+CONFIG_GENERIC_ALLOCATOR=y
+CONFIG_INTERVAL_TREE=y
+CONFIG_ASSOCIATIVE_ARRAY=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT_MAP=y
+CONFIG_HAS_DMA=y
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_ARCH_DMA_ADDR_T_64BIT=y
+CONFIG_ARCH_HAS_DMA_WRITE_COMBINE=y
+CONFIG_DMA_DECLARE_COHERENT=y
+CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE=y
+CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU=y
+CONFIG_ARCH_HAS_DMA_PREP_COHERENT=y
+CONFIG_SWIOTLB=y
+CONFIG_DMA_REMAP=y
+CONFIG_DMA_DIRECT_REMAP=y
+# CONFIG_DMA_API_DEBUG is not set
+CONFIG_CPU_RMAP=y
+CONFIG_DQL=y
+CONFIG_GLOB=y
+# CONFIG_GLOB_SELFTEST is not set
+CONFIG_NLATTR=y
+# CONFIG_IRQ_POLL is not set
+CONFIG_LIBFDT=y
+CONFIG_OID_REGISTRY=y
+CONFIG_FONT_SUPPORT=y
+# CONFIG_FONTS is not set
+CONFIG_FONT_8x8=y
+CONFIG_FONT_8x16=y
+CONFIG_SG_POOL=y
+CONFIG_SBITMAP=y
+# CONFIG_PARMAN is not set
+# CONFIG_OBJAGG is not set
+# CONFIG_STRING_SELFTEST is not set
+# end of Library routines
+
+#
+# Kernel hacking
+#
+
+#
+# printk and dmesg options
+#
+CONFIG_PRINTK_TIME=y
+# CONFIG_PRINTK_CALLER is not set
+CONFIG_CONSOLE_LOGLEVEL_DEFAULT=7
+CONFIG_CONSOLE_LOGLEVEL_QUIET=4
+CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4
+# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_DYNAMIC_DEBUG is not set
+# end of printk and dmesg options
+
+#
+# Compile-time checks and compiler options
+#
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=2048
+# CONFIG_STRIP_ASM_SYMS is not set
+# CONFIG_READABLE_ASM is not set
+CONFIG_DEBUG_FS=y
+# CONFIG_HEADERS_INSTALL is not set
+CONFIG_OPTIMIZE_INLINING=y
+# CONFIG_DEBUG_SECTION_MISMATCH is not set
+CONFIG_SECTION_MISMATCH_WARN_ONLY=y
+CONFIG_ARCH_WANT_FRAME_POINTERS=y
+CONFIG_FRAME_POINTER=y
+# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
+# end of Compile-time checks and compiler options
+
+# CONFIG_MAGIC_SYSRQ is not set
+CONFIG_DEBUG_KERNEL=y
+CONFIG_DEBUG_MISC=y
+
+#
+# Memory Debugging
+#
+# CONFIG_PAGE_EXTENSION is not set
+# CONFIG_DEBUG_PAGEALLOC is not set
+# CONFIG_PAGE_OWNER is not set
+# CONFIG_PAGE_POISONING is not set
+# CONFIG_DEBUG_OBJECTS is not set
+# CONFIG_SLUB_DEBUG_ON is not set
+# CONFIG_SLUB_STATS is not set
+# CONFIG_DEBUG_STACK_USAGE is not set
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
+# CONFIG_DEBUG_PER_CPU_MAPS is not set
+CONFIG_CC_HAS_KASAN_GENERIC=y
+CONFIG_KASAN_STACK=1
+# end of Memory Debugging
+
+CONFIG_CC_HAS_SANCOV_TRACE_PC=y
+# CONFIG_DEBUG_SHIRQ is not set
+
+#
+# Debug Lockups and Hangs
+#
+# CONFIG_SOFTLOCKUP_DETECTOR is not set
+CONFIG_DETECT_HUNG_TASK=y
+CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=60
+# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
+CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
+# CONFIG_WQ_WATCHDOG is not set
+# end of Debug Lockups and Hangs
+
+# CONFIG_PANIC_ON_OOPS is not set
+CONFIG_PANIC_ON_OOPS_VALUE=0
+CONFIG_PANIC_TIMEOUT=0
+CONFIG_SCHED_DEBUG=y
+# CONFIG_SCHEDSTATS is not set
+# CONFIG_SCHED_STACK_END_CHECK is not set
+# CONFIG_DEBUG_TIMEKEEPING is not set
+
+#
+# Lock Debugging (spinlocks, mutexes, etc...)
+#
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_RWSEMS is not set
+CONFIG_DEBUG_ATOMIC_SLEEP=y
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_LOCK_TORTURE_TEST is not set
+# CONFIG_WW_MUTEX_SELFTEST is not set
+# end of Lock Debugging (spinlocks, mutexes, etc...)
+
+# CONFIG_STACKTRACE is not set
+# CONFIG_WARN_ALL_UNSEEDED_RANDOM is not set
+# CONFIG_DEBUG_KOBJECT is not set
+CONFIG_DEBUG_BUGVERBOSE=y
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_PLIST is not set
+# CONFIG_DEBUG_SG is not set
+# CONFIG_DEBUG_NOTIFIERS is not set
+# CONFIG_DEBUG_CREDENTIALS is not set
+
+#
+# RCU Debugging
+#
+# CONFIG_RCU_PERF_TEST is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+CONFIG_RCU_CPU_STALL_TIMEOUT=21
+# CONFIG_RCU_TRACE is not set
+# CONFIG_RCU_EQS_DEBUG is not set
+# end of RCU Debugging
+
+# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set
+# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
+# CONFIG_NOTIFIER_ERROR_INJECTION is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_LATENCYTOP is not set
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
+CONFIG_HAVE_DYNAMIC_FTRACE=y
+CONFIG_HAVE_DYNAMIC_FTRACE_WITH_REGS=y
+CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
+CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
+CONFIG_TRACING_SUPPORT=y
+CONFIG_FTRACE=y
+# CONFIG_FUNCTION_TRACER is not set
+# CONFIG_PREEMPTIRQ_EVENTS is not set
+# CONFIG_IRQSOFF_TRACER is not set
+# CONFIG_SCHED_TRACER is not set
+# CONFIG_HWLAT_TRACER is not set
+# CONFIG_ENABLE_DEFAULT_TRACERS is not set
+# CONFIG_FTRACE_SYSCALLS is not set
+# CONFIG_TRACER_SNAPSHOT is not set
+CONFIG_BRANCH_PROFILE_NONE=y
+# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set
+# CONFIG_PROFILE_ALL_BRANCHES is not set
+# CONFIG_STACK_TRACER is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_TRACEPOINT_BENCHMARK is not set
+# CONFIG_PREEMPTIRQ_DELAY_TEST is not set
+CONFIG_RUNTIME_TESTING_MENU=y
+# CONFIG_LKDTM is not set
+# CONFIG_TEST_LIST_SORT is not set
+# CONFIG_TEST_SORT is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_RBTREE_TEST is not set
+# CONFIG_REED_SOLOMON_TEST is not set
+# CONFIG_INTERVAL_TREE_TEST is not set
+# CONFIG_PERCPU_TEST is not set
+# CONFIG_ATOMIC64_SELFTEST is not set
+# CONFIG_TEST_HEXDUMP is not set
+# CONFIG_TEST_STRING_HELPERS is not set
+# CONFIG_TEST_STRSCPY is not set
+# CONFIG_TEST_KSTRTOX is not set
+# CONFIG_TEST_PRINTF is not set
+# CONFIG_TEST_BITMAP is not set
+# CONFIG_TEST_BITFIELD is not set
+# CONFIG_TEST_UUID is not set
+# CONFIG_TEST_XARRAY is not set
+# CONFIG_TEST_OVERFLOW is not set
+# CONFIG_TEST_RHASHTABLE is not set
+# CONFIG_TEST_HASH is not set
+# CONFIG_TEST_IDA is not set
+# CONFIG_TEST_LKM is not set
+# CONFIG_TEST_VMALLOC is not set
+# CONFIG_TEST_USER_COPY is not set
+# CONFIG_TEST_BPF is not set
+# CONFIG_TEST_BLACKHOLE_DEV is not set
+# CONFIG_FIND_BIT_BENCHMARK is not set
+# CONFIG_TEST_FIRMWARE is not set
+# CONFIG_TEST_SYSCTL is not set
+# CONFIG_TEST_UDELAY is not set
+# CONFIG_TEST_STATIC_KEYS is not set
+# CONFIG_TEST_KMOD is not set
+# CONFIG_TEST_MEMCAT_P is not set
+# CONFIG_TEST_STACKINIT is not set
+# CONFIG_TEST_MEMINIT is not set
+# CONFIG_MEMTEST is not set
+# CONFIG_BUG_ON_DATA_CORRUPTION is not set
+# CONFIG_SAMPLES is not set
+# CONFIG_UBSAN is not set
+CONFIG_UBSAN_ALIGNMENT=y
+# end of Kernel hacking
+
+# CONFIG_WARN_MISSING_DOCUMENTS is not set

+ 989 - 0
recipes-kernel/linux/files/xuantie-c910/xuantie-c910_defconfig

@@ -0,0 +1,989 @@
+CONFIG_SYSVIPC=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_FHANDLE=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_CGROUPS=y
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_BSD_PROCESS_ACCT_V3=y
+CONFIG_TASKSTATS=y
+CONFIG_TASK_DELAY_ACCT=y
+CONFIG_TASK_XACCT=y
+CONFIG_TASK_IO_ACCOUNTING=y
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_SCHED_AUTOGROUP=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_BPF_SYSCALL=y
+CONFIG_PERF_EVENTS=y
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_BLK_DEV_BSGLIB=y
+CONFIG_BLK_DEV_INTEGRITY=y
+CONFIG_PARTITION_ADVANCED=y
+CONFIG_MAC_PARTITION=y
+CONFIG_LDM_PARTITION=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_SMP=y
+CONFIG_NR_CPUS=8
+CONFIG_AEABI=y
+CONFIG_HIGHMEM=y
+CONFIG_HIGHPTE=y
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_ARM_APPENDED_DTB=y
+CONFIG_ARM_ATAG_DTB_COMPAT=y
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_FREQ_STAT=y
+CONFIG_CPU_FREQ_STAT_DETAILS=y
+CONFIG_CPU_FREQ_GOV_POWERSAVE=y
+CONFIG_CPU_FREQ_GOV_USERSPACE=y
+CONFIG_CPU_FREQ_GOV_ONDEMAND=y
+CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
+CONFIG_CPUFREQ_DT=m
+CONFIG_CPU_IDLE=y
+CONFIG_ARM_CPUIDLE=y
+CONFIG_VFP=y
+CONFIG_NEON=y
+CONFIG_KERNEL_MODE_NEON=y
+CONFIG_HIBERNATION=y
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_PACKET_DIAG=m
+CONFIG_UNIX=y
+CONFIG_UNIX_DIAG=m
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_ADVANCED_ROUTER=y
+CONFIG_IP_FIB_TRIE_STATS=y
+CONFIG_IP_MULTIPLE_TABLES=y
+CONFIG_IP_ROUTE_MULTIPATH=y
+CONFIG_IP_ROUTE_VERBOSE=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_NET_IPIP=m
+CONFIG_NET_IPGRE_DEMUX=m
+CONFIG_NET_IPGRE=m
+CONFIG_NET_FOU=m
+CONFIG_INET_AH=m
+CONFIG_INET_ESP=m
+CONFIG_INET_IPCOMP=m
+CONFIG_INET_XFRM_MODE_TRANSPORT=m
+CONFIG_INET_XFRM_MODE_TUNNEL=m
+CONFIG_INET_XFRM_MODE_BEET=m
+CONFIG_INET_LRO=m
+CONFIG_INET_DIAG=m
+CONFIG_INET_UDP_DIAG=m
+CONFIG_TCP_CONG_ADVANCED=y
+CONFIG_TCP_CONG_HSTCP=m
+CONFIG_TCP_CONG_HYBLA=m
+CONFIG_TCP_CONG_SCALABLE=m
+CONFIG_TCP_CONG_LP=m
+CONFIG_TCP_CONG_VENO=m
+CONFIG_TCP_CONG_YEAH=m
+CONFIG_TCP_CONG_ILLINOIS=m
+CONFIG_TCP_CONG_DCTCP=m
+CONFIG_INET6_AH=m
+CONFIG_INET6_ESP=m
+CONFIG_INET6_IPCOMP=m
+CONFIG_IPV6_MIP6=m
+CONFIG_IPV6_VTI=m
+CONFIG_IPV6_GRE=m
+CONFIG_IPV6_MULTIPLE_TABLES=y
+CONFIG_IPV6_SUBTREES=y
+CONFIG_IPV6_MROUTE=y
+CONFIG_IPV6_MROUTE_MULTIPLE_TABLES=y
+CONFIG_IPV6_PIMSM_V2=y
+CONFIG_NETFILTER=y
+CONFIG_NF_CONNTRACK=m
+CONFIG_NF_CONNTRACK_EVENTS=y
+CONFIG_NF_CONNTRACK_TIMEOUT=y
+CONFIG_NF_CONNTRACK_TIMESTAMP=y
+CONFIG_NF_CT_PROTO_DCCP=m
+CONFIG_NF_CT_PROTO_SCTP=m
+CONFIG_NF_CT_PROTO_UDPLITE=m
+CONFIG_NF_CONNTRACK_AMANDA=m
+CONFIG_NF_CONNTRACK_FTP=m
+CONFIG_NF_CONNTRACK_H323=m
+CONFIG_NF_CONNTRACK_IRC=m
+CONFIG_NF_CONNTRACK_NETBIOS_NS=m
+CONFIG_NF_CONNTRACK_SNMP=m
+CONFIG_NF_CONNTRACK_PPTP=m
+CONFIG_NF_CONNTRACK_SANE=m
+CONFIG_NF_CONNTRACK_SIP=m
+CONFIG_NF_CONNTRACK_TFTP=m
+CONFIG_NF_CT_NETLINK=m
+CONFIG_NF_CT_NETLINK_TIMEOUT=m
+CONFIG_NF_CT_NETLINK_HELPER=m
+CONFIG_NETFILTER_NETLINK_QUEUE_CT=y
+CONFIG_NF_TABLES=m
+CONFIG_NF_TABLES_INET=m
+CONFIG_NFT_EXTHDR=m
+CONFIG_NFT_META=m
+CONFIG_NFT_CT=m
+CONFIG_NFT_RBTREE=m
+CONFIG_NFT_HASH=m
+CONFIG_NFT_COUNTER=m
+CONFIG_NFT_LOG=m
+CONFIG_NFT_LIMIT=m
+CONFIG_NFT_MASQ=m
+CONFIG_NFT_REDIR=m
+CONFIG_NFT_NAT=m
+CONFIG_NFT_QUEUE=m
+CONFIG_NFT_REJECT=m
+CONFIG_NFT_COMPAT=m
+CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
+CONFIG_NETFILTER_XT_TARGET_CONNMARK=m
+CONFIG_NETFILTER_XT_TARGET_HMARK=m
+CONFIG_NETFILTER_XT_TARGET_IDLETIMER=m
+CONFIG_NETFILTER_XT_TARGET_LED=m
+CONFIG_NETFILTER_XT_TARGET_LOG=m
+CONFIG_NETFILTER_XT_TARGET_MARK=m
+CONFIG_NETFILTER_XT_TARGET_NFLOG=m
+CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
+CONFIG_NETFILTER_XT_TARGET_TEE=m
+CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
+CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m
+CONFIG_NETFILTER_XT_MATCH_BPF=m
+CONFIG_NETFILTER_XT_MATCH_CGROUP=m
+CONFIG_NETFILTER_XT_MATCH_CLUSTER=m
+CONFIG_NETFILTER_XT_MATCH_COMMENT=m
+CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m
+CONFIG_NETFILTER_XT_MATCH_CONNLABEL=m
+CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m
+CONFIG_NETFILTER_XT_MATCH_CONNMARK=m
+CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
+CONFIG_NETFILTER_XT_MATCH_CPU=m
+CONFIG_NETFILTER_XT_MATCH_DCCP=m
+CONFIG_NETFILTER_XT_MATCH_DEVGROUP=m
+CONFIG_NETFILTER_XT_MATCH_DSCP=m
+CONFIG_NETFILTER_XT_MATCH_ESP=m
+CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m
+CONFIG_NETFILTER_XT_MATCH_HELPER=m
+CONFIG_NETFILTER_XT_MATCH_IPCOMP=m
+CONFIG_NETFILTER_XT_MATCH_IPRANGE=m
+CONFIG_NETFILTER_XT_MATCH_LENGTH=m
+CONFIG_NETFILTER_XT_MATCH_LIMIT=m
+CONFIG_NETFILTER_XT_MATCH_MAC=m
+CONFIG_NETFILTER_XT_MATCH_MARK=m
+CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
+CONFIG_NETFILTER_XT_MATCH_NFACCT=m
+CONFIG_NETFILTER_XT_MATCH_OSF=m
+CONFIG_NETFILTER_XT_MATCH_OWNER=m
+CONFIG_NETFILTER_XT_MATCH_POLICY=m
+CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
+CONFIG_NETFILTER_XT_MATCH_QUOTA=m
+CONFIG_NETFILTER_XT_MATCH_RATEEST=m
+CONFIG_NETFILTER_XT_MATCH_REALM=m
+CONFIG_NETFILTER_XT_MATCH_RECENT=m
+CONFIG_NETFILTER_XT_MATCH_SCTP=m
+CONFIG_NETFILTER_XT_MATCH_SOCKET=m
+CONFIG_NETFILTER_XT_MATCH_STATE=m
+CONFIG_NETFILTER_XT_MATCH_STATISTIC=m
+CONFIG_NETFILTER_XT_MATCH_STRING=m
+CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
+CONFIG_NETFILTER_XT_MATCH_TIME=m
+CONFIG_NETFILTER_XT_MATCH_U32=m
+CONFIG_IP_VS=m
+CONFIG_IP_VS_IPV6=y
+CONFIG_IP_VS_DEBUG=y
+CONFIG_IP_VS_PROTO_TCP=y
+CONFIG_IP_VS_PROTO_UDP=y
+CONFIG_IP_VS_PROTO_ESP=y
+CONFIG_IP_VS_PROTO_AH=y
+CONFIG_IP_VS_PROTO_SCTP=y
+CONFIG_IP_VS_RR=m
+CONFIG_IP_VS_WRR=m
+CONFIG_IP_VS_LC=m
+CONFIG_IP_VS_WLC=m
+CONFIG_IP_VS_FO=m
+CONFIG_IP_VS_LBLC=m
+CONFIG_IP_VS_LBLCR=m
+CONFIG_IP_VS_DH=m
+CONFIG_IP_VS_SH=m
+CONFIG_IP_VS_SED=m
+CONFIG_IP_VS_NQ=m
+CONFIG_IP_VS_FTP=m
+CONFIG_IP_VS_PE_SIP=m
+CONFIG_NF_CONNTRACK_IPV4=m
+CONFIG_NFT_CHAIN_ROUTE_IPV4=m
+CONFIG_NF_TABLES_ARP=m
+CONFIG_NF_LOG_ARP=m
+CONFIG_NFT_CHAIN_NAT_IPV4=m
+CONFIG_NFT_MASQ_IPV4=m
+CONFIG_NFT_REDIR_IPV4=m
+CONFIG_IP_NF_IPTABLES=m
+CONFIG_IP_NF_MATCH_AH=m
+CONFIG_IP_NF_MATCH_ECN=m
+CONFIG_IP_NF_MATCH_TTL=m
+CONFIG_IP_NF_FILTER=m
+CONFIG_IP_NF_TARGET_REJECT=m
+CONFIG_IP_NF_TARGET_SYNPROXY=m
+CONFIG_IP_NF_NAT=m
+CONFIG_IP_NF_TARGET_MASQUERADE=m
+CONFIG_IP_NF_TARGET_NETMAP=m
+CONFIG_IP_NF_TARGET_REDIRECT=m
+CONFIG_IP_NF_MANGLE=m
+CONFIG_IP_NF_TARGET_CLUSTERIP=m
+CONFIG_IP_NF_TARGET_ECN=m
+CONFIG_IP_NF_TARGET_TTL=m
+CONFIG_IP_NF_RAW=m
+CONFIG_IP_NF_ARPTABLES=m
+CONFIG_IP_NF_ARPFILTER=m
+CONFIG_IP_NF_ARP_MANGLE=m
+CONFIG_NF_CONNTRACK_IPV6=m
+CONFIG_NFT_CHAIN_ROUTE_IPV6=m
+CONFIG_NFT_CHAIN_NAT_IPV6=m
+CONFIG_NFT_MASQ_IPV6=m
+CONFIG_NFT_REDIR_IPV6=m
+CONFIG_IP6_NF_MATCH_AH=m
+CONFIG_IP6_NF_MATCH_EUI64=m
+CONFIG_IP6_NF_MATCH_FRAG=m
+CONFIG_IP6_NF_MATCH_OPTS=m
+CONFIG_IP6_NF_MATCH_HL=m
+CONFIG_IP6_NF_MATCH_IPV6HEADER=m
+CONFIG_IP6_NF_MATCH_MH=m
+CONFIG_IP6_NF_MATCH_RPFILTER=m
+CONFIG_IP6_NF_MATCH_RT=m
+CONFIG_IP6_NF_TARGET_HL=m
+CONFIG_IP6_NF_FILTER=m
+CONFIG_IP6_NF_TARGET_REJECT=m
+CONFIG_IP6_NF_TARGET_SYNPROXY=m
+CONFIG_IP6_NF_MANGLE=m
+CONFIG_IP6_NF_RAW=m
+CONFIG_IP6_NF_NAT=m
+CONFIG_IP6_NF_TARGET_MASQUERADE=m
+CONFIG_IP6_NF_TARGET_NPT=m
+CONFIG_L2TP=m
+CONFIG_BRIDGE=m
+CONFIG_BRIDGE_VLAN_FILTERING=y
+CONFIG_VLAN_8021Q=m
+CONFIG_VLAN_8021Q_GVRP=y
+CONFIG_VLAN_8021Q_MVRP=y
+CONFIG_6LOWPAN=m
+CONFIG_IEEE802154=m
+CONFIG_IEEE802154_6LOWPAN=m
+CONFIG_MAC802154=m
+CONFIG_NET_SCHED=y
+CONFIG_NET_SCH_CBQ=m
+CONFIG_NET_SCH_HTB=y
+CONFIG_NET_SCH_HFSC=m
+CONFIG_NET_SCH_PRIO=m
+CONFIG_NET_SCH_MULTIQ=m
+CONFIG_NET_SCH_RED=m
+CONFIG_NET_SCH_SFB=m
+CONFIG_NET_SCH_SFQ=y
+CONFIG_NET_SCH_TEQL=m
+CONFIG_NET_SCH_TBF=m
+CONFIG_NET_SCH_GRED=m
+CONFIG_NET_SCH_DSMARK=m
+CONFIG_NET_SCH_NETEM=m
+CONFIG_NET_SCH_DRR=m
+CONFIG_NET_SCH_MQPRIO=m
+CONFIG_NET_SCH_CHOKE=m
+CONFIG_NET_SCH_QFQ=m
+CONFIG_NET_SCH_CODEL=m
+CONFIG_NET_SCH_FQ_CODEL=y
+CONFIG_NET_SCH_FQ=m
+CONFIG_NET_SCH_HHF=m
+CONFIG_NET_SCH_PIE=y
+CONFIG_NET_SCH_PLUG=m
+CONFIG_NET_CLS_BASIC=m
+CONFIG_NET_CLS_TCINDEX=m
+CONFIG_NET_CLS_ROUTE4=m
+CONFIG_NET_CLS_FW=m
+CONFIG_NET_CLS_U32=m
+CONFIG_NET_CLS_RSVP=m
+CONFIG_NET_CLS_RSVP6=m
+CONFIG_NET_CLS_FLOW=m
+CONFIG_NET_CLS_CGROUP=m
+CONFIG_NET_CLS_BPF=m
+CONFIG_NET_EMATCH=y
+CONFIG_NET_EMATCH_CMP=m
+CONFIG_NET_EMATCH_NBYTE=m
+CONFIG_NET_EMATCH_U32=m
+CONFIG_NET_EMATCH_META=m
+CONFIG_NET_EMATCH_TEXT=m
+CONFIG_NET_CLS_ACT=y
+CONFIG_NET_ACT_POLICE=m
+CONFIG_NET_ACT_GACT=m
+CONFIG_NET_ACT_MIRRED=m
+CONFIG_NET_ACT_IPT=m
+CONFIG_NET_ACT_NAT=m
+CONFIG_NET_ACT_SIMP=m
+CONFIG_NET_ACT_SKBEDIT=m
+CONFIG_NET_ACT_CSUM=m
+CONFIG_NET_ACT_VLAN=m
+CONFIG_NET_ACT_BPF=m
+CONFIG_NET_ACT_CONNMARK=m
+CONFIG_VSOCKETS=m
+CONFIG_NETLINK_MMAP=y
+CONFIG_NETLINK_DIAG=y
+CONFIG_BPF_JIT=y
+CONFIG_BT=m
+CONFIG_BT_RFCOMM=m
+CONFIG_BT_RFCOMM_TTY=y
+CONFIG_BT_BNEP=m
+CONFIG_BT_BNEP_PROTO_FILTER=y
+CONFIG_BT_HIDP=m
+CONFIG_BT_HCIBTUSB=m
+CONFIG_BT_HCIBTSDIO=m
+CONFIG_BT_HCIUART=m
+CONFIG_BT_HCIUART_BCSP=y
+CONFIG_BT_HCIUART_ATH3K=y
+CONFIG_BT_HCIUART_LL=y
+CONFIG_BT_HCIUART_3WIRE=y
+CONFIG_BT_HCIUART_INTEL=y
+CONFIG_BT_HCIUART_BCM=y
+CONFIG_BT_HCIBCM203X=m
+CONFIG_BT_HCIBPA10X=m
+CONFIG_BT_HCIBFUSB=m
+CONFIG_BT_MRVL=m
+CONFIG_BT_MRVL_SDIO=m
+CONFIG_BT_ATH3K=m
+CONFIG_CFG80211=m
+CONFIG_CFG80211_WEXT=y
+CONFIG_RFKILL=m
+CONFIG_RFKILL_LEDS=y
+CONFIG_RFKILL_INPUT=y
+CONFIG_RFKILL_GPIO=m
+CONFIG_MAC80211=m
+CONFIG_MAC80211_MESH=y
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+CONFIG_BLK_DEV_LOOP=m
+CONFIG_BLK_DEV_LOOP_MIN_COUNT=0
+CONFIG_BLK_DEV_NBD=m
+CONFIG_BLK_DEV_RAM=m
+CONFIG_CDROM_PKTCDVD=m
+CONFIG_CDROM_PKTCDVD_WCACHE=y
+CONFIG_EEPROM_SUNXI_SID=y
+CONFIG_SCSI_MQ_DEFAULT=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_CHR_DEV_SG=y
+CONFIG_ATA=y
+CONFIG_AHCI_SUNXI=y
+CONFIG_MD=y
+CONFIG_MD_LINEAR=m
+CONFIG_MD_RAID0=m
+CONFIG_MD_MULTIPATH=m
+CONFIG_MD_FAULTY=m
+CONFIG_BCACHE=m
+CONFIG_BLK_DEV_DM=m
+CONFIG_DM_MQ_DEFAULT=y
+CONFIG_DM_CRYPT=m
+CONFIG_DM_SNAPSHOT=m
+CONFIG_DM_THIN_PROVISIONING=m
+CONFIG_DM_CACHE=m
+CONFIG_DM_ERA=m
+CONFIG_DM_MIRROR=m
+CONFIG_DM_LOG_USERSPACE=m
+CONFIG_DM_RAID=m
+CONFIG_DM_ZERO=m
+CONFIG_DM_MULTIPATH=m
+CONFIG_DM_MULTIPATH_QL=m
+CONFIG_DM_MULTIPATH_ST=m
+CONFIG_DM_DELAY=m
+CONFIG_DM_UEVENT=y
+CONFIG_DM_FLAKEY=m
+CONFIG_DM_VERITY=m
+CONFIG_DM_SWITCH=m
+CONFIG_DM_LOG_WRITES=m
+CONFIG_NETDEVICES=y
+CONFIG_BONDING=m
+CONFIG_DUMMY=m
+CONFIG_NET_TEAM=m
+CONFIG_NET_TEAM_MODE_BROADCAST=m
+CONFIG_NET_TEAM_MODE_ROUNDROBIN=m
+CONFIG_NET_TEAM_MODE_RANDOM=m
+CONFIG_NET_TEAM_MODE_ACTIVEBACKUP=m
+CONFIG_NET_TEAM_MODE_LOADBALANCE=m
+CONFIG_MACVLAN=m
+CONFIG_MACVTAP=m
+CONFIG_IPVLAN=m
+CONFIG_VXLAN=m
+CONFIG_GTP=m
+CONFIG_TUN=m
+CONFIG_VETH=m
+CONFIG_NLMON=m
+CONFIG_SUN4I_EMAC=y
+# CONFIG_NET_VENDOR_ARC is not set
+# CONFIG_NET_CADENCE is not set
+# CONFIG_NET_VENDOR_BROADCOM is not set
+# CONFIG_NET_VENDOR_CIRRUS is not set
+# CONFIG_NET_VENDOR_FARADAY is not set
+# CONFIG_NET_VENDOR_INTEL is not set
+# CONFIG_NET_VENDOR_MARVELL is not set
+# CONFIG_NET_VENDOR_MICREL is not set
+# CONFIG_NET_VENDOR_MICROCHIP is not set
+# CONFIG_NET_VENDOR_NATSEMI is not set
+# CONFIG_NET_VENDOR_SAMSUNG is not set
+# CONFIG_NET_VENDOR_SEEQ is not set
+# CONFIG_NET_VENDOR_SMSC is not set
+CONFIG_STMMAC_ETH=y
+# CONFIG_NET_VENDOR_VIA is not set
+# CONFIG_NET_VENDOR_WIZNET is not set
+CONFIG_PPP=m
+CONFIG_PPP_BSDCOMP=m
+CONFIG_PPP_DEFLATE=m
+CONFIG_PPP_FILTER=y
+CONFIG_PPP_MPPE=m
+CONFIG_PPP_MULTILINK=y
+CONFIG_PPPOE=m
+CONFIG_PPTP=m
+CONFIG_PPPOL2TP=m
+CONFIG_PPP_ASYNC=m
+CONFIG_PPP_SYNC_TTY=m
+CONFIG_LIBERTAS_THINFIRM=m
+CONFIG_LIBERTAS_THINFIRM_USB=m
+CONFIG_AT76C50X_USB=m
+CONFIG_USB_ZD1201=m
+CONFIG_USB_NET_RNDIS_WLAN=m
+CONFIG_RTL8187=m
+CONFIG_RTL8XXXU=m
+CONFIG_RTL8XXXU_UNTESTED=y
+CONFIG_ATH_CARDS=m
+CONFIG_ATH9K=m
+CONFIG_ATH9K_AHB=y
+CONFIG_ATH9K_CHANNEL_CONTEXT=y
+CONFIG_ATH9K_HTC=m
+CONFIG_CARL9170=m
+CONFIG_ATH6KL=m
+CONFIG_ATH6KL_SDIO=m
+CONFIG_ATH6KL_USB=m
+CONFIG_AR5523=m
+CONFIG_ATH10K=m
+CONFIG_WCN36XX=m
+CONFIG_B43=m
+CONFIG_B43_SDIO=y
+CONFIG_BRCMFMAC=m
+CONFIG_BRCMFMAC_USB=y
+CONFIG_HOSTAP=m
+CONFIG_HOSTAP_FIRMWARE=y
+CONFIG_LIBERTAS=m
+CONFIG_LIBERTAS_USB=m
+CONFIG_LIBERTAS_SDIO=m
+CONFIG_LIBERTAS_SPI=m
+CONFIG_P54_COMMON=m
+CONFIG_P54_USB=m
+CONFIG_P54_SPI=m
+CONFIG_RT2X00=m
+CONFIG_RT2500USB=m
+CONFIG_RT73USB=m
+CONFIG_RT2800USB=m
+CONFIG_RT2800USB_RT3573=y
+CONFIG_RT2800USB_RT53XX=y
+CONFIG_RT2800USB_RT55XX=y
+CONFIG_RT2800USB_UNKNOWN=y
+CONFIG_WL_TI=y
+CONFIG_WL1251=m
+CONFIG_WL1251_SPI=m
+CONFIG_WL1251_SDIO=m
+CONFIG_WL12XX=m
+CONFIG_WL18XX=m
+CONFIG_WLCORE_SPI=m
+CONFIG_WLCORE_SDIO=m
+CONFIG_ZD1211RW=m
+CONFIG_MWIFIEX=m
+CONFIG_MWIFIEX_SDIO=m
+CONFIG_MWIFIEX_USB=m
+CONFIG_CW1200=m
+CONFIG_CW1200_WLAN_SDIO=m
+CONFIG_CW1200_WLAN_SPI=m
+CONFIG_RSI_91X=m
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+CONFIG_INPUT_TOUCHSCREEN=y
+CONFIG_TOUCHSCREEN_SUN4I=y
+CONFIG_INPUT_MISC=y
+CONFIG_INPUT_AXP20X_PEK=y
+CONFIG_INPUT_EVDEV=y
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_NR_UARTS=8
+CONFIG_SERIAL_8250_RUNTIME_UARTS=8
+CONFIG_SERIAL_8250_DW=y
+CONFIG_SERIAL_OF_PLATFORM=y
+# CONFIG_HW_RANDOM is not set
+CONFIG_I2C=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_MV64XXX=y
+CONFIG_I2C_SUN6I_P2WI=y
+CONFIG_SPI=y
+CONFIG_SPI_SPIDEV=y
+CONFIG_SPI_SUN4I=y
+CONFIG_SPI_SUN6I=y
+CONFIG_GPIOLIB_IRQCHIP=y
+CONFIG_GPIO_SYSFS=y
+CONFIG_GPIO_MAX730X=m
+CONFIG_GPIO_ADP5588=m
+CONFIG_GPIO_ADNP=m
+CONFIG_GPIO_MAX7300=m
+CONFIG_GPIO_MAX732X=m
+CONFIG_GPIO_PCA953X=m
+CONFIG_GPIO_PCF857X=m
+CONFIG_GPIO_TPIC2810=m
+CONFIG_GPIO_74X164=m
+CONFIG_GPIO_MAX7301=m
+CONFIG_GPIO_MC33880=m
+CONFIG_GPIO_PISOSR=m
+CONFIG_GPIO_XRA1403=m
+CONFIG_POWER_SUPPLY=y
+CONFIG_POWER_RESET=y
+CONFIG_POWER_RESET_GPIO=y
+CONFIG_POWER_RESET_GPIO_RESTART=y
+CONFIG_POWER_RESET_LTC2952=y
+CONFIG_THERMAL=y
+# CONFIG_THERMAL_STATISTICS is not set
+CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
+CONFIG_THERMAL_HWMON=y
+CONFIG_THERMAL_OF=y
+CONFIG_THERMAL_WRITABLE_TRIPS=y
+# CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE is not set
+CONFIG_THERMAL_DEFAULT_GOV_FAIR_SHARE=y
+# CONFIG_THERMAL_DEFAULT_GOV_USER_SPACE is not set
+# CONFIG_THERMAL_DEFAULT_GOV_POWER_ALLOCATOR is not set
+CONFIG_THERMAL_GOV_FAIR_SHARE=y
+CONFIG_THERMAL_GOV_STEP_WISE=y
+CONFIG_THERMAL_GOV_BANG_BANG=y
+# CONFIG_THERMAL_GOV_USER_SPACE is not set
+CONFIG_THERMAL_GOV_POWER_ALLOCATOR=y
+CONFIG_CPU_THERMAL=y
+CONFIG_CLOCK_THERMAL=y
+# CONFIG_DEVFREQ_THERMAL is not set
+# CONFIG_THERMAL_EMULATION is not set
+CONFIG_THERMAL_MMIO=m
+# CONFIG_QORIQ_THERMAL is not set
+CONFIG_SUN8I_THERMAL=m
+CONFIG_GENERIC_ADC_THERMAL=m
+CONFIG_WATCHDOG=y
+CONFIG_SUNXI_WATCHDOG=y
+CONFIG_WATCHDOG_CORE=y
+CONFIG_MFD_CORE=y
+CONFIG_MFD_SUN4I_GPADC=m
+CONFIG_MFD_AXP20X=y
+CONFIG_REGULATOR=y
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
+CONFIG_REGULATOR_AXP20X=y
+CONFIG_REGULATOR_GPIO=y
+CONFIG_MEDIA_SUPPORT=m
+CONFIG_MEDIA_CAMERA_SUPPORT=y
+CONFIG_MEDIA_ANALOG_TV_SUPPORT=y
+CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y
+CONFIG_MEDIA_RADIO_SUPPORT=y
+CONFIG_MEDIA_SDR_SUPPORT=y
+CONFIG_MEDIA_RC_SUPPORT=y
+CONFIG_MEDIA_CONTROLLER=y
+CONFIG_VIDEO_ADV_DEBUG=y
+CONFIG_DVB_DYNAMIC_MINORS=y
+CONFIG_MEDIA_USB_SUPPORT=y
+CONFIG_USB_VIDEO_CLASS=m
+CONFIG_USB_M5602=m
+CONFIG_USB_STV06XX=m
+CONFIG_USB_GL860=m
+CONFIG_USB_GSPCA_BENQ=m
+CONFIG_USB_GSPCA_CONEX=m
+CONFIG_USB_GSPCA_CPIA1=m
+CONFIG_USB_GSPCA_DTCS033=m
+CONFIG_USB_GSPCA_ETOMS=m
+CONFIG_USB_GSPCA_FINEPIX=m
+CONFIG_USB_GSPCA_JEILINJ=m
+CONFIG_USB_GSPCA_JL2005BCD=m
+CONFIG_USB_GSPCA_KINECT=m
+CONFIG_USB_GSPCA_KONICA=m
+CONFIG_USB_GSPCA_MARS=m
+CONFIG_USB_GSPCA_MR97310A=m
+CONFIG_USB_GSPCA_NW80X=m
+CONFIG_USB_GSPCA_OV519=m
+CONFIG_USB_GSPCA_OV534=m
+CONFIG_USB_GSPCA_OV534_9=m
+CONFIG_USB_GSPCA_PAC207=m
+CONFIG_USB_GSPCA_PAC7302=m
+CONFIG_USB_GSPCA_PAC7311=m
+CONFIG_USB_GSPCA_SE401=m
+CONFIG_USB_GSPCA_SN9C2028=m
+CONFIG_USB_GSPCA_SN9C20X=m
+CONFIG_USB_GSPCA_SONIXB=m
+CONFIG_USB_GSPCA_SONIXJ=m
+CONFIG_USB_GSPCA_SPCA500=m
+CONFIG_USB_GSPCA_SPCA501=m
+CONFIG_USB_GSPCA_SPCA505=m
+CONFIG_USB_GSPCA_SPCA506=m
+CONFIG_USB_GSPCA_SPCA508=m
+CONFIG_USB_GSPCA_SPCA561=m
+CONFIG_USB_GSPCA_SPCA1528=m
+CONFIG_USB_GSPCA_SQ905=m
+CONFIG_USB_GSPCA_SQ905C=m
+CONFIG_USB_GSPCA_SQ930X=m
+CONFIG_USB_GSPCA_STK014=m
+CONFIG_USB_GSPCA_STK1135=m
+CONFIG_USB_GSPCA_STV0680=m
+CONFIG_USB_GSPCA_SUNPLUS=m
+CONFIG_USB_GSPCA_T613=m
+CONFIG_USB_GSPCA_TOPRO=m
+CONFIG_USB_GSPCA_TOUPTEK=m
+CONFIG_USB_GSPCA_TV8532=m
+CONFIG_USB_GSPCA_VC032X=m
+CONFIG_USB_GSPCA_VICAM=m
+CONFIG_USB_GSPCA_XIRLINK_CIT=m
+CONFIG_USB_GSPCA_ZC3XX=m
+CONFIG_USB_PWC=m
+CONFIG_VIDEO_CPIA2=m
+CONFIG_USB_ZR364XX=m
+CONFIG_USB_STKWEBCAM=m
+CONFIG_USB_S2255=m
+CONFIG_VIDEO_PVRUSB2=m
+CONFIG_VIDEO_HDPVR=m
+CONFIG_VIDEO_USBVISION=m
+CONFIG_VIDEO_STK1160_COMMON=m
+CONFIG_VIDEO_AU0828=m
+CONFIG_VIDEO_AU0828_RC=y
+CONFIG_VIDEO_CX231XX=m
+CONFIG_VIDEO_CX231XX_DVB=m
+CONFIG_VIDEO_TM6000=m
+CONFIG_VIDEO_TM6000_DVB=m
+CONFIG_DVB_USB=m
+CONFIG_DVB_USB_A800=m
+CONFIG_DVB_USB_DIBUSB_MB=m
+CONFIG_DVB_USB_DIBUSB_MC=m
+CONFIG_DVB_USB_DIB0700=m
+CONFIG_DVB_USB_UMT_010=m
+CONFIG_DVB_USB_CXUSB=m
+CONFIG_DVB_USB_M920X=m
+CONFIG_DVB_USB_DIGITV=m
+CONFIG_DVB_USB_VP7045=m
+CONFIG_DVB_USB_VP702X=m
+CONFIG_DVB_USB_GP8PSK=m
+CONFIG_DVB_USB_NOVA_T_USB2=m
+CONFIG_DVB_USB_TTUSB2=m
+CONFIG_DVB_USB_DTT200U=m
+CONFIG_DVB_USB_OPERA1=m
+CONFIG_DVB_USB_AF9005=m
+CONFIG_DVB_USB_AF9005_REMOTE=m
+CONFIG_DVB_USB_PCTV452E=m
+CONFIG_DVB_USB_DW2102=m
+CONFIG_DVB_USB_CINERGY_T2=m
+CONFIG_DVB_USB_DTV5100=m
+CONFIG_DVB_USB_FRIIO=m
+CONFIG_DVB_USB_AZ6027=m
+CONFIG_DVB_USB_TECHNISAT_USB2=m
+CONFIG_DVB_USB_V2=m
+CONFIG_DVB_USB_AF9015=m
+CONFIG_DVB_USB_AF9035=m
+CONFIG_DVB_USB_ANYSEE=m
+CONFIG_DVB_USB_AU6610=m
+CONFIG_DVB_USB_AZ6007=m
+CONFIG_DVB_USB_CE6230=m
+CONFIG_DVB_USB_EC168=m
+CONFIG_DVB_USB_GL861=m
+CONFIG_DVB_USB_LME2510=m
+CONFIG_DVB_USB_MXL111SF=m
+CONFIG_DVB_USB_RTL28XXU=m
+CONFIG_DVB_USB_DVBSKY=m
+CONFIG_SMS_USB_DRV=m
+CONFIG_DVB_B2C2_FLEXCOP_USB=m
+CONFIG_DVB_AS102=m
+CONFIG_USB_AIRSPY=m
+CONFIG_USB_HACKRF=m
+CONFIG_USB_MSI2500=m
+CONFIG_V4L_PLATFORM_DRIVERS=y
+CONFIG_SOC_CAMERA=m
+CONFIG_SOC_CAMERA_PLATFORM=m
+CONFIG_V4L_MEM2MEM_DRIVERS=y
+CONFIG_V4L_TEST_DRIVERS=y
+CONFIG_VIDEO_VIVID=m
+CONFIG_VIDEO_VIM2M=m
+CONFIG_SMS_SDIO_DRV=m
+CONFIG_RADIO_SI470X=y
+CONFIG_USB_SI470X=m
+CONFIG_I2C_SI470X=m
+CONFIG_RADIO_SI4713=m
+CONFIG_USB_SI4713=m
+CONFIG_PLATFORM_SI4713=m
+CONFIG_USB_MR800=m
+CONFIG_USB_DSBR=m
+CONFIG_RADIO_SHARK=m
+CONFIG_RADIO_SHARK2=m
+CONFIG_USB_KEENE=m
+CONFIG_USB_RAREMONO=m
+CONFIG_USB_MA901=m
+CONFIG_RADIO_TEA5764=m
+CONFIG_RADIO_SAA7706H=m
+CONFIG_RADIO_TEF6862=m
+CONFIG_RADIO_WL1273=m
+CONFIG_SOC_CAMERA_IMX074=m
+CONFIG_SOC_CAMERA_MT9M001=m
+CONFIG_SOC_CAMERA_MT9M111=m
+CONFIG_SOC_CAMERA_MT9T031=m
+CONFIG_SOC_CAMERA_MT9T112=m
+CONFIG_SOC_CAMERA_MT9V022=m
+CONFIG_SOC_CAMERA_OV2640=m
+CONFIG_SOC_CAMERA_OV5642=m
+CONFIG_SOC_CAMERA_OV6650=m
+CONFIG_SOC_CAMERA_OV772X=m
+CONFIG_SOC_CAMERA_OV9640=m
+CONFIG_SOC_CAMERA_OV9740=m
+CONFIG_SOC_CAMERA_RJ54N1=m
+CONFIG_SOC_CAMERA_TW9910=m
+CONFIG_FB=y
+CONFIG_FB_SIMPLE=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
+CONFIG_USB=y
+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
+CONFIG_USB_DYNAMIC_MINORS=y
+CONFIG_USB_MON=m
+CONFIG_USB_EHCI_ROOT_HUB_TT=y
+CONFIG_USB_TMC=m
+CONFIG_USBIP_CORE=m
+CONFIG_USBIP_VHCI_HCD=m
+CONFIG_USBIP_VHCI_HC_PORTS=8
+CONFIG_USBIP_VHCI_NR_HCS=1
+CONFIG_USBIP_HOST=m
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_HCD_PLATFORM=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_HCD_PLATFORM=y
+CONFIG_USB_SERIAL=m
+CONFIG_USB_SERIAL_GENERIC=y
+CONFIG_USB_SERIAL_SIMPLE=m
+CONFIG_USB_SERIAL_CP210X=m
+CONFIG_USB_SERIAL_CH341=m
+CONFIG_USB_SERIAL_FTDI_SIO=m
+CONFIG_USB_SERIAL_KEYSPAN=m
+CONFIG_USB_SERIAL_KEYSPAN_MPR=y
+CONFIG_USB_SERIAL_KEYSPAN_USA28=y
+CONFIG_USB_SERIAL_KEYSPAN_USA28X=y
+CONFIG_USB_SERIAL_KEYSPAN_USA28XA=y
+CONFIG_USB_SERIAL_KEYSPAN_USA28XB=y
+CONFIG_USB_SERIAL_KEYSPAN_USA19=y
+CONFIG_USB_SERIAL_KEYSPAN_USA18X=y
+CONFIG_USB_SERIAL_KEYSPAN_USA19W=y
+CONFIG_USB_SERIAL_KEYSPAN_USA19QI=y
+CONFIG_USB_SERIAL_KEYSPAN_USA49W=y
+CONFIG_USB_SERIAL_KEYSPAN_USA49WLC=y
+CONFIG_USB_SERIAL_KLSI=m
+CONFIG_USB_SERIAL_MOS7720=m
+CONFIG_USB_SERIAL_MOS7840=m
+CONFIG_USB_SERIAL_PL2303=m
+CONFIG_USB_SERIAL_QCAUX=m
+CONFIG_USB_SERIAL_QUALCOMM=m
+CONFIG_USB_SERIAL_WWAN=m
+CONFIG_USB_SERIAL_OPTION=m
+CONFIG_MMC=y
+CONFIG_MMC_SUNXI=y
+CONFIG_LEDS_CLASS=y
+CONFIG_LEDS_CLASS_FLASH=y
+CONFIG_LEDS_LM3530=m
+CONFIG_LEDS_GPIO=y
+CONFIG_LEDS_LP3944=m
+CONFIG_LEDS_LP5521=m
+CONFIG_LEDS_LP5523=m
+CONFIG_LEDS_LP5562=m
+CONFIG_LEDS_LP8501=m
+CONFIG_LEDS_PCA955X=m
+CONFIG_LEDS_PCA963X=m
+CONFIG_LEDS_DAC124S085=m
+CONFIG_LEDS_REGULATOR=y
+CONFIG_LEDS_BD2802=m
+CONFIG_LEDS_LT3593=m
+CONFIG_LEDS_TCA6507=m
+CONFIG_LEDS_LM355x=m
+CONFIG_LEDS_BLINKM=m
+CONFIG_LEDS_TRIGGER_TIMER=y
+CONFIG_LEDS_TRIGGER_ONESHOT=y
+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
+CONFIG_LEDS_TRIGGER_BACKLIGHT=y
+CONFIG_LEDS_TRIGGER_CPU=y
+CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
+CONFIG_LEDS_TRIGGER_TRANSIENT=y
+CONFIG_LEDS_TRIGGER_CAMERA=y
+CONFIG_RTC_LIB=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_HCTOSYS=y
+CONFIG_RTC_HCTOSYS_DEVICE="rtc1"
+CONFIG_RTC_SYSTOHC=y
+CONFIG_RTC_SYSTOHC_DEVICE="rtc1"
+CONFIG_RTC_NVMEM=y
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+CONFIG_RTC_INTF_DEV_UIE_EMUL=y
+CONFIG_RTC_DRV_DS1307=m
+CONFIG_RTC_DRV_PCF8563=m
+CONFIG_RTC_DRV_DS3232=m
+CONFIG_RTC_DRV_DS3232_HWMON=y
+CONFIG_RTC_DRV_RX8010=m
+CONFIG_RTC_DRV_RX8581=m
+CONFIG_RTC_DRV_RX8025=m
+CONFIG_RTC_DRV_DS1302=m
+CONFIG_RTC_DRV_R9701=m
+CONFIG_RTC_DRV_RX4581=m
+CONFIG_RTC_DRV_RX6110=m
+CONFIG_RTC_DRV_SUN6I=y
+CONFIG_RTC_DRV_SUNXI=y
+CONFIG_DMADEVICES=y
+CONFIG_DMA_SUN6I=y
+# CONFIG_IOMMU_SUPPORT is not set
+CONFIG_EXTCON=y
+CONFIG_PWM=y
+CONFIG_PWM_SUN4I=y
+CONFIG_PHY_SUN4I_USB=y
+CONFIG_PHY_SUN9I_USB=y
+CONFIG_EXT4_FS=y
+CONFIG_XFS_FS=m
+CONFIG_XFS_POSIX_ACL=y
+CONFIG_BTRFS_FS=m
+CONFIG_BTRFS_FS_POSIX_ACL=y
+CONFIG_F2FS_FS=y
+CONFIG_F2FS_STAT_FS=y
+CONFIG_F2FS_FS_XATTR=y
+CONFIG_F2FS_FS_POSIX_ACL=y
+CONFIG_FANOTIFY=y
+CONFIG_AUTOFS4_FS=m
+CONFIG_FUSE_FS=m
+CONFIG_OVERLAY_FS=y
+CONFIG_OVERLAY_FS_REDIRECT_DIR=y
+CONFIG_OVERLAY_FS_INDEX=y
+CONFIG_FSCACHE=m
+CONFIG_FSCACHE_STATS=y
+CONFIG_FSCACHE_HISTOGRAM=y
+CONFIG_CACHEFILES=m
+CONFIG_CACHEFILES_HISTOGRAM=y
+CONFIG_SQUASHFS=y
+CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU=y
+CONFIG_SQUASHFS_XATTR=y
+CONFIG_SQUASHFS_LZO=y
+CONFIG_SQUASHFS_XZ=y
+CONFIG_SQUASHFS_ZSTD=y
+CONFIG_SQUASHFS_4K_DEVBLK_SIZE=y
+CONFIG_SQUASHFS_EMBEDDED=y
+CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3
+CONFIG_ISO9660_FS=m
+CONFIG_JOLIET=y
+CONFIG_ZISOFS=y
+CONFIG_UDF_FS=m
+CONFIG_VFAT_FS=y
+CONFIG_TMPFS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3_ACL=y
+CONFIG_NFS_V4=y
+CONFIG_ROOT_NFS=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_PRINTK_TIME=y
+CONFIG_CRYPTO_DEV_SUN4I_SS=y
+CONFIG_ARM_CRYPTO=y
+CONFIG_CRYPTO_SHA1_ARM=m
+CONFIG_CRYPTO_SHA1_ARM_NEON=m
+CONFIG_CRYPTO_SHA1_ARM_CE=m
+CONFIG_CRYPTO_SHA2_ARM_CE=m
+CONFIG_CRYPTO_SHA256_ARM=m
+CONFIG_CRYPTO_SHA512_ARM=m
+CONFIG_CRYPTO_AES_ARM=m
+CONFIG_CRYPTO_AES_ARM_BS=m
+CONFIG_CRYPTO_AES_ARM_CE=m
+CONFIG_CRYPTO_GHASH_ARM_CE=m
+CONFIG_CRYPTO_CRCT10DIF_ARM_CE=m
+CONFIG_CRYPTO_CRC32_ARM_CE=y
+CONFIG_CRYPTO_CHACHA20_NEON=y
+CONFIG_USB_ACM=m
+CONFIG_USB_STORAGE=y
+
+CONFIG_SENSORS_INA2XX=m
+CONFIG_BATTERY_BQ27XXX=m
+CONFIG_BATTERY_BQ27XXX_I2C=m
+CONFIG_BATTERY_BQ27XXX_DT_UPDATES_NVM=y
+CONFIG_BATTERY_MAX17040=m
+CONFIG_BATTERY_MAX17042=m
+CONFIG_BATTERY_CW2015=m
+CONFIG_CHARGER_MAX8903=m
+CONFIG_CHARGER_LP8727=m
+CONFIG_CHARGER_GPIO=m
+CONFIG_CHARGER_MANAGER=y
+CONFIG_CHARGER_LTC3651=m
+CONFIG_CHARGER_DETECTOR_MAX14656=m
+CONFIG_CHARGER_BQ2415X=m
+CONFIG_CHARGER_BQ24190=m
+CONFIG_CHARGER_BQ24257=m
+CONFIG_CHARGER_BQ24735=m
+CONFIG_CHARGER_BQ25890=m
+CONFIG_CHARGER_SMB347=m
+CONFIG_BATTERY_GAUGE_LTC2941=m
+CONFIG_CHARGER_RT9455=m
+
+CONFIG_USB_CATC=m
+CONFIG_USB_KAWETH=m
+CONFIG_USB_PEGASUS=m
+CONFIG_USB_RTL8150=m
+CONFIG_USB_RTL8152=m
+CONFIG_USB_LAN78XX=m
+CONFIG_USB_NET_CDC_EEM=m
+CONFIG_USB_NET_HUAWEI_CDC_NCM=m
+CONFIG_USB_NET_CDC_MBIM=m
+CONFIG_USB_NET_DM9601=m
+CONFIG_USB_NET_SR9700=m
+CONFIG_USB_NET_SR9800=m
+CONFIG_USB_NET_SMSC75XX=m
+CONFIG_USB_NET_SMSC95XX=m
+CONFIG_USB_NET_GL620A=m
+CONFIG_USB_NET_PLUSB=m
+CONFIG_USB_NET_MCS7830=m
+CONFIG_USB_NET_CX82310_ETH=m
+CONFIG_USB_NET_KALMIA=m
+CONFIG_USB_NET_QMI_WWAN=m
+CONFIG_USB_HSO=m
+CONFIG_USB_NET_INT51X1=m
+CONFIG_USB_IPHETH=m
+CONFIG_USB_SIERRA_NET=m
+CONFIG_USB_VL600=m
+CONFIG_USB_NET_CH9200=m
+CONFIG_USB_WDM=m
+
+CONFIG_UIO=m
+CONFIG_UIO_PDRV_GENIRQ=m
+CONFIG_UIO_DMEM_GENIRQ=m
+CONFIG_IIO=m
+CONFIG_IIO_BUFFER=y
+CONFIG_IIO_BUFFER_CB=m
+CONFIG_IIO_KFIFO_BUF=m
+CONFIG_IIO_TRIGGERED_BUFFER=m
+CONFIG_IIO_TRIGGER=y
+CONFIG_IIO_CONSUMERS_PER_TRIGGER=2
+
+CONFIG_POWERCAP=y
+
+CONFIG_SUN4I_GPADC=m
+
+CONFIG_USB_MUSB_HDRC=m
+CONFIG_USB_MUSB_DUAL_ROLE=y
+CONFIG_USB_MUSB_SUNXI=m
+
+CONFIG_USB_OTG=y
+CONFIG_USB_OTG_FSM=m
+
+CONFIG_USB_PHY=y
+CONFIG_NOP_USB_XCEIV=m
+
+CONFIG_USB_GADGET=m
+CONFIG_USB_GADGET_VBUS_DRAW=500
+CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2
+CONFIG_U_SERIAL_CONSOLE=y
+
+CONFIG_USB_LIBCOMPOSITE=m
+CONFIG_USB_F_ACM=m
+CONFIG_USB_U_SERIAL=m
+CONFIG_USB_U_ETHER=m
+CONFIG_USB_F_ECM=m
+CONFIG_USB_F_RNDIS=m
+CONFIG_USB_CONFIGFS=m
+CONFIG_USB_CONFIGFS_ACM=y
+CONFIG_USB_CONFIGFS_ECM=y
+CONFIG_USB_CONFIGFS_RNDIS=y
+
+CONFIG_USB_ETH=m
+CONFIG_USB_ETH_RNDIS=y
+CONFIG_USB_G_NCM=m
+CONFIG_USB_G_SERIAL=m

+ 4269 - 0
recipes-kernel/linux/files/xuantie-c910/xuantie-linux-5.4.36.patch

@@ -0,0 +1,4269 @@
+diff -Nur linux-5.4.36/arch/riscv/include/asm/asid.h kernel/arch/riscv/include/asm/asid.h
+--- linux-5.4.36/arch/riscv/include/asm/asid.h	1970-01-01 00:00:00.000000000 +0000
++++ kernel/arch/riscv/include/asm/asid.h	2020-09-03 06:01:13.901989796 +0000
+@@ -0,0 +1,78 @@
++/* SPDX-License-Identifier: GPL-2.0 */
++#ifndef __ASM_ASM_ASID_H
++#define __ASM_ASM_ASID_H
++
++#include <linux/atomic.h>
++#include <linux/compiler.h>
++#include <linux/cpumask.h>
++#include <linux/percpu.h>
++#include <linux/spinlock.h>
++
++struct asid_info
++{
++	atomic64_t	generation;
++	unsigned long	*map;
++	atomic64_t __percpu	*active;
++	u64 __percpu		*reserved;
++	u32			bits;
++	/* Lock protecting the structure */
++	raw_spinlock_t		lock;
++	/* Which CPU requires context flush on next call */
++	cpumask_t		flush_pending;
++	/* Number of ASID allocated by context (shift value) */
++	unsigned int		ctxt_shift;
++	/* Callback to locally flush the context. */
++	void			(*flush_cpu_ctxt_cb)(void);
++};
++
++#define NUM_ASIDS(info)			(1UL << ((info)->bits))
++#define NUM_CTXT_ASIDS(info)		(NUM_ASIDS(info) >> (info)->ctxt_shift)
++
++#define active_asid(info, cpu)	*per_cpu_ptr((info)->active, cpu)
++
++void asid_new_context(struct asid_info *info, atomic64_t *pasid,
++		      unsigned int cpu, struct mm_struct *mm);
++
++/*
++ * Check the ASID is still valid for the context. If not generate a new ASID.
++ *
++ * @pasid: Pointer to the current ASID batch
++ * @cpu: current CPU ID. Must have been acquired throught get_cpu()
++ */
++static inline void asid_check_context(struct asid_info *info,
++				      atomic64_t *pasid, unsigned int cpu,
++				      struct mm_struct *mm)
++{
++	u64 asid, old_active_asid;
++
++	asid = atomic64_read(pasid);
++
++	/*
++	 * The memory ordering here is subtle.
++	 * If our active_asid is non-zero and the ASID matches the current
++	 * generation, then we update the active_asid entry with a relaxed
++	 * cmpxchg. Racing with a concurrent rollover means that either:
++	 *
++	 * - We get a zero back from the cmpxchg and end up waiting on the
++	 *   lock. Taking the lock synchronises with the rollover and so
++	 *   we are forced to see the updated generation.
++	 *
++	 * - We get a valid ASID back from the cmpxchg, which means the
++	 *   relaxed xchg in flush_context will treat us as reserved
++	 *   because atomic RmWs are totally ordered for a given location.
++	 */
++	old_active_asid = atomic64_read(&active_asid(info, cpu));
++	if (old_active_asid &&
++	    !((asid ^ atomic64_read(&info->generation)) >> info->bits) &&
++	    atomic64_cmpxchg_relaxed(&active_asid(info, cpu),
++				     old_active_asid, asid))
++		return;
++
++	asid_new_context(info, pasid, cpu, mm);
++}
++
++int asid_allocator_init(struct asid_info *info,
++			u32 bits, unsigned int asid_per_ctxt,
++			void (*flush_cpu_ctxt_cb)(void));
++
++#endif
+diff -Nur linux-5.4.36/arch/riscv/include/asm/cacheflush.h kernel/arch/riscv/include/asm/cacheflush.h
+--- linux-5.4.36/arch/riscv/include/asm/cacheflush.h	2020-04-29 14:33:25.000000000 +0000
++++ kernel/arch/riscv/include/asm/cacheflush.h	2020-09-03 06:01:13.902989796 +0000
+@@ -99,6 +99,9 @@
+ 
+ #endif /* CONFIG_SMP */
+ 
++void dma_wbinv_range(unsigned long start, unsigned long end);
++void dma_wb_range(unsigned long start, unsigned long end);
++
+ /*
+  * Bits in sys_riscv_flush_icache()'s flags argument.
+  */
+diff -Nur linux-5.4.36/arch/riscv/include/asm/csr.h kernel/arch/riscv/include/asm/csr.h
+--- linux-5.4.36/arch/riscv/include/asm/csr.h	2020-04-29 14:33:25.000000000 +0000
++++ kernel/arch/riscv/include/asm/csr.h	2020-09-03 06:01:13.902989796 +0000
+@@ -21,6 +21,12 @@
+ #define SR_FS_CLEAN	_AC(0x00004000, UL)
+ #define SR_FS_DIRTY	_AC(0x00006000, UL)
+ 
++#define SR_VS		_AC(0x01800000, UL) /* Vector Status */
++#define SR_VS_OFF	_AC(0x00000000, UL)
++#define SR_VS_INITIAL	_AC(0x00800000, UL)
++#define SR_VS_CLEAN	_AC(0x01000000, UL)
++#define SR_VS_DIRTY	_AC(0x01800000, UL)
++
+ #define SR_XS		_AC(0x00018000, UL) /* Extension Status */
+ #define SR_XS_OFF	_AC(0x00000000, UL)
+ #define SR_XS_INITIAL	_AC(0x00008000, UL)
+@@ -42,6 +48,9 @@
+ #define SATP_PPN	_AC(0x00000FFFFFFFFFFF, UL)
+ #define SATP_MODE_39	_AC(0x8000000000000000, UL)
+ #define SATP_MODE	SATP_MODE_39
++#define SATP_ASID_BITS	16
++#define SATP_ASID_SHIFT	44
++#define SATP_ASID_MASK	_AC(0xFFFF, UL)
+ #endif
+ 
+ /* SCAUSE */
+@@ -56,6 +65,7 @@
+ #define IRQ_U_EXT		8
+ #define IRQ_S_EXT		9
+ #define IRQ_M_EXT		11
++#define IRQ_S_PMU		17
+ 
+ #define EXC_INST_MISALIGNED	0
+ #define EXC_INST_ACCESS		1
+@@ -67,10 +77,18 @@
+ #define EXC_LOAD_PAGE_FAULT	13
+ #define EXC_STORE_PAGE_FAULT	15
+ 
++#define CSR_VSTART		0x8
++#define CSR_VXSAT		0x9
++#define CSR_VXRM		0xa
++#define CSR_VL			0xc20
++#define CSR_VTYPE		0xc21
++#define CSR_VLENB		0xc22
++
+ /* SIE (Interrupt Enable) and SIP (Interrupt Pending) flags */
+ #define SIE_SSIE		(_AC(0x1, UL) << IRQ_S_SOFT)
+ #define SIE_STIE		(_AC(0x1, UL) << IRQ_S_TIMER)
+ #define SIE_SEIE		(_AC(0x1, UL) << IRQ_S_EXT)
++#define SIE_SMIE		(_AC(0x1, UL) << IRQ_S_PMU)
+ 
+ #define CSR_CYCLE		0xc00
+ #define CSR_TIME		0xc01
+diff -Nur linux-5.4.36/arch/riscv/include/asm/elf.h kernel/arch/riscv/include/asm/elf.h
+--- linux-5.4.36/arch/riscv/include/asm/elf.h	2020-04-29 14:33:25.000000000 +0000
++++ kernel/arch/riscv/include/asm/elf.h	2020-09-03 06:01:13.902989796 +0000
+@@ -49,6 +49,9 @@
+ #define ELF_HWCAP	(elf_hwcap)
+ extern unsigned long elf_hwcap;
+ 
++#define ELF_CORE_COPY_REGS(dest, regs)  \
++	*(struct user_regs_struct *)&(dest) = (regs)->user_regs;
++
+ /*
+  * This yields a string that ld.so will use to load implementation
+  * specific libraries for optimization.  This is more specific in
+diff -Nur linux-5.4.36/arch/riscv/include/asm/fence.h kernel/arch/riscv/include/asm/fence.h
+--- linux-5.4.36/arch/riscv/include/asm/fence.h	2020-04-29 14:33:25.000000000 +0000
++++ kernel/arch/riscv/include/asm/fence.h	2020-09-03 06:01:13.902989796 +0000
+@@ -9,4 +9,8 @@
+ #define RISCV_RELEASE_BARRIER
+ #endif
+ 
++extern int c910_mmu_v1_flag;
++#define sync_mmu_v1() \
++	if (c910_mmu_v1_flag) asm volatile (".long 0x01b0000b");
++
+ #endif	/* _ASM_RISCV_FENCE_H */
+diff -Nur linux-5.4.36/arch/riscv/include/asm/io.h kernel/arch/riscv/include/asm/io.h
+--- linux-5.4.36/arch/riscv/include/asm/io.h	2020-04-29 14:33:25.000000000 +0000
++++ kernel/arch/riscv/include/asm/io.h	2020-09-03 06:01:13.903989796 +0000
+@@ -12,19 +12,17 @@
+ #define _ASM_RISCV_IO_H
+ 
+ #include <linux/types.h>
++#include <asm/fence.h>
+ #include <asm/mmiowb.h>
+ #include <asm/pgtable.h>
+ 
+-extern void __iomem *ioremap(phys_addr_t offset, unsigned long size);
++extern void __iomem *ioremap_cache(phys_addr_t addr, size_t size);
++extern void __iomem *__ioremap(phys_addr_t addr, size_t size, pgprot_t prot);
+ 
+-/*
+- * The RISC-V ISA doesn't yet specify how to query or modify PMAs, so we can't
+- * change the properties of memory regions.  This should be fixed by the
+- * upcoming platform spec.
+- */
+-#define ioremap_nocache(addr, size) ioremap((addr), (size))
+-#define ioremap_wc(addr, size) ioremap((addr), (size))
+-#define ioremap_wt(addr, size) ioremap((addr), (size))
++#define ioremap(addr, size)		__ioremap((addr), (size), pgprot_noncached(PAGE_KERNEL))
++#define ioremap_wc(addr, size)		__ioremap((addr), (size), pgprot_writecombine(PAGE_KERNEL))
++#define ioremap_nocache(addr, size)	ioremap((addr), (size))
++#define ioremap_cache			ioremap_cache
+ 
+ extern void iounmap(volatile void __iomem *addr);
+ 
+@@ -32,26 +30,34 @@
+ #define __raw_writeb __raw_writeb
+ static inline void __raw_writeb(u8 val, volatile void __iomem *addr)
+ {
++	sync_mmu_v1();
+ 	asm volatile("sb %0, 0(%1)" : : "r" (val), "r" (addr));
++	sync_mmu_v1();
+ }
+ 
+ #define __raw_writew __raw_writew
+ static inline void __raw_writew(u16 val, volatile void __iomem *addr)
+ {
++	sync_mmu_v1();
+ 	asm volatile("sh %0, 0(%1)" : : "r" (val), "r" (addr));
++	sync_mmu_v1();
+ }
+ 
+ #define __raw_writel __raw_writel
+ static inline void __raw_writel(u32 val, volatile void __iomem *addr)
+ {
++	sync_mmu_v1();
+ 	asm volatile("sw %0, 0(%1)" : : "r" (val), "r" (addr));
++	sync_mmu_v1();
+ }
+ 
+ #ifdef CONFIG_64BIT
+ #define __raw_writeq __raw_writeq
+ static inline void __raw_writeq(u64 val, volatile void __iomem *addr)
+ {
++	sync_mmu_v1();
+ 	asm volatile("sd %0, 0(%1)" : : "r" (val), "r" (addr));
++	sync_mmu_v1();
+ }
+ #endif
+ 
+@@ -60,7 +66,9 @@
+ {
+ 	u8 val;
+ 
++	sync_mmu_v1();
+ 	asm volatile("lb %0, 0(%1)" : "=r" (val) : "r" (addr));
++	sync_mmu_v1();
+ 	return val;
+ }
+ 
+@@ -69,7 +77,9 @@
+ {
+ 	u16 val;
+ 
++	sync_mmu_v1();
+ 	asm volatile("lh %0, 0(%1)" : "=r" (val) : "r" (addr));
++	sync_mmu_v1();
+ 	return val;
+ }
+ 
+@@ -78,7 +88,9 @@
+ {
+ 	u32 val;
+ 
++	sync_mmu_v1();
+ 	asm volatile("lw %0, 0(%1)" : "=r" (val) : "r" (addr));
++	sync_mmu_v1();
+ 	return val;
+ }
+ 
+@@ -88,7 +100,9 @@
+ {
+ 	u64 val;
+ 
++	sync_mmu_v1();
+ 	asm volatile("ld %0, 0(%1)" : "=r" (val) : "r" (addr));
++	sync_mmu_v1();
+ 	return val;
+ }
+ #endif
+diff -Nur linux-5.4.36/arch/riscv/include/asm/kexec.h kernel/arch/riscv/include/asm/kexec.h
+--- linux-5.4.36/arch/riscv/include/asm/kexec.h	1970-01-01 00:00:00.000000000 +0000
++++ kernel/arch/riscv/include/asm/kexec.h	2020-09-03 06:01:13.903989796 +0000
+@@ -0,0 +1,99 @@
++/*
++ * kexec for riscv
++ *
++ * Copyright (C) 2020-2025 Alibaba Group Holding Limited
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#ifndef _RISCV_KEXEC_H
++#define _RISCV_KEXEC_H
++
++/* Maximum physical address we can use pages from */
++
++#define KEXEC_SOURCE_MEMORY_LIMIT (-1UL)
++
++/* Maximum address we can reach in physical address mode */
++
++#define KEXEC_DESTINATION_MEMORY_LIMIT (-1UL)
++
++/* Maximum address we can use for the control code buffer */
++
++#define KEXEC_CONTROL_MEMORY_LIMIT (-1UL)
++
++#define KEXEC_CONTROL_PAGE_SIZE 4096
++
++#define KEXEC_ARCH KEXEC_ARCH_RISCV
++
++#ifndef __ASSEMBLY__
++
++/**
++ * crash_setup_regs() - save registers for the panic kernel
++ *
++ * @newregs: registers are saved here
++ * @oldregs: registers to be saved (may be %NULL)
++ */
++static inline void crash_setup_regs(struct pt_regs *newregs,
++				    struct pt_regs *oldregs)
++{
++	if (oldregs) {
++		memcpy(newregs, oldregs, sizeof(*newregs));
++	} else {
++		u64 tmp1, tmp2;
++
++		__asm__ __volatile__ (
++			"sd	ra, 8(%2)\n"
++			"sd	gp, 24(%2)\n"
++			"sd	t0, 40(%2)\n"
++			"sd	t1, 48(%2)\n"
++			"sd	t2, 56(%2)\n"
++			"sd	s0, 64(%2)\n"
++			"sd	s1, 72(%2)\n"
++			"sd	a0, 80(%2)\n"
++			"sd	a1, 88(%2)\n"
++			"sd	a2, 96(%2)\n"
++			"sd	a3, 104(%2)\n"
++			"sd	a4, 112(%2)\n"
++			"sd	a5, 120(%2)\n"
++			"sd	a6, 128(%2)\n"
++			"sd	a7, 136(%2)\n"
++			"sd	s2, 144(%2)\n"
++			"sd	s3, 152(%2)\n"
++			"sd	s4, 160(%2)\n"
++			"sd	s5, 168(%2)\n"
++			"sd	s6, 176(%2)\n"
++			"sd	s7, 184(%2)\n"
++			"sd	s8, 192(%2)\n"
++			"sd	s9, 200(%2)\n"
++			"sd	s10, 208(%2)\n"
++			"sd	s11, 216(%2)\n"
++			"sd	t3, 224(%2)\n"
++			"sd	t4, 232(%2)\n"
++			"sd	t5, 240(%2)\n"
++			"sd	t6, 248(%2)\n"
++			"auipc	%0, 0\n"
++			"sd	%0, 0(%2)\n"
++			"csrr	%0, sstatus\n"
++			"sd	%0, 256(%2)\n"
++			"csrr	%0, stval\n"
++			"sd	%0, 264(%2)\n"
++			"csrr	%0, scause\n"
++			"sd	%0, 272(%2)\n"
++			"sd tp, 32(%2)\n"
++			"sd	sp, 16(%2)\n"
++			: "=&r" (tmp1), "=&r" (tmp2)
++			: "r" (newregs)
++			: "memory"
++		);
++	}
++}
++
++static inline bool crash_is_nosave(unsigned long pfn) {return false; }
++static inline void crash_prepare_suspend(void) {}
++static inline void crash_post_resume(void) {}
++
++#endif /* __ASSEMBLY__ */
++
++#endif
+diff -Nur linux-5.4.36/arch/riscv/include/asm/mmu_context.h kernel/arch/riscv/include/asm/mmu_context.h
+--- linux-5.4.36/arch/riscv/include/asm/mmu_context.h	2020-04-29 14:33:25.000000000 +0000
++++ kernel/arch/riscv/include/asm/mmu_context.h	2020-09-03 06:01:13.903989796 +0000
+@@ -12,19 +12,20 @@
+ 
+ #include <linux/mm.h>
+ #include <linux/sched.h>
++#include <asm/tlbflush.h>
++#include <asm/cacheflush.h>
++#include <asm/asid.h>
++
++#define ASID_MASK		((1 << SATP_ASID_BITS) - 1)
++#define cpu_asid(mm)		(atomic64_read(&mm->context.asid) & ASID_MASK)
++
++#define init_new_context(tsk,mm)	({ atomic64_set(&(mm)->context.asid, 0); 0; })
+ 
+ static inline void enter_lazy_tlb(struct mm_struct *mm,
+ 	struct task_struct *task)
+ {
+ }
+ 
+-/* Initialize context-related info for a new mm_struct */
+-static inline int init_new_context(struct task_struct *task,
+-	struct mm_struct *mm)
+-{
+-	return 0;
+-}
+-
+ static inline void destroy_context(struct mm_struct *mm)
+ {
+ }
+@@ -32,6 +33,8 @@
+ void switch_mm(struct mm_struct *prev, struct mm_struct *next,
+ 	struct task_struct *task);
+ 
++void check_and_switch_context(struct mm_struct *mm, unsigned int cpu);
++
+ static inline void activate_mm(struct mm_struct *prev,
+ 			       struct mm_struct *next)
+ {
+diff -Nur linux-5.4.36/arch/riscv/include/asm/mmu.h kernel/arch/riscv/include/asm/mmu.h
+--- linux-5.4.36/arch/riscv/include/asm/mmu.h	2020-04-29 14:33:25.000000000 +0000
++++ kernel/arch/riscv/include/asm/mmu.h	2020-09-03 06:01:13.903989796 +0000
+@@ -11,6 +11,7 @@
+ 
+ typedef struct {
+ 	void *vdso;
++	atomic64_t asid;
+ #ifdef CONFIG_SMP
+ 	/* A local icache flush is needed before user execution can resume. */
+ 	cpumask_t icache_stale_mask;
+diff -Nur linux-5.4.36/arch/riscv/include/asm/perf_event.h kernel/arch/riscv/include/asm/perf_event.h
+--- linux-5.4.36/arch/riscv/include/asm/perf_event.h	2020-04-29 14:33:25.000000000 +0000
++++ kernel/arch/riscv/include/asm/perf_event.h	2020-09-03 06:01:13.903989796 +0000
+@@ -18,8 +18,8 @@
+  * The RISCV_MAX_COUNTERS parameter should be specified.
+  */
+ 
+-#ifdef CONFIG_RISCV_BASE_PMU
+-#define RISCV_MAX_COUNTERS	2
++#if defined(CONFIG_RISCV_BASE_PMU) || defined(CONFIG_THEAD_XT_V1_PMU)
++#define RISCV_MAX_COUNTERS	32
+ #endif
+ 
+ #ifndef RISCV_MAX_COUNTERS
+diff -Nur linux-5.4.36/arch/riscv/include/asm/pgtable-64.h kernel/arch/riscv/include/asm/pgtable-64.h
+--- linux-5.4.36/arch/riscv/include/asm/pgtable-64.h	2020-04-29 14:33:25.000000000 +0000
++++ kernel/arch/riscv/include/asm/pgtable-64.h	2020-09-03 06:01:13.903989796 +0000
+@@ -55,7 +55,7 @@
+ 
+ static inline unsigned long pud_page_vaddr(pud_t pud)
+ {
+-	return (unsigned long)pfn_to_virt(pud_val(pud) >> _PAGE_PFN_SHIFT);
++	return (unsigned long)pfn_to_virt((pud_val(pud) & _PAGE_CHG_MASK) >> _PAGE_PFN_SHIFT);
+ }
+ 
+ #define pmd_index(addr) (((addr) >> PMD_SHIFT) & (PTRS_PER_PMD - 1))
+diff -Nur linux-5.4.36/arch/riscv/include/asm/pgtable-bits.h kernel/arch/riscv/include/asm/pgtable-bits.h
+--- linux-5.4.36/arch/riscv/include/asm/pgtable-bits.h	2020-04-29 14:33:25.000000000 +0000
++++ kernel/arch/riscv/include/asm/pgtable-bits.h	2020-09-03 06:01:13.903989796 +0000
+@@ -24,6 +24,13 @@
+ #define _PAGE_DIRTY     (1 << 7)    /* Set by hardware on any write */
+ #define _PAGE_SOFT      (1 << 8)    /* Reserved for software */
+ 
++/* C-SKY extend */
++#define _PAGE_SEC	(1UL << 59)   /* Security */
++#define _PAGE_SHARE	(1UL << 60)   /* Shareable */
++#define _PAGE_BUF	(1UL << 61)   /* Bufferable */
++#define _PAGE_CACHE	(1UL << 62)   /* Cacheable */
++#define _PAGE_SO	(1UL << 63)   /* Strong Order */
++
+ #define _PAGE_SPECIAL   _PAGE_SOFT
+ #define _PAGE_TABLE     _PAGE_PRESENT
+ 
+@@ -38,6 +45,9 @@
+ /* Set of bits to preserve across pte_modify() */
+ #define _PAGE_CHG_MASK  (~(unsigned long)(_PAGE_PRESENT | _PAGE_READ |	\
+ 					  _PAGE_WRITE | _PAGE_EXEC |	\
+-					  _PAGE_USER | _PAGE_GLOBAL))
++					  _PAGE_USER | _PAGE_GLOBAL |	\
++					  _PAGE_SEC | _PAGE_SHARE |	\
++					  _PAGE_BUF | _PAGE_CACHE |	\
++					  _PAGE_SO ))
+ 
+ #endif /* _ASM_RISCV_PGTABLE_BITS_H */
+diff -Nur linux-5.4.36/arch/riscv/include/asm/pgtable.h kernel/arch/riscv/include/asm/pgtable.h
+--- linux-5.4.36/arch/riscv/include/asm/pgtable.h	2020-04-29 14:33:25.000000000 +0000
++++ kernel/arch/riscv/include/asm/pgtable.h	2020-09-03 06:01:13.903989796 +0000
+@@ -35,9 +35,11 @@
+ #define FIRST_USER_ADDRESS  0
+ 
+ /* Page protection bits */
+-#define _PAGE_BASE	(_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_USER)
++#define _PAGE_BASE	(_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_USER | \
++			 _PAGE_SHARE | _PAGE_CACHE | _PAGE_BUF)
+ 
+-#define PAGE_NONE		__pgprot(_PAGE_PROT_NONE)
++#define PAGE_NONE		__pgprot(_PAGE_PROT_NONE | _PAGE_CACHE | \
++					 _PAGE_BUF | _PAGE_SHARE | _PAGE_SHARE)
+ #define PAGE_READ		__pgprot(_PAGE_BASE | _PAGE_READ)
+ #define PAGE_WRITE		__pgprot(_PAGE_BASE | _PAGE_READ | _PAGE_WRITE)
+ #define PAGE_EXEC		__pgprot(_PAGE_BASE | _PAGE_EXEC)
+@@ -54,11 +56,17 @@
+ #define _PAGE_KERNEL		(_PAGE_READ \
+ 				| _PAGE_WRITE \
+ 				| _PAGE_PRESENT \
++				| _PAGE_GLOBAL \
+ 				| _PAGE_ACCESSED \
+-				| _PAGE_DIRTY)
++				| _PAGE_DIRTY \
++				| _PAGE_CACHE \
++				| _PAGE_SHARE \
++				| _PAGE_BUF)
+ 
+ #define PAGE_KERNEL		__pgprot(_PAGE_KERNEL)
+ #define PAGE_KERNEL_EXEC	__pgprot(_PAGE_KERNEL | _PAGE_EXEC)
++#define PAGE_KERNEL_SO		__pgprot((_PAGE_KERNEL | _PAGE_SO) & \
++					~(_PAGE_CACHE | _PAGE_BUF))
+ 
+ #define PAGE_TABLE		__pgprot(_PAGE_TABLE)
+ 
+@@ -167,18 +175,18 @@
+ 
+ static inline struct page *pmd_page(pmd_t pmd)
+ {
+-	return pfn_to_page(pmd_val(pmd) >> _PAGE_PFN_SHIFT);
++	return pfn_to_page((pmd_val(pmd) & _PAGE_CHG_MASK) >> _PAGE_PFN_SHIFT);
+ }
+ 
+ static inline unsigned long pmd_page_vaddr(pmd_t pmd)
+ {
+-	return (unsigned long)pfn_to_virt(pmd_val(pmd) >> _PAGE_PFN_SHIFT);
++	return (unsigned long)pfn_to_virt((pmd_val(pmd) & _PAGE_CHG_MASK) >> _PAGE_PFN_SHIFT);
+ }
+ 
+ /* Yields the page frame number (PFN) of a page table entry */
+ static inline unsigned long pte_pfn(pte_t pte)
+ {
+-	return (pte_val(pte) >> _PAGE_PFN_SHIFT);
++	return ((pte_val(pte) & _PAGE_CHG_MASK) >> _PAGE_PFN_SHIFT);
+ }
+ 
+ #define pte_page(x)     pfn_to_page(pte_pfn(x))
+@@ -405,6 +413,32 @@
+ 	return ptep_test_and_clear_young(vma, address, ptep);
+ }
+ 
++#define __HAVE_PHYS_MEM_ACCESS_PROT
++struct file;
++extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
++				     unsigned long size, pgprot_t vma_prot);
++
++#define pgprot_noncached pgprot_noncached
++static inline pgprot_t pgprot_noncached(pgprot_t _prot)
++{
++	unsigned long prot = pgprot_val(_prot);
++
++	prot &= ~(_PAGE_CACHE | _PAGE_BUF);
++	prot |= _PAGE_SO;
++
++	return __pgprot(prot);
++}
++
++#define pgprot_writecombine pgprot_writecombine
++static inline pgprot_t pgprot_writecombine(pgprot_t _prot)
++{
++	unsigned long prot = pgprot_val(_prot);
++
++	prot &= ~(_PAGE_CACHE | _PAGE_BUF);
++
++	return __pgprot(prot);
++}
++
+ /*
+  * Encode and decode a swap entry
+  *
+diff -Nur linux-5.4.36/arch/riscv/include/asm/processor.h kernel/arch/riscv/include/asm/processor.h
+--- linux-5.4.36/arch/riscv/include/asm/processor.h	2020-04-29 14:33:25.000000000 +0000
++++ kernel/arch/riscv/include/asm/processor.h	2020-09-03 06:01:13.903989796 +0000
+@@ -32,6 +32,7 @@
+ 	unsigned long sp;	/* Kernel mode stack */
+ 	unsigned long s[12];	/* s[0]: frame pointer */
+ 	struct __riscv_d_ext_state fstate;
++	struct __riscv_v_state vstate;
+ };
+ 
+ #define INIT_THREAD {					\
+diff -Nur linux-5.4.36/arch/riscv/include/asm/ptrace.h kernel/arch/riscv/include/asm/ptrace.h
+--- linux-5.4.36/arch/riscv/include/asm/ptrace.h	2020-04-29 14:33:25.000000000 +0000
++++ kernel/arch/riscv/include/asm/ptrace.h	2020-09-03 06:01:13.903989796 +0000
+@@ -12,38 +12,43 @@
+ #ifndef __ASSEMBLY__
+ 
+ struct pt_regs {
+-	unsigned long sepc;
+-	unsigned long ra;
+-	unsigned long sp;
+-	unsigned long gp;
+-	unsigned long tp;
+-	unsigned long t0;
+-	unsigned long t1;
+-	unsigned long t2;
+-	unsigned long s0;
+-	unsigned long s1;
+-	unsigned long a0;
+-	unsigned long a1;
+-	unsigned long a2;
+-	unsigned long a3;
+-	unsigned long a4;
+-	unsigned long a5;
+-	unsigned long a6;
+-	unsigned long a7;
+-	unsigned long s2;
+-	unsigned long s3;
+-	unsigned long s4;
+-	unsigned long s5;
+-	unsigned long s6;
+-	unsigned long s7;
+-	unsigned long s8;
+-	unsigned long s9;
+-	unsigned long s10;
+-	unsigned long s11;
+-	unsigned long t3;
+-	unsigned long t4;
+-	unsigned long t5;
+-	unsigned long t6;
++	union {
++		struct user_regs_struct user_regs;
++		struct {
++			unsigned long sepc;
++			unsigned long ra;
++			unsigned long sp;
++			unsigned long gp;
++			unsigned long tp;
++			unsigned long t0;
++			unsigned long t1;
++			unsigned long t2;
++			unsigned long s0;
++			unsigned long s1;
++			unsigned long a0;
++			unsigned long a1;
++			unsigned long a2;
++			unsigned long a3;
++			unsigned long a4;
++			unsigned long a5;
++			unsigned long a6;
++			unsigned long a7;
++			unsigned long s2;
++			unsigned long s3;
++			unsigned long s4;
++			unsigned long s5;
++			unsigned long s6;
++			unsigned long s7;
++			unsigned long s8;
++			unsigned long s9;
++			unsigned long s10;
++			unsigned long s11;
++			unsigned long t3;
++			unsigned long t4;
++			unsigned long t5;
++			unsigned long t6;
++		};
++	};
+ 	/* Supervisor CSRs */
+ 	unsigned long sstatus;
+ 	unsigned long sbadaddr;
+diff -Nur linux-5.4.36/arch/riscv/include/asm/sbi.h kernel/arch/riscv/include/asm/sbi.h
+--- linux-5.4.36/arch/riscv/include/asm/sbi.h	2020-04-29 14:33:25.000000000 +0000
++++ kernel/arch/riscv/include/asm/sbi.h	2020-09-03 06:01:13.903989796 +0000
+@@ -17,6 +17,7 @@
+ #define SBI_REMOTE_SFENCE_VMA 6
+ #define SBI_REMOTE_SFENCE_VMA_ASID 7
+ #define SBI_SHUTDOWN 8
++#define SBI_PMU 0x09000001
+ 
+ #define SBI_CALL(which, arg0, arg1, arg2, arg3) ({		\
+ 	register uintptr_t a0 asm ("a0") = (uintptr_t)(arg0);	\
+@@ -94,4 +95,9 @@
+ 	SBI_CALL_4(SBI_REMOTE_SFENCE_VMA_ASID, hart_mask, start, size, asid);
+ }
+ 
++static inline void sbi_set_pmu(int start)
++{
++	SBI_CALL_1(SBI_PMU, start);
++}
++
+ #endif
+diff -Nur linux-5.4.36/arch/riscv/include/asm/switch_to.h kernel/arch/riscv/include/asm/switch_to.h
+--- linux-5.4.36/arch/riscv/include/asm/switch_to.h	2020-04-29 14:33:25.000000000 +0000
++++ kernel/arch/riscv/include/asm/switch_to.h	2020-09-03 06:01:13.904989796 +0000
+@@ -63,6 +63,52 @@
+ #define __switch_to_aux(__prev, __next) do { } while (0)
+ #endif
+ 
++#ifdef CONFIG_VECTOR
++extern void __vstate_save(struct task_struct *save_to);
++extern void __vstate_restore(struct task_struct *restore_from);
++
++static inline void __vstate_clean(struct pt_regs *regs)
++{
++	regs->sstatus |= (regs->sstatus & ~(SR_VS)) | SR_VS_CLEAN;
++}
++
++static inline void vstate_save(struct task_struct *task,
++			       struct pt_regs *regs)
++{
++	if ((regs->sstatus & SR_VS) == SR_VS_DIRTY) {
++		__vstate_save(task);
++		__vstate_clean(regs);
++	}
++}
++
++static inline void vstate_restore(struct task_struct *task,
++				  struct pt_regs *regs)
++{
++	if ((regs->sstatus & SR_VS) != SR_VS_OFF) {
++		__vstate_restore(task);
++		__vstate_clean(regs);
++	}
++}
++
++static inline void __switch_to_vector(struct task_struct *prev,
++				   struct task_struct *next)
++{
++	struct pt_regs *regs;
++
++	regs = task_pt_regs(prev);
++	if (unlikely(regs->sstatus & SR_SD))
++		vstate_save(prev, regs);
++	vstate_restore(next, task_pt_regs(next));
++}
++
++extern bool has_vector;
++#else
++#define has_vector false
++#define vstate_save(task, regs) do { } while (0)
++#define vstate_restore(task, regs) do { } while (0)
++#define __switch_to_vector(__prev, __next) do { } while (0)
++#endif
++
+ extern struct task_struct *__switch_to(struct task_struct *,
+ 				       struct task_struct *);
+ 
+@@ -72,6 +118,8 @@
+ 	struct task_struct *__next = (next);		\
+ 	if (has_fpu)					\
+ 		__switch_to_aux(__prev, __next);	\
++	if (has_vector)					\
++		__switch_to_vector(__prev, __next);	\
+ 	((last) = __switch_to(__prev, __next));		\
+ } while (0)
+ 
+diff -Nur linux-5.4.36/arch/riscv/include/asm/tlbflush.h kernel/arch/riscv/include/asm/tlbflush.h
+--- linux-5.4.36/arch/riscv/include/asm/tlbflush.h	2020-04-29 14:33:25.000000000 +0000
++++ kernel/arch/riscv/include/asm/tlbflush.h	2020-09-03 06:01:13.904989796 +0000
+@@ -12,12 +12,18 @@
+ 
+ static inline void local_flush_tlb_all(void)
+ {
++	sync_mmu_v1();
++	sync_mmu_v1();
++	sync_mmu_v1();
+ 	__asm__ __volatile__ ("sfence.vma" : : : "memory");
+ }
+ 
+ /* Flush one page from local TLB */
+ static inline void local_flush_tlb_page(unsigned long addr)
+ {
++	sync_mmu_v1();
++	sync_mmu_v1();
++	sync_mmu_v1();
+ 	__asm__ __volatile__ ("sfence.vma %0" : : "r" (addr) : "memory");
+ }
+ 
+@@ -44,7 +50,17 @@
+ static inline void flush_tlb_kernel_range(unsigned long start,
+ 	unsigned long end)
+ {
+-	flush_tlb_all();
++	start &= PAGE_MASK;
++	end   += PAGE_SIZE - 1;
++	end   &= PAGE_MASK;
++
++	while (start < end) {
++		sync_mmu_v1();
++		sync_mmu_v1();
++		sync_mmu_v1();
++		__asm__ __volatile__ ("sfence.vma %0" : : "r" (start) : "memory");
++		start += PAGE_SIZE;
++	}
+ }
+ 
+ #endif /* _ASM_RISCV_TLBFLUSH_H */
+diff -Nur linux-5.4.36/arch/riscv/include/uapi/asm/elf.h kernel/arch/riscv/include/uapi/asm/elf.h
+--- linux-5.4.36/arch/riscv/include/uapi/asm/elf.h	2020-04-29 14:33:25.000000000 +0000
++++ kernel/arch/riscv/include/uapi/asm/elf.h	2020-09-03 06:01:13.904989796 +0000
+@@ -24,6 +24,8 @@
+ typedef union __riscv_fp_state elf_fpregset_t;
+ #define ELF_NFPREG (sizeof(struct __riscv_d_ext_state) / sizeof(elf_fpreg_t))
+ 
++#define ELF_NVREG  (sizeof(struct __riscv_v_state) / sizeof(elf_greg_t))
++
+ #if __riscv_xlen == 64
+ #define ELF_RISCV_R_SYM(r_info)		ELF64_R_SYM(r_info)
+ #define ELF_RISCV_R_TYPE(r_info)	ELF64_R_TYPE(r_info)
+diff -Nur linux-5.4.36/arch/riscv/include/uapi/asm/hwcap.h kernel/arch/riscv/include/uapi/asm/hwcap.h
+--- linux-5.4.36/arch/riscv/include/uapi/asm/hwcap.h	2020-04-29 14:33:25.000000000 +0000
++++ kernel/arch/riscv/include/uapi/asm/hwcap.h	2020-09-03 06:01:13.904989796 +0000
+@@ -21,5 +21,6 @@
+ #define COMPAT_HWCAP_ISA_F	(1 << ('F' - 'A'))
+ #define COMPAT_HWCAP_ISA_D	(1 << ('D' - 'A'))
+ #define COMPAT_HWCAP_ISA_C	(1 << ('C' - 'A'))
++#define COMPAT_HWCAP_ISA_V	(1 << ('V' - 'A'))
+ 
+ #endif
+diff -Nur linux-5.4.36/arch/riscv/include/uapi/asm/ptrace.h kernel/arch/riscv/include/uapi/asm/ptrace.h
+--- linux-5.4.36/arch/riscv/include/uapi/asm/ptrace.h	2020-04-29 14:33:25.000000000 +0000
++++ kernel/arch/riscv/include/uapi/asm/ptrace.h	2020-09-03 06:01:13.905989796 +0000
+@@ -77,6 +77,15 @@
+ 	struct __riscv_q_ext_state q;
+ };
+ 
++struct __riscv_v_state {
++	__uint128_t v[32];
++	unsigned long vstart;
++	unsigned long vxsat;
++	unsigned long vxrm;
++	unsigned long vl;
++	unsigned long vtype;
++};
++
+ #endif /* __ASSEMBLY__ */
+ 
+ #endif /* _UAPI_ASM_RISCV_PTRACE_H */
+diff -Nur linux-5.4.36/arch/riscv/include/uapi/asm/sigcontext.h kernel/arch/riscv/include/uapi/asm/sigcontext.h
+--- linux-5.4.36/arch/riscv/include/uapi/asm/sigcontext.h	2020-04-29 14:33:25.000000000 +0000
++++ kernel/arch/riscv/include/uapi/asm/sigcontext.h	2020-09-03 06:01:13.905989796 +0000
+@@ -17,6 +17,7 @@
+ struct sigcontext {
+ 	struct user_regs_struct sc_regs;
+ 	union __riscv_fp_state sc_fpregs;
++	struct __riscv_v_state sc_vregs;
+ };
+ 
+ #endif /* _UAPI_ASM_RISCV_SIGCONTEXT_H */
+diff -Nur linux-5.4.36/arch/riscv/Kconfig kernel/arch/riscv/Kconfig
+--- linux-5.4.36/arch/riscv/Kconfig	2020-04-29 14:33:25.000000000 +0000
++++ kernel/arch/riscv/Kconfig	2020-09-14 01:45:17.782702016 +0000
+@@ -30,9 +30,11 @@
+ 	select GENERIC_STRNLEN_USER
+ 	select GENERIC_SMP_IDLE_THREAD
+ 	select GENERIC_ATOMIC64 if !64BIT
++	select GENERIC_ALLOCATOR
+ 	select HAVE_ARCH_AUDITSYSCALL
+ 	select HAVE_ASM_MODVERSIONS
+ 	select HAVE_MEMBLOCK_NODE_MAP
++	select DMA_DIRECT_REMAP
+ 	select HAVE_DMA_CONTIGUOUS
+ 	select HAVE_FUTEX_CMPXCHG if FUTEX
+ 	select HAVE_PERF_EVENTS
+@@ -50,10 +52,16 @@
+ 	select PCI_DOMAINS_GENERIC if PCI
+ 	select PCI_MSI if PCI
+ 	select RISCV_TIMER
++	select DW_APB_TIMER_OF
+ 	select GENERIC_IRQ_MULTI_HANDLER
+ 	select GENERIC_ARCH_TOPOLOGY if SMP
+ 	select ARCH_HAS_PTE_SPECIAL
+ 	select ARCH_HAS_MMIOWB
++	select ARCH_HAS_DMA_PREP_COHERENT
++	select ARCH_HAS_SYNC_DMA_FOR_CPU
++	select ARCH_HAS_SYNC_DMA_FOR_DEVICE
++	select ARCH_HAS_DMA_WRITE_COMBINE
++	select ARCH_HAS_DMA_MMAP_PGPROT
+ 	select HAVE_EBPF_JIT if 64BIT
+ 	select EDAC_SUPPORT
+ 	select ARCH_HAS_GIGANTIC_PAGE
+@@ -62,6 +70,7 @@
+ 	select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU
+ 	select HAVE_ARCH_MMAP_RND_BITS
+ 	select HAVE_COPY_THREAD_TLS
++	select RTC_DRV_XGENE
+ 
+ config ARCH_MMAP_RND_BITS_MIN
+ 	default 18 if 64BIT
+@@ -268,12 +277,41 @@
+ 
+ 	  If you don't know what to do here, say Y.
+ 
++config VECTOR
++	bool "VECTOR support"
++	default n
++	help
++	  Say N here if you want to disable all vector related procedure
++	  in the kernel.
++
++	  If you don't know what to do here, say Y.
++
+ endmenu
+ 
+ menu "Kernel features"
+ 
+ source "kernel/Kconfig.hz"
+ 
++config KEXEC
++	select KEXEC_CORE
++	bool "kexec system call"
++	---help---
++	  kexec is a system call that implements the ability to shutdown your
++	  current kernel, and to start another kernel.  It is like a reboot
++	  but it is independent of the system firmware.   And like a reboot
++	  you can start any kernel with it, not just Linux.
++
++config CRASH_DUMP
++	bool "Build kdump crash kernel"
++	help
++	  Generate crash dump after being started by kexec. This should
++	  be normally only set in special crash dump kernels which are
++	  loaded in the main kernel with kexec-tools into a specially
++	  reserved region and then later executed after a crash by
++	  kdump/kexec.
++
++	  For more details see Documentation/kdump/kdump.txt
++
+ endmenu
+ 
+ menu "Boot options"
+diff -Nur linux-5.4.36/arch/riscv/kernel/asm-offsets.c kernel/arch/riscv/kernel/asm-offsets.c
+--- linux-5.4.36/arch/riscv/kernel/asm-offsets.c	2020-04-29 14:33:25.000000000 +0000
++++ kernel/arch/riscv/kernel/asm-offsets.c	2020-09-03 06:01:13.905989796 +0000
+@@ -70,6 +70,45 @@
+ 	OFFSET(TASK_THREAD_F31, task_struct, thread.fstate.f[31]);
+ 	OFFSET(TASK_THREAD_FCSR, task_struct, thread.fstate.fcsr);
+ 
++	OFFSET(TASK_THREAD_V0,  task_struct, thread.vstate.v[0]);
++	OFFSET(TASK_THREAD_V1,  task_struct, thread.vstate.v[1]);
++	OFFSET(TASK_THREAD_V2,  task_struct, thread.vstate.v[2]);
++	OFFSET(TASK_THREAD_V3,  task_struct, thread.vstate.v[3]);
++	OFFSET(TASK_THREAD_V4,  task_struct, thread.vstate.v[4]);
++	OFFSET(TASK_THREAD_V5,  task_struct, thread.vstate.v[5]);
++	OFFSET(TASK_THREAD_V6,  task_struct, thread.vstate.v[6]);
++	OFFSET(TASK_THREAD_V7,  task_struct, thread.vstate.v[7]);
++	OFFSET(TASK_THREAD_V8,  task_struct, thread.vstate.v[8]);
++	OFFSET(TASK_THREAD_V9,  task_struct, thread.vstate.v[9]);
++	OFFSET(TASK_THREAD_V10, task_struct, thread.vstate.v[10]);
++	OFFSET(TASK_THREAD_V11, task_struct, thread.vstate.v[11]);
++	OFFSET(TASK_THREAD_V12, task_struct, thread.vstate.v[12]);
++	OFFSET(TASK_THREAD_V13, task_struct, thread.vstate.v[13]);
++	OFFSET(TASK_THREAD_V14, task_struct, thread.vstate.v[14]);
++	OFFSET(TASK_THREAD_V15, task_struct, thread.vstate.v[15]);
++	OFFSET(TASK_THREAD_V16, task_struct, thread.vstate.v[16]);
++	OFFSET(TASK_THREAD_V17, task_struct, thread.vstate.v[17]);
++	OFFSET(TASK_THREAD_V18, task_struct, thread.vstate.v[18]);
++	OFFSET(TASK_THREAD_V19, task_struct, thread.vstate.v[19]);
++	OFFSET(TASK_THREAD_V20, task_struct, thread.vstate.v[20]);
++	OFFSET(TASK_THREAD_V21, task_struct, thread.vstate.v[21]);
++	OFFSET(TASK_THREAD_V22, task_struct, thread.vstate.v[22]);
++	OFFSET(TASK_THREAD_V23, task_struct, thread.vstate.v[23]);
++	OFFSET(TASK_THREAD_V24, task_struct, thread.vstate.v[24]);
++	OFFSET(TASK_THREAD_V25, task_struct, thread.vstate.v[25]);
++	OFFSET(TASK_THREAD_V26, task_struct, thread.vstate.v[26]);
++	OFFSET(TASK_THREAD_V27, task_struct, thread.vstate.v[27]);
++	OFFSET(TASK_THREAD_V28, task_struct, thread.vstate.v[28]);
++	OFFSET(TASK_THREAD_V29, task_struct, thread.vstate.v[29]);
++	OFFSET(TASK_THREAD_V30, task_struct, thread.vstate.v[30]);
++	OFFSET(TASK_THREAD_V31, task_struct, thread.vstate.v[31]);
++	OFFSET(TASK_THREAD_VSTART, task_struct, thread.vstate.vstart);
++	OFFSET(TASK_THREAD_VXSAT, task_struct, thread.vstate.vxsat);
++	OFFSET(TASK_THREAD_VXRM, task_struct, thread.vstate.vxrm);
++	OFFSET(TASK_THREAD_VL, task_struct, thread.vstate.vl);
++	OFFSET(TASK_THREAD_VTYPE, task_struct, thread.vstate.vtype);
++	DEFINE(RISCV_VECTOR_VLENB, sizeof(__uint128_t));
++
+ 	DEFINE(PT_SIZE, sizeof(struct pt_regs));
+ 	OFFSET(PT_SEPC, pt_regs, sepc);
+ 	OFFSET(PT_RA, pt_regs, ra);
+@@ -171,6 +210,7 @@
+ 		- offsetof(struct task_struct, thread.ra)
+ 	);
+ 
++	/* Float Point */
+ 	DEFINE(TASK_THREAD_F0_F0,
+ 		  offsetof(struct task_struct, thread.fstate.f[0])
+ 		- offsetof(struct task_struct, thread.fstate.f[0])
+@@ -304,6 +344,156 @@
+ 		- offsetof(struct task_struct, thread.fstate.f[0])
+ 	);
+ 
++	/* Vector */
++	DEFINE(TASK_THREAD_V0_V0,
++		  offsetof(struct task_struct, thread.vstate.v[0])
++		- offsetof(struct task_struct, thread.vstate.v[0])
++	);
++	DEFINE(TASK_THREAD_V1_V0,
++		  offsetof(struct task_struct, thread.vstate.v[1])
++		- offsetof(struct task_struct, thread.vstate.v[0])
++	);
++	DEFINE(TASK_THREAD_V2_V0,
++		  offsetof(struct task_struct, thread.vstate.v[2])
++		- offsetof(struct task_struct, thread.vstate.v[0])
++	);
++	DEFINE(TASK_THREAD_V3_V0,
++		  offsetof(struct task_struct, thread.vstate.v[3])
++		- offsetof(struct task_struct, thread.vstate.v[0])
++	);
++	DEFINE(TASK_THREAD_V4_V0,
++		  offsetof(struct task_struct, thread.vstate.v[4])
++		- offsetof(struct task_struct, thread.vstate.v[0])
++	);
++	DEFINE(TASK_THREAD_V5_V0,
++		  offsetof(struct task_struct, thread.vstate.v[5])
++		- offsetof(struct task_struct, thread.vstate.v[0])
++	);
++	DEFINE(TASK_THREAD_V6_V0,
++		  offsetof(struct task_struct, thread.vstate.v[6])
++		- offsetof(struct task_struct, thread.vstate.v[0])
++	);
++	DEFINE(TASK_THREAD_V7_V0,
++		  offsetof(struct task_struct, thread.vstate.v[7])
++		- offsetof(struct task_struct, thread.vstate.v[0])
++	);
++	DEFINE(TASK_THREAD_V8_V0,
++		  offsetof(struct task_struct, thread.vstate.v[8])
++		- offsetof(struct task_struct, thread.vstate.v[0])
++	);
++	DEFINE(TASK_THREAD_V9_V0,
++		  offsetof(struct task_struct, thread.vstate.v[9])
++		- offsetof(struct task_struct, thread.vstate.v[0])
++	);
++	DEFINE(TASK_THREAD_V10_V0,
++		  offsetof(struct task_struct, thread.vstate.v[10])
++		- offsetof(struct task_struct, thread.vstate.v[0])
++	);
++	DEFINE(TASK_THREAD_V11_V0,
++		  offsetof(struct task_struct, thread.vstate.v[11])
++		- offsetof(struct task_struct, thread.vstate.v[0])
++	);
++	DEFINE(TASK_THREAD_V12_V0,
++		  offsetof(struct task_struct, thread.vstate.v[12])
++		- offsetof(struct task_struct, thread.vstate.v[0])
++	);
++	DEFINE(TASK_THREAD_V13_V0,
++		  offsetof(struct task_struct, thread.vstate.v[13])
++		- offsetof(struct task_struct, thread.vstate.v[0])
++	);
++	DEFINE(TASK_THREAD_V14_V0,
++		  offsetof(struct task_struct, thread.vstate.v[14])
++		- offsetof(struct task_struct, thread.vstate.v[0])
++	);
++	DEFINE(TASK_THREAD_V15_V0,
++		  offsetof(struct task_struct, thread.vstate.v[15])
++		- offsetof(struct task_struct, thread.vstate.v[0])
++	);
++	DEFINE(TASK_THREAD_V16_V0,
++		  offsetof(struct task_struct, thread.vstate.v[16])
++		- offsetof(struct task_struct, thread.vstate.v[0])
++	);
++	DEFINE(TASK_THREAD_V17_V0,
++		  offsetof(struct task_struct, thread.vstate.v[17])
++		- offsetof(struct task_struct, thread.vstate.v[0])
++	);
++	DEFINE(TASK_THREAD_V18_V0,
++		  offsetof(struct task_struct, thread.vstate.v[18])
++		- offsetof(struct task_struct, thread.vstate.v[0])
++	);
++	DEFINE(TASK_THREAD_V19_V0,
++		  offsetof(struct task_struct, thread.vstate.v[19])
++		- offsetof(struct task_struct, thread.vstate.v[0])
++	);
++	DEFINE(TASK_THREAD_V20_V0,
++		  offsetof(struct task_struct, thread.vstate.v[20])
++		- offsetof(struct task_struct, thread.vstate.v[0])
++	);
++	DEFINE(TASK_THREAD_V21_V0,
++		  offsetof(struct task_struct, thread.vstate.v[21])
++		- offsetof(struct task_struct, thread.vstate.v[0])
++	);
++	DEFINE(TASK_THREAD_V22_V0,
++		  offsetof(struct task_struct, thread.vstate.v[22])
++		- offsetof(struct task_struct, thread.vstate.v[0])
++	);
++	DEFINE(TASK_THREAD_V23_V0,
++		  offsetof(struct task_struct, thread.vstate.v[23])
++		- offsetof(struct task_struct, thread.vstate.v[0])
++	);
++	DEFINE(TASK_THREAD_V24_V0,
++		  offsetof(struct task_struct, thread.vstate.v[24])
++		- offsetof(struct task_struct, thread.vstate.v[0])
++	);
++	DEFINE(TASK_THREAD_V25_V0,
++		  offsetof(struct task_struct, thread.vstate.v[25])
++		- offsetof(struct task_struct, thread.vstate.v[0])
++	);
++	DEFINE(TASK_THREAD_V26_V0,
++		  offsetof(struct task_struct, thread.vstate.v[26])
++		- offsetof(struct task_struct, thread.vstate.v[0])
++	);
++	DEFINE(TASK_THREAD_V27_V0,
++		  offsetof(struct task_struct, thread.vstate.v[27])
++		- offsetof(struct task_struct, thread.vstate.v[0])
++	);
++	DEFINE(TASK_THREAD_V28_V0,
++		  offsetof(struct task_struct, thread.vstate.v[28])
++		- offsetof(struct task_struct, thread.vstate.v[0])
++	);
++	DEFINE(TASK_THREAD_V29_V0,
++		  offsetof(struct task_struct, thread.vstate.v[29])
++		- offsetof(struct task_struct, thread.vstate.v[0])
++	);
++	DEFINE(TASK_THREAD_V30_V0,
++		  offsetof(struct task_struct, thread.vstate.v[30])
++		- offsetof(struct task_struct, thread.vstate.v[0])
++	);
++	DEFINE(TASK_THREAD_V31_V0,
++		  offsetof(struct task_struct, thread.vstate.v[31])
++		- offsetof(struct task_struct, thread.vstate.v[0])
++	);
++	DEFINE(TASK_THREAD_VSTART_V0,
++		  offsetof(struct task_struct, thread.vstate.vstart)
++		- offsetof(struct task_struct, thread.vstate.v[0])
++	);
++	DEFINE(TASK_THREAD_VXSAT_V0,
++		  offsetof(struct task_struct, thread.vstate.vxsat)
++		- offsetof(struct task_struct, thread.vstate.v[0])
++	);
++	DEFINE(TASK_THREAD_VXRM_V0,
++		  offsetof(struct task_struct, thread.vstate.vxrm)
++		- offsetof(struct task_struct, thread.vstate.v[0])
++	);
++	DEFINE(TASK_THREAD_VL_V0,
++		  offsetof(struct task_struct, thread.vstate.vl)
++		- offsetof(struct task_struct, thread.vstate.v[0])
++	);
++	DEFINE(TASK_THREAD_VTYPE_V0,
++		  offsetof(struct task_struct, thread.vstate.vtype)
++		- offsetof(struct task_struct, thread.vstate.v[0])
++	);
++
+ 	/*
+ 	 * We allocate a pt_regs on the stack when entering the kernel.  This
+ 	 * ensures the alignment is sane.
+diff -Nur linux-5.4.36/arch/riscv/kernel/cpu.c kernel/arch/riscv/kernel/cpu.c
+--- linux-5.4.36/arch/riscv/kernel/cpu.c	2020-04-29 14:33:25.000000000 +0000
++++ kernel/arch/riscv/kernel/cpu.c	2020-09-03 06:01:13.905989796 +0000
+@@ -48,7 +48,7 @@
+ 
+ static void print_isa(struct seq_file *f, const char *orig_isa)
+ {
+-	static const char *ext = "mafdcsu";
++	static const char *ext = "mafdcvsu";
+ 	const char *isa = orig_isa;
+ 	const char *e;
+ 
+diff -Nur linux-5.4.36/arch/riscv/kernel/cpufeature.c kernel/arch/riscv/kernel/cpufeature.c
+--- linux-5.4.36/arch/riscv/kernel/cpufeature.c	2020-04-29 14:33:25.000000000 +0000
++++ kernel/arch/riscv/kernel/cpufeature.c	2020-09-03 06:01:13.905989796 +0000
+@@ -17,6 +17,10 @@
+ bool has_fpu __read_mostly;
+ #endif
+ 
++#ifdef CONFIG_VECTOR
++bool has_vector __read_mostly;
++#endif
++
+ void riscv_fill_hwcap(void)
+ {
+ 	struct device_node *node;
+@@ -30,6 +34,7 @@
+ 	isa2hwcap['f'] = isa2hwcap['F'] = COMPAT_HWCAP_ISA_F;
+ 	isa2hwcap['d'] = isa2hwcap['D'] = COMPAT_HWCAP_ISA_D;
+ 	isa2hwcap['c'] = isa2hwcap['C'] = COMPAT_HWCAP_ISA_C;
++	isa2hwcap['v'] = isa2hwcap['V'] = COMPAT_HWCAP_ISA_V;
+ 
+ 	elf_hwcap = 0;
+ 
+@@ -44,7 +49,8 @@
+ 			continue;
+ 		}
+ 
+-		for (i = 0; i < strlen(isa); ++i)
++		/* skip "rv64" */
++		for (i = 4; i < strlen(isa); ++i)
+ 			this_hwcap |= isa2hwcap[(unsigned char)(isa[i])];
+ 
+ 		/*
+@@ -71,4 +77,9 @@
+ 	if (elf_hwcap & (COMPAT_HWCAP_ISA_F | COMPAT_HWCAP_ISA_D))
+ 		has_fpu = true;
+ #endif
++
++#ifdef CONFIG_VECTOR
++	if (elf_hwcap & COMPAT_HWCAP_ISA_V)
++		has_vector = true;
++#endif
+ }
+diff -Nur linux-5.4.36/arch/riscv/kernel/cpu-reset.h kernel/arch/riscv/kernel/cpu-reset.h
+--- linux-5.4.36/arch/riscv/kernel/cpu-reset.h	1970-01-01 00:00:00.000000000 +0000
++++ kernel/arch/riscv/kernel/cpu-reset.h	2020-09-03 06:01:13.905989796 +0000
+@@ -0,0 +1,58 @@
++/*
++ * CPU reset routines
++ *
++ * Copyright (C) 2020-2025 Alibaba Group Holding Limited
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#ifndef _RISCV_CPU_RESET_H
++#define _RISCV_CPU_RESET_H
++
++extern struct resource *standard_resources;
++void __cpu_soft_restart(unsigned long entry, unsigned long arg0, unsigned long arg1,
++								unsigned long arg2);
++
++__attribute__ ((optimize("-O0"))) static void __noreturn cpu_soft_restart(unsigned long entry,
++					       unsigned long arg0,
++					       unsigned long arg1,
++					       unsigned long arg2)
++{
++	typeof(__cpu_soft_restart) *restart;
++	pgd_t *idmap_pgd;
++	pmd_t *idmap_pmd;
++	long pa_start, pa_end;
++	long i, j, m, n, delta;
++	long idmap_pmd_size;
++
++	pa_start = standard_resources->start;
++	pa_end = standard_resources->end;
++
++	idmap_pmd_size = (pa_end - pa_start + 1) / PMD_SIZE * sizeof(pmd_t);
++
++	idmap_pgd = (pgd_t *)__va((csr_read(CSR_SATP) & ((1UL<<44)-1))<< PAGE_SHIFT);
++	idmap_pmd = (pmd_t *)__get_free_pages(GFP_KERNEL, get_order(idmap_pmd_size));
++
++	m = (pa_start >> PGDIR_SHIFT) % PTRS_PER_PGD;
++	n = (pa_end >> PGDIR_SHIFT) % PTRS_PER_PGD;
++
++	for (i = 0; m <= n; m++,i++)
++		idmap_pgd[m] = pfn_pgd(PFN_DOWN(__pa(idmap_pmd)) + i,
++				__pgprot(_PAGE_TABLE));
++
++	m = pa_start >> PMD_SHIFT;
++	n = (pa_end + 1) >> PMD_SHIFT;
++	delta = n - m;
++
++	for (i = (pa_start + 1) % PMD_SIZE,j=0; i <= delta; i++,j++)
++		idmap_pmd[i] = pfn_pmd(PFN_DOWN(pa_start + j * PMD_SIZE),
++				__pgprot(pgprot_val(PAGE_KERNEL) | _PAGE_EXEC));
++
++	restart = (void *)__pa_symbol(__cpu_soft_restart);
++	restart(entry, arg0, arg1, arg2);
++	unreachable();
++}
++
++#endif
+diff -Nur linux-5.4.36/arch/riscv/kernel/cpu-reset.S kernel/arch/riscv/kernel/cpu-reset.S
+--- linux-5.4.36/arch/riscv/kernel/cpu-reset.S	1970-01-01 00:00:00.000000000 +0000
++++ kernel/arch/riscv/kernel/cpu-reset.S	2020-09-03 06:01:13.905989796 +0000
+@@ -0,0 +1,23 @@
++/*
++ * CPU reset routines
++ *
++ * Copyright (C) 2020-2025 Alibaba Group Holding Limited
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include <linux/linkage.h>
++
++ENTRY(__cpu_soft_restart)
++		fence
++		fence.i
++		sfence.vma
++		mv	s1, a0		//entry
++		mv	a0, a1		//arg0
++		mv	a1, a2		//arg1
++		mv	a2, a3		//arg2
++		jr s1
++		ebreak
++ENDPROC(__cpu_soft_restart)
+diff -Nur linux-5.4.36/arch/riscv/kernel/crash_dump.c kernel/arch/riscv/kernel/crash_dump.c
+--- linux-5.4.36/arch/riscv/kernel/crash_dump.c	1970-01-01 00:00:00.000000000 +0000
++++ kernel/arch/riscv/kernel/crash_dump.c	2020-09-03 06:01:13.905989796 +0000
+@@ -0,0 +1,69 @@
++/*
++ * Routines for doing kexec-based kdump
++ *
++ * Copyright (C) 2020-2025 Alibaba Group Holding Limited
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include <linux/crash_dump.h>
++#include <linux/errno.h>
++#include <linux/io.h>
++#include <linux/memblock.h>
++#include <linux/uaccess.h>
++
++/**
++ * copy_oldmem_page() - copy one page from old kernel memory
++ * @pfn: page frame number to be copied
++ * @buf: buffer where the copied page is placed
++ * @csize: number of bytes to copy
++ * @offset: offset in bytes into the page
++ * @userbuf: if set, @buf is in a user address space
++ *
++ * This function copies one page from old kernel memory into buffer pointed by
++ * @buf. If @buf is in userspace, set @userbuf to %1. Returns number of bytes
++ * copied or negative error in case of failure.
++ */
++ssize_t copy_oldmem_page(unsigned long pfn, char *buf,
++			 size_t csize, unsigned long offset,
++			 int userbuf)
++{
++	void *vaddr;
++
++	if (!csize)
++		return 0;
++
++	vaddr = memremap(__pfn_to_phys(pfn), PAGE_SIZE, MEMREMAP_WB);
++	if (!vaddr)
++		return -ENOMEM;
++
++	if (userbuf) {
++		if (copy_to_user((char __user *)buf, vaddr + offset, csize)) {
++			memunmap(vaddr);
++			return -EFAULT;
++		}
++	} else {
++		memcpy(buf, vaddr + offset, csize);
++	}
++
++	memunmap(vaddr);
++
++	return csize;
++}
++
++/**
++ * elfcorehdr_read - read from ELF core header
++ * @buf: buffer where the data is placed
++ * @count: number of bytes to read
++ * @ppos: address in the memory
++ *
++ * This function reads @count bytes from elf core header which exists
++ * on crash dump kernel's memory.
++ */
++ssize_t elfcorehdr_read(char *buf, size_t count, u64 *ppos)
++{
++	memcpy(buf, phys_to_virt((phys_addr_t)*ppos), count);
++	return count;
++}
+diff -Nur linux-5.4.36/arch/riscv/kernel/entry.S kernel/arch/riscv/kernel/entry.S
+--- linux-5.4.36/arch/riscv/kernel/entry.S	2020-04-29 14:33:25.000000000 +0000
++++ kernel/arch/riscv/kernel/entry.S	2020-09-03 06:01:13.905989796 +0000
+@@ -76,7 +76,7 @@
+ 	 * Disable the FPU to detect illegal usage of floating point in kernel
+ 	 * space.
+ 	 */
+-	li t0, SR_SUM | SR_FS
++	li t0, SR_SUM | SR_FS | SR_VS
+ 
+ 	REG_L s0, TASK_TI_USER_SP(tp)
+ 	csrrc s1, CSR_SSTATUS, t0
+diff -Nur linux-5.4.36/arch/riscv/kernel/head.S kernel/arch/riscv/kernel/head.S
+--- linux-5.4.36/arch/riscv/kernel/head.S	2020-04-29 14:33:25.000000000 +0000
++++ kernel/arch/riscv/kernel/head.S	2020-09-03 06:01:13.905989796 +0000
+@@ -60,7 +60,7 @@
+ 	 * Disable FPU to detect illegal usage of
+ 	 * floating point in kernel space
+ 	 */
+-	li t0, SR_FS
++	li t0, SR_FS | SR_VS
+ 	csrc CSR_SSTATUS, t0
+ 
+ #ifdef CONFIG_SMP
+diff -Nur linux-5.4.36/arch/riscv/kernel/irq.c kernel/arch/riscv/kernel/irq.c
+--- linux-5.4.36/arch/riscv/kernel/irq.c	2020-04-29 14:33:25.000000000 +0000
++++ kernel/arch/riscv/kernel/irq.c	2020-09-03 06:01:13.905989796 +0000
+@@ -17,6 +17,7 @@
+ #define INTERRUPT_CAUSE_SOFTWARE	IRQ_S_SOFT
+ #define INTERRUPT_CAUSE_TIMER		IRQ_S_TIMER
+ #define INTERRUPT_CAUSE_EXTERNAL	IRQ_S_EXT
++#define INTERRUPT_CAUSE_PMU		IRQ_S_PMU
+ 
+ int arch_show_interrupts(struct seq_file *p, int prec)
+ {
+@@ -24,6 +25,7 @@
+ 	return 0;
+ }
+ 
++extern int riscv_pmu_handle_irq(void);
+ asmlinkage __visible void __irq_entry do_IRQ(struct pt_regs *regs)
+ {
+ 	struct pt_regs *old_regs = set_irq_regs(regs);
+@@ -33,6 +35,11 @@
+ 	case INTERRUPT_CAUSE_TIMER:
+ 		riscv_timer_interrupt();
+ 		break;
++#ifdef CONFIG_THEAD_XT_V1_PMU
++	case INTERRUPT_CAUSE_PMU:
++		riscv_pmu_handle_irq();
++		break;
++#endif
+ #ifdef CONFIG_SMP
+ 	case INTERRUPT_CAUSE_SOFTWARE:
+ 		/*
+diff -Nur linux-5.4.36/arch/riscv/kernel/machine_kexec.c kernel/arch/riscv/kernel/machine_kexec.c
+--- linux-5.4.36/arch/riscv/kernel/machine_kexec.c	1970-01-01 00:00:00.000000000 +0000
++++ kernel/arch/riscv/kernel/machine_kexec.c	2020-09-03 06:01:13.906989796 +0000
+@@ -0,0 +1,163 @@
++/*
++ * kexec for riscv
++ *
++ * Copyright (C) 2020-2025 Alibaba Group Holding Limited
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include <linux/interrupt.h>
++#include <linux/irq.h>
++#include <linux/kernel.h>
++#include <linux/kexec.h>
++#include <linux/page-flags.h>
++#include <linux/smp.h>
++
++#include <asm/cacheflush.h>
++#include <asm/mmu.h>
++#include <asm/mmu_context.h>
++#include <asm/page.h>
++
++#include "cpu-reset.h"
++
++/* Global variables for the riscv_relocate_new_kernel routine. */
++extern const unsigned char riscv_relocate_new_kernel[];
++extern const unsigned long riscv_relocate_new_kernel_size;
++
++/*
++ * kexec_image_info - For debugging output.
++ */
++#define kexec_image_info(_i) _kexec_image_info(__func__, __LINE__, _i)
++static void _kexec_image_info(const char *func, int line,
++	const struct kimage *kimage)
++{
++	unsigned long i;
++
++	pr_debug("%s:%d:\n", func, line);
++	pr_debug("  kexec kimage info:\n");
++	pr_debug("    type:        %d\n", kimage->type);
++	pr_debug("    start:       0x%lx\n", kimage->start);
++	pr_debug("    head:        0x%lx\n", kimage->head);
++	pr_debug("    nr_segments: %lu\n", kimage->nr_segments);
++
++	for (i = 0; i < kimage->nr_segments; i++) {
++		pr_debug("      segment[%lu]: %016lx - %016lx, 0x%lx bytes, %lu pages\n",
++			i,
++			kimage->segment[i].mem,
++			kimage->segment[i].mem + kimage->segment[i].memsz,
++			kimage->segment[i].memsz,
++			kimage->segment[i].memsz /  PAGE_SIZE);
++	}
++}
++
++void machine_kexec_cleanup(struct kimage *kimage)
++{
++	/* Empty routine needed to avoid build errors. */
++}
++
++/**
++ * machine_kexec_prepare - Prepare for a kexec reboot.
++ *
++ * Called from the core kexec code when a kernel image is loaded.
++ * Forbid loading a kexec kernel if we have no way of hotplugging cpus or cpus
++ * are stuck in the kernel. This avoids a panic once we hit machine_kexec().
++ */
++int machine_kexec_prepare(struct kimage *kimage)
++{
++	kexec_image_info(kimage);
++
++	return 0;
++}
++
++/**
++ * machine_kexec - Do the kexec reboot.
++ *
++ * Called from the core kexec code for a sys_reboot with LINUX_REBOOT_CMD_KEXEC.
++ */
++void machine_kexec(struct kimage *kimage)
++{
++	phys_addr_t reboot_code_buffer_phys;
++	void *reboot_code_buffer;
++
++	reboot_code_buffer_phys = page_to_phys(kimage->control_code_page);
++	reboot_code_buffer = phys_to_virt(reboot_code_buffer_phys);
++
++	pr_debug("%s:%d: control_code_page:        0x%lx\n", __func__, __LINE__,
++		(long)kimage->control_code_page);
++	pr_debug("%s:%d: reboot_code_buffer_phys:  0x%lx\n", __func__, __LINE__,
++		(long)reboot_code_buffer_phys);
++	pr_debug("%s:%d: reboot_code_buffer:       0x%lx\n", __func__, __LINE__,
++		(long)reboot_code_buffer);
++	pr_debug("%s:%d: relocate_new_kernel:      0x%lx\n", __func__, __LINE__,
++		(long)riscv_relocate_new_kernel);
++	pr_debug("%s:%d: relocate_new_kernel_size: 0x%lx(%lu) bytes\n",
++		__func__, __LINE__, riscv_relocate_new_kernel_size,
++		riscv_relocate_new_kernel_size);
++
++	/*
++	 * Copy riscv_relocate_new_kernel to the reboot_code_buffer for use
++	 * after the kernel is shut down.
++	 */
++	memcpy(reboot_code_buffer, riscv_relocate_new_kernel,
++		riscv_relocate_new_kernel_size);
++
++	pr_info("Bye!\n");
++
++	local_irq_disable();
++
++	cpu_soft_restart(reboot_code_buffer_phys, kimage->head,
++				kimage->segment[0].mem, kimage->segment[2].mem);
++
++	BUG(); /* Should never get here. */
++}
++
++static void machine_kexec_mask_interrupts(void)
++{
++	unsigned int i;
++	struct irq_desc *desc;
++
++	for_each_irq_desc(i, desc) {
++		struct irq_chip *chip;
++		int ret;
++
++		chip = irq_desc_get_chip(desc);
++		if (!chip)
++			continue;
++
++		/*
++		 * First try to remove the active state. If this
++		 * fails, try to EOI the interrupt.
++		 */
++		ret = irq_set_irqchip_state(i, IRQCHIP_STATE_ACTIVE, false);
++
++		if (ret && irqd_irq_inprogress(&desc->irq_data) &&
++		    chip->irq_eoi)
++			chip->irq_eoi(&desc->irq_data);
++
++		if (chip->irq_mask)
++			chip->irq_mask(&desc->irq_data);
++
++		if (chip->irq_disable && !irqd_irq_disabled(&desc->irq_data))
++			chip->irq_disable(&desc->irq_data);
++	}
++}
++
++/**
++ * machine_crash_shutdown - shutdown non-crashing cpus and save registers
++ */
++extern void crash_smp_send_stop(void);
++void machine_crash_shutdown(struct pt_regs *regs)
++{
++	local_irq_disable();
++
++	/* shutdown non-crashing cpus */
++	crash_smp_send_stop();
++
++	/* for crashing cpu */
++	crash_save_cpu(regs, smp_processor_id());
++	machine_kexec_mask_interrupts();
++
++	pr_info("Starting crashdump kernel...\n");
++}
+diff -Nur linux-5.4.36/arch/riscv/kernel/Makefile kernel/arch/riscv/kernel/Makefile
+--- linux-5.4.36/arch/riscv/kernel/Makefile	2020-04-29 14:33:25.000000000 +0000
++++ kernel/arch/riscv/kernel/Makefile	2020-09-03 06:01:13.905989796 +0000
+@@ -30,6 +30,7 @@
+ obj-y	+= vdso/
+ 
+ obj-$(CONFIG_FPU)		+= fpu.o
++obj-$(CONFIG_VECTOR)		+= vector.o
+ obj-$(CONFIG_SMP)		+= smpboot.o
+ obj-$(CONFIG_SMP)		+= smp.o
+ obj-$(CONFIG_MODULES)		+= module.o
+@@ -42,4 +43,8 @@
+ obj-$(CONFIG_PERF_EVENTS)	+= perf_callchain.o
+ obj-$(CONFIG_HAVE_PERF_REGS)	+= perf_regs.o
+ 
++obj-$(CONFIG_KEXEC_CORE)        += machine_kexec.o relocate_kernel.o    \
++						cpu-reset.o
++obj-$(CONFIG_CRASH_DUMP)        += crash_dump.o
++
+ clean:
+diff -Nur linux-5.4.36/arch/riscv/kernel/module.c kernel/arch/riscv/kernel/module.c
+--- linux-5.4.36/arch/riscv/kernel/module.c	2020-04-29 14:33:25.000000000 +0000
++++ kernel/arch/riscv/kernel/module.c	2020-09-03 06:01:13.906989796 +0000
+@@ -253,7 +253,7 @@
+ 	pr_err(
+ 	  "%s: The unexpected relocation type 'R_RISCV_ALIGN' from PC = %p\n",
+ 	  me->name, location);
+-	return -EINVAL;
++	return 0; /* Do not return -EINVAL when relocation type is R_RISCV_ALIGN */
+ }
+ 
+ static int apply_r_riscv_add32_rela(struct module *me, u32 *location,
+diff -Nur linux-5.4.36/arch/riscv/kernel/perf_event.c kernel/arch/riscv/kernel/perf_event.c
+--- linux-5.4.36/arch/riscv/kernel/perf_event.c	2020-04-29 14:33:25.000000000 +0000
++++ kernel/arch/riscv/kernel/perf_event.c	2020-09-03 06:01:13.906989796 +0000
+@@ -477,9 +477,9 @@
+ 		if (of_id)
+ 			riscv_pmu = of_id->data;
+ 		of_node_put(node);
++		perf_pmu_register(riscv_pmu->pmu, "cpu", PERF_TYPE_RAW);
+ 	}
+ 
+-	perf_pmu_register(riscv_pmu->pmu, "cpu", PERF_TYPE_RAW);
+ 	return 0;
+ }
+ arch_initcall(init_hw_perf_events);
+diff -Nur linux-5.4.36/arch/riscv/kernel/process.c kernel/arch/riscv/kernel/process.c
+--- linux-5.4.36/arch/riscv/kernel/process.c	2020-04-29 14:33:25.000000000 +0000
++++ kernel/arch/riscv/kernel/process.c	2020-09-03 06:01:13.906989796 +0000
+@@ -74,6 +74,12 @@
+ 		 */
+ 		fstate_restore(current, regs);
+ 	}
++
++	if (has_vector) {
++		regs->sstatus |= SR_VS_INITIAL;
++		vstate_restore(current, regs);
++	}
++
+ 	regs->sepc = pc;
+ 	regs->sp = sp;
+ 	set_fs(USER_DS);
+diff -Nur linux-5.4.36/arch/riscv/kernel/ptrace.c kernel/arch/riscv/kernel/ptrace.c
+--- linux-5.4.36/arch/riscv/kernel/ptrace.c	2020-04-29 14:33:25.000000000 +0000
++++ kernel/arch/riscv/kernel/ptrace.c	2020-09-03 06:01:13.906989796 +0000
+@@ -26,6 +26,9 @@
+ #ifdef CONFIG_FPU
+ 	REGSET_F,
+ #endif
++#ifdef CONFIG_VECTOR
++	REGSET_V,
++#endif
+ };
+ 
+ static int riscv_gpr_get(struct task_struct *target,
+@@ -92,6 +95,34 @@
+ }
+ #endif
+ 
++#ifdef CONFIG_VECTOR
++static int riscv_vr_get(struct task_struct *target,
++			 const struct user_regset *regset,
++			 unsigned int pos, unsigned int count,
++			 void *kbuf, void __user *ubuf)
++{
++	int ret;
++	struct __riscv_v_state *vstate = &target->thread.vstate;
++
++	ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, vstate, 0,
++				  offsetof(struct __riscv_v_state, vtype));
++	return ret;
++}
++
++static int riscv_vr_set(struct task_struct *target,
++			 const struct user_regset *regset,
++			 unsigned int pos, unsigned int count,
++			 const void *kbuf, const void __user *ubuf)
++{
++	int ret;
++	struct __riscv_v_state *vstate = &target->thread.vstate;
++
++	ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, vstate, 0,
++				 offsetof(struct __riscv_v_state, vtype));
++	return ret;
++}
++#endif
++
+ static const struct user_regset riscv_user_regset[] = {
+ 	[REGSET_X] = {
+ 		.core_note_type = NT_PRSTATUS,
+@@ -111,6 +142,16 @@
+ 		.set = &riscv_fpr_set,
+ 	},
+ #endif
++#ifdef CONFIG_VECTOR
++	[REGSET_V] = {
++		.core_note_type = NT_RISCV_VECTOR,
++		.n = ELF_NVREG,
++		.size = sizeof(elf_greg_t),
++		.align = sizeof(elf_greg_t),
++		.get = &riscv_vr_get,
++		.set = &riscv_vr_set,
++	},
++#endif
+ };
+ 
+ static const struct user_regset_view riscv_user_native_view = {
+diff -Nur linux-5.4.36/arch/riscv/kernel/relocate_kernel.S kernel/arch/riscv/kernel/relocate_kernel.S
+--- linux-5.4.36/arch/riscv/kernel/relocate_kernel.S	1970-01-01 00:00:00.000000000 +0000
++++ kernel/arch/riscv/kernel/relocate_kernel.S	2020-09-03 06:01:13.906989796 +0000
+@@ -0,0 +1,32 @@
++/*
++ * kexec for riscv
++ *
++ * Copyright (C) 2020-2025 Alibaba Group Holding Limited
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include <linux/kexec.h>
++#include <linux/linkage.h>
++
++#include <asm/kexec.h>
++#include <asm/page.h>
++
++ENTRY(riscv_relocate_new_kernel)
++	/* Start new image. */
++	mv	s1, a1
++	mv	a0, zero
++	mv	a1, a2
++	mv	a2, zero
++	mv	a3, zero
++	jr	s1
++ENDPROC(riscv_relocate_new_kernel)
++
++.Lcopy_end:
++.org	KEXEC_CONTROL_PAGE_SIZE
++
++.globl riscv_relocate_new_kernel_size
++riscv_relocate_new_kernel_size:
++	.quad	.Lcopy_end - riscv_relocate_new_kernel
+diff -Nur linux-5.4.36/arch/riscv/kernel/reset.c kernel/arch/riscv/kernel/reset.c
+--- linux-5.4.36/arch/riscv/kernel/reset.c	2020-04-29 14:33:25.000000000 +0000
++++ kernel/arch/riscv/kernel/reset.c	2020-09-03 06:01:13.906989796 +0000
+@@ -31,3 +31,7 @@
+ {
+ 	pm_power_off();
+ }
++
++void machine_shutdown(void)
++{
++}
+diff -Nur linux-5.4.36/arch/riscv/kernel/setup.c kernel/arch/riscv/kernel/setup.c
+--- linux-5.4.36/arch/riscv/kernel/setup.c	2020-04-29 14:33:25.000000000 +0000
++++ kernel/arch/riscv/kernel/setup.c	2020-09-03 06:01:13.906989796 +0000
+@@ -38,7 +38,7 @@
+ #endif
+ 
+ /* The lucky hart to first increment this variable will boot the other cores */
+-atomic_t hart_lottery;
++__section(.data) atomic_t hart_lottery;
+ unsigned long boot_cpu_hartid;
+ 
+ void __init parse_dtb(void)
+diff -Nur linux-5.4.36/arch/riscv/kernel/signal.c kernel/arch/riscv/kernel/signal.c
+--- linux-5.4.36/arch/riscv/kernel/signal.c	2020-04-29 14:33:25.000000000 +0000
++++ kernel/arch/riscv/kernel/signal.c	2020-09-03 06:01:13.906989796 +0000
+@@ -78,6 +78,41 @@
+ #define restore_fp_state(task, regs) (0)
+ #endif
+ 
++#ifdef CONFIG_VECTOR
++static long restore_v_state(struct pt_regs *regs,
++			    struct __riscv_v_state *sc_vregs)
++{
++	long err;
++	struct __riscv_v_state __user *state = sc_vregs;
++
++	err = __copy_from_user(&current->thread.vstate, state, sizeof(*state));
++	if (unlikely(err))
++		return err;
++
++	vstate_restore(current, regs);
++
++	return err;
++}
++
++static long save_v_state(struct pt_regs *regs,
++			 struct __riscv_v_state *sc_vregs)
++{
++	long err;
++	struct __riscv_v_state __user *state = sc_vregs;
++
++	vstate_save(current, regs);
++	err = __copy_to_user(state, &current->thread.vstate, sizeof(*state));
++	if (unlikely(err))
++		return err;
++
++	return err;
++}
++#else
++#define save_v_state(task, regs) (0)
++#define restore_v_state(task, regs) (0)
++#endif
++
++
+ static long restore_sigcontext(struct pt_regs *regs,
+ 	struct sigcontext __user *sc)
+ {
+@@ -87,6 +122,9 @@
+ 	/* Restore the floating-point state. */
+ 	if (has_fpu)
+ 		err |= restore_fp_state(regs, &sc->sc_fpregs);
++	/* Restore the vector state. */
++	if (has_vector)
++		err |= restore_v_state(regs, &sc->sc_vregs);
+ 	return err;
+ }
+ 
+@@ -140,6 +178,9 @@
+ 	/* Save the floating-point state. */
+ 	if (has_fpu)
+ 		err |= save_fp_state(regs, &sc->sc_fpregs);
++	/* Save the vector state. */
++	if (has_vector)
++		err |= save_v_state(regs, &sc->sc_vregs);
+ 	return err;
+ }
+ 
+diff -Nur linux-5.4.36/arch/riscv/kernel/smpboot.c kernel/arch/riscv/kernel/smpboot.c
+--- linux-5.4.36/arch/riscv/kernel/smpboot.c	2020-04-29 14:33:25.000000000 +0000
++++ kernel/arch/riscv/kernel/smpboot.c	2020-09-03 06:01:13.906989796 +0000
+@@ -33,8 +33,8 @@
+ 
+ #include "head.h"
+ 
+-void *__cpu_up_stack_pointer[NR_CPUS];
+-void *__cpu_up_task_pointer[NR_CPUS];
++__section(.data) void *__cpu_up_stack_pointer[NR_CPUS];
++__section(.data) void *__cpu_up_task_pointer[NR_CPUS];
+ static DECLARE_COMPLETION(cpu_running);
+ 
+ void __init smp_prepare_boot_cpu(void)
+@@ -102,6 +102,7 @@
+ 	int hartid = cpuid_to_hartid_map(cpu);
+ 	tidle->thread_info.cpu = cpu;
+ 
++	SBI_CALL_1(0x09000003, hartid);
+ 	/*
+ 	 * On RISC-V systems, all harts boot on their own accord.  Our _start
+ 	 * selects the first hart to boot the kernel and causes the remainder
+diff -Nur linux-5.4.36/arch/riscv/kernel/vector.S kernel/arch/riscv/kernel/vector.S
+--- linux-5.4.36/arch/riscv/kernel/vector.S	1970-01-01 00:00:00.000000000 +0000
++++ kernel/arch/riscv/kernel/vector.S	2020-09-03 06:01:13.907989796 +0000
+@@ -0,0 +1,84 @@
++/* SPDX-License-Identifier: GPL-2.0 */
++/*
++ * Copyright (C) 2012 Regents of the University of California
++ * Copyright (C) 2017 SiFive
++ * Copyright (C) 2019 T-HEAD
++ *
++ *   This program is free software; you can redistribute it and/or
++ *   modify it under the terms of the GNU General Public License
++ *   as published by the Free Software Foundation, version 2.
++ *
++ *   This program is distributed in the hope that it will be useful,
++ *   but WITHOUT ANY WARRANTY; without even the implied warranty of
++ *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ *   GNU General Public License for more details.
++ */
++
++#include <linux/linkage.h>
++
++#include <asm/asm.h>
++#include <asm/csr.h>
++#include <asm/asm-offsets.h>
++
++ENTRY(__vstate_save)
++	li	a2,  TASK_THREAD_V0
++	add	a0,  a0, a2
++
++	li	t1, (SR_VS | SR_FS)
++	csrs	sstatus, t1
++
++	csrr	t0,  CSR_VSTART
++	sd	t0,  TASK_THREAD_VSTART_V0(a0)
++	csrr	t0,  CSR_VXSAT
++	sd	t0,  TASK_THREAD_VXSAT_V0(a0)
++	csrr	t0,  CSR_VXRM
++	sd	t0,  TASK_THREAD_VXRM_V0(a0)
++	csrr	t0,  CSR_VL
++	sd	t0,  TASK_THREAD_VL_V0(a0)
++	csrr	t0,  CSR_VTYPE
++	sd	t0,  TASK_THREAD_VTYPE_V0(a0)
++
++	vsetvli	t0, x0, e8,m8
++	vsb.v	v0,  (a0)
++	addi	a0, a0, RISCV_VECTOR_VLENB*8
++	vsb.v	v8,  (a0)
++	addi	a0, a0, RISCV_VECTOR_VLENB*8
++	vsb.v	v16, (a0)
++	addi	a0, a0, RISCV_VECTOR_VLENB*8
++	vsb.v	v24, (a0)
++
++	csrc	sstatus, t1
++	ret
++ENDPROC(__vstate_save)
++
++ENTRY(__vstate_restore)
++	li	a2,  TASK_THREAD_V0
++	add	a0,  a0, a2
++	mv	t2,  a0
++
++	li	t1, (SR_VS | SR_FS)
++	csrs	sstatus, t1
++
++	vsetvli	t0, x0, e8,m8
++	vlb.v	v0,  (a0)
++	addi	a0, a0, RISCV_VECTOR_VLENB*8
++	vlb.v	v8,  (a0)
++	addi	a0, a0, RISCV_VECTOR_VLENB*8
++	vlb.v	v16, (a0)
++	addi	a0, a0, RISCV_VECTOR_VLENB*8
++	vlb.v	v24, (a0)
++
++	mv	a0,  t2
++	ld	t0,  TASK_THREAD_VSTART_V0(a0)
++	csrw	CSR_VSTART, t0
++	ld	t0,  TASK_THREAD_VXSAT_V0(a0)
++	csrw	CSR_VXSAT, t0
++	ld	t0,  TASK_THREAD_VXRM_V0(a0)
++	csrw	CSR_VXRM, t0
++	ld	t0,  TASK_THREAD_VL_V0(a0)
++	ld	t2,  TASK_THREAD_VTYPE_V0(a0)
++	vsetvl	t0, t0, t2
++
++	csrc	sstatus, t1
++	ret
++ENDPROC(__vstate_restore)
+diff -Nur linux-5.4.36/arch/riscv/Makefile kernel/arch/riscv/Makefile
+--- linux-5.4.36/arch/riscv/Makefile	2020-04-29 14:33:25.000000000 +0000
++++ kernel/arch/riscv/Makefile	2020-09-03 06:01:13.901989796 +0000
+@@ -35,12 +35,19 @@
+ endif
+ 
+ # ISA string setting
+-riscv-march-$(CONFIG_ARCH_RV32I)	:= rv32ima
+-riscv-march-$(CONFIG_ARCH_RV64I)	:= rv64ima
+-riscv-march-$(CONFIG_FPU)		:= $(riscv-march-y)fd
+-riscv-march-$(CONFIG_RISCV_ISA_C)	:= $(riscv-march-y)c
+-KBUILD_CFLAGS += -march=$(subst fd,,$(riscv-march-y))
+-KBUILD_AFLAGS += -march=$(riscv-march-y)
++riscv-march-cflags-$(CONFIG_ARCH_RV32I)		:= rv32ima
++riscv-march-cflags-$(CONFIG_ARCH_RV64I)		:= rv64ima
++riscv-march-cflags-$(CONFIG_RISCV_ISA_C)	:= $(riscv-march-cflags-y)c
++
++riscv-march-aflags-$(CONFIG_ARCH_RV32I)		:= rv32ima
++riscv-march-aflags-$(CONFIG_ARCH_RV64I)		:= rv64ima
++riscv-march-aflags-$(CONFIG_FPU)		:= $(riscv-march-aflags-y)fd
++riscv-march-aflags-$(CONFIG_RISCV_ISA_C)	:= $(riscv-march-aflags-y)c
++riscv-march-aflags-$(CONFIG_VECTOR)		:= $(riscv-march-aflags-y)v
++riscv-march-aflags-$(CONFIG_RISCV_ISA_THEAD)	:= $(riscv-march-aflags-y)xthead
++
++KBUILD_CFLAGS += -march=$(riscv-march-cflags-y) -Wa,-march=$(riscv-march-aflags-y)
++KBUILD_AFLAGS += -march=$(riscv-march-aflags-y)
+ 
+ KBUILD_CFLAGS += -mno-save-restore
+ KBUILD_CFLAGS += -DCONFIG_PAGE_OFFSET=$(CONFIG_PAGE_OFFSET)
+diff -Nur linux-5.4.36/arch/riscv/mm/asid.c kernel/arch/riscv/mm/asid.c
+--- linux-5.4.36/arch/riscv/mm/asid.c	1970-01-01 00:00:00.000000000 +0000
++++ kernel/arch/riscv/mm/asid.c	2020-09-03 06:01:13.908989796 +0000
+@@ -0,0 +1,189 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Generic ASID allocator.
++ *
++ * Based on arch/arm/mm/context.c
++ *
++ * Copyright (C) 2002-2003 Deep Blue Solutions Ltd, all rights reserved.
++ * Copyright (C) 2012 ARM Ltd.
++ */
++
++#include <linux/slab.h>
++#include <linux/mm_types.h>
++
++#include <asm/asid.h>
++
++#define reserved_asid(info, cpu) *per_cpu_ptr((info)->reserved, cpu)
++
++#define ASID_MASK(info)			(~GENMASK((info)->bits - 1, 0))
++#define ASID_FIRST_VERSION(info)	(1UL << ((info)->bits))
++
++#define asid2idx(info, asid)		(((asid) & ~ASID_MASK(info)) >> (info)->ctxt_shift)
++#define idx2asid(info, idx)		(((idx) << (info)->ctxt_shift) & ~ASID_MASK(info))
++
++static void flush_context(struct asid_info *info)
++{
++	int i;
++	u64 asid;
++
++	/* Update the list of reserved ASIDs and the ASID bitmap. */
++	bitmap_clear(info->map, 0, NUM_CTXT_ASIDS(info));
++
++	for_each_possible_cpu(i) {
++		asid = atomic64_xchg_relaxed(&active_asid(info, i), 0);
++		/*
++		 * If this CPU has already been through a
++		 * rollover, but hasn't run another task in
++		 * the meantime, we must preserve its reserved
++		 * ASID, as this is the only trace we have of
++		 * the process it is still running.
++		 */
++		if (asid == 0)
++			asid = reserved_asid(info, i);
++		__set_bit(asid2idx(info, asid), info->map);
++		reserved_asid(info, i) = asid;
++	}
++
++	/*
++	 * Queue a TLB invalidation for each CPU to perform on next
++	 * context-switch
++	 */
++	cpumask_setall(&info->flush_pending);
++}
++
++static bool check_update_reserved_asid(struct asid_info *info, u64 asid,
++				       u64 newasid)
++{
++	int cpu;
++	bool hit = false;
++
++	/*
++	 * Iterate over the set of reserved ASIDs looking for a match.
++	 * If we find one, then we can update our mm to use newasid
++	 * (i.e. the same ASID in the current generation) but we can't
++	 * exit the loop early, since we need to ensure that all copies
++	 * of the old ASID are updated to reflect the mm. Failure to do
++	 * so could result in us missing the reserved ASID in a future
++	 * generation.
++	 */
++	for_each_possible_cpu(cpu) {
++		if (reserved_asid(info, cpu) == asid) {
++			hit = true;
++			reserved_asid(info, cpu) = newasid;
++		}
++	}
++
++	return hit;
++}
++
++static u64 new_context(struct asid_info *info, atomic64_t *pasid,
++		       struct mm_struct *mm)
++{
++	static u32 cur_idx = 1;
++	u64 asid = atomic64_read(pasid);
++	u64 generation = atomic64_read(&info->generation);
++
++	if (asid != 0) {
++		u64 newasid = generation | (asid & ~ASID_MASK(info));
++
++		/*
++		 * If our current ASID was active during a rollover, we
++		 * can continue to use it and this was just a false alarm.
++		 */
++		if (check_update_reserved_asid(info, asid, newasid))
++			return newasid;
++
++		/*
++		 * We had a valid ASID in a previous life, so try to re-use
++		 * it if possible.
++		 */
++		if (!__test_and_set_bit(asid2idx(info, asid), info->map))
++			return newasid;
++	}
++
++	/*
++	 * Allocate a free ASID. If we can't find one, take a note of the
++	 * currently active ASIDs and mark the TLBs as requiring flushes.  We
++	 * always count from ASID #2 (index 1), as we use ASID #0 when setting
++	 * a reserved TTBR0 for the init_mm and we allocate ASIDs in even/odd
++	 * pairs.
++	 */
++	asid = find_next_zero_bit(info->map, NUM_CTXT_ASIDS(info), cur_idx);
++	if (asid != NUM_CTXT_ASIDS(info))
++		goto set_asid;
++
++	/* We're out of ASIDs, so increment the global generation count */
++	generation = atomic64_add_return_relaxed(ASID_FIRST_VERSION(info),
++						 &info->generation);
++	flush_context(info);
++
++	/* We have more ASIDs than CPUs, so this will always succeed */
++	asid = find_next_zero_bit(info->map, NUM_CTXT_ASIDS(info), 1);
++
++set_asid:
++	__set_bit(asid, info->map);
++	cur_idx = asid;
++	cpumask_clear(mm_cpumask(mm));
++	return idx2asid(info, asid) | generation;
++}
++
++/*
++ * Generate a new ASID for the context.
++ *
++ * @pasid: Pointer to the current ASID batch allocated. It will be updated
++ * with the new ASID batch.
++ * @cpu: current CPU ID. Must have been acquired through get_cpu()
++ */
++void asid_new_context(struct asid_info *info, atomic64_t *pasid,
++		      unsigned int cpu, struct mm_struct *mm)
++{
++	unsigned long flags;
++	u64 asid;
++
++	raw_spin_lock_irqsave(&info->lock, flags);
++	/* Check that our ASID belongs to the current generation. */
++	asid = atomic64_read(pasid);
++	if ((asid ^ atomic64_read(&info->generation)) >> info->bits) {
++		asid = new_context(info, pasid, mm);
++		atomic64_set(pasid, asid);
++	}
++
++	if (cpumask_test_and_clear_cpu(cpu, &info->flush_pending))
++		info->flush_cpu_ctxt_cb();
++
++	atomic64_set(&active_asid(info, cpu), asid);
++	cpumask_set_cpu(cpu, mm_cpumask(mm));
++	raw_spin_unlock_irqrestore(&info->lock, flags);
++}
++
++/*
++ * Initialize the ASID allocator
++ *
++ * @info: Pointer to the asid allocator structure
++ * @bits: Number of ASIDs available
++ * @asid_per_ctxt: Number of ASIDs to allocate per-context. ASIDs are
++ * allocated contiguously for a given context. This value should be a power of
++ * 2.
++ */
++int asid_allocator_init(struct asid_info *info,
++			u32 bits, unsigned int asid_per_ctxt,
++			void (*flush_cpu_ctxt_cb)(void))
++{
++	info->bits = bits;
++	info->ctxt_shift = ilog2(asid_per_ctxt);
++	info->flush_cpu_ctxt_cb = flush_cpu_ctxt_cb;
++	/*
++	 * Expect allocation after rollover to fail if we don't have at least
++	 * one more ASID than CPUs. ASID #0 is always reserved.
++	 */
++	WARN_ON(NUM_CTXT_ASIDS(info) - 1 <= num_possible_cpus());
++	atomic64_set(&info->generation, ASID_FIRST_VERSION(info));
++	info->map = kcalloc(BITS_TO_LONGS(NUM_CTXT_ASIDS(info)),
++			    sizeof(*info->map), GFP_KERNEL);
++	if (!info->map)
++		return -ENOMEM;
++
++	raw_spin_lock_init(&info->lock);
++
++	return 0;
++}
+diff -Nur linux-5.4.36/arch/riscv/mm/cacheflush.c kernel/arch/riscv/mm/cacheflush.c
+--- linux-5.4.36/arch/riscv/mm/cacheflush.c	2020-04-29 14:33:25.000000000 +0000
++++ kernel/arch/riscv/mm/cacheflush.c	2020-09-03 06:01:13.908989796 +0000
+@@ -74,3 +74,24 @@
+ 	if (!test_and_set_bit(PG_dcache_clean, &page->flags))
+ 		flush_icache_all();
+ }
++
++#define sync_is()	asm volatile (".long 0x01b0000b")
++void dma_wbinv_range(unsigned long start, unsigned long end)
++{
++	register unsigned long i asm("a0") = start & ~(L1_CACHE_BYTES - 1);
++
++	for (; i < end; i += L1_CACHE_BYTES)
++		asm volatile (".long 0x02b5000b"); /* dcache.cipa a0 */
++
++	sync_is();
++}
++
++void dma_wb_range(unsigned long start, unsigned long end)
++{
++	register unsigned long i asm("a0") = start & ~(L1_CACHE_BYTES - 1);
++
++	for (; i < end; i += L1_CACHE_BYTES)
++		asm volatile (".long 0x0295000b"); /* dcache.cpa a0 */
++
++	sync_is();
++}
+diff -Nur linux-5.4.36/arch/riscv/mm/context.c kernel/arch/riscv/mm/context.c
+--- linux-5.4.36/arch/riscv/mm/context.c	2020-04-29 14:33:25.000000000 +0000
++++ kernel/arch/riscv/mm/context.c	2020-09-03 06:01:13.908989796 +0000
+@@ -8,6 +8,7 @@
+ #include <asm/tlbflush.h>
+ #include <asm/cacheflush.h>
+ #include <asm/mmu_context.h>
++#include <asm/fence.h>
+ 
+ /*
+  * When necessary, performs a deferred icache flush for the given MM context,
+@@ -44,6 +45,8 @@
+ 	struct task_struct *task)
+ {
+ 	unsigned int cpu;
++	unsigned long asid;
++	unsigned long x;
+ 
+ 	if (unlikely(prev == next))
+ 		return;
+@@ -58,8 +61,50 @@
+ 	cpumask_clear_cpu(cpu, mm_cpumask(prev));
+ 	cpumask_set_cpu(cpu, mm_cpumask(next));
+ 
+-	csr_write(CSR_SATP, virt_to_pfn(next->pgd) | SATP_MODE);
+-	local_flush_tlb_all();
++	check_and_switch_context(next, cpu);
++	asid = (next->context.asid.counter & SATP_ASID_MASK)
++		<< SATP_ASID_SHIFT;
++
++	x = virt_to_pfn(next->pgd) | SATP_MODE | asid;
++	sync_mmu_v1();
++	sync_mmu_v1();
++	sync_mmu_v1();
++	csr_write(sptbr, x);
+ 
+ 	flush_icache_deferred(next);
+ }
++
++static DEFINE_PER_CPU(atomic64_t, active_asids);
++static DEFINE_PER_CPU(u64, reserved_asids);
++
++struct asid_info asid_info;
++
++void check_and_switch_context(struct mm_struct *mm, unsigned int cpu)
++{
++	asid_check_context(&asid_info, &mm->context.asid, cpu, mm);
++}
++
++static void asid_flush_cpu_ctxt(void)
++{
++	local_flush_tlb_all();
++}
++
++static int asids_init(void)
++{
++	BUG_ON(((1 << SATP_ASID_BITS) - 1) <= num_possible_cpus());
++
++	if (asid_allocator_init(&asid_info, SATP_ASID_BITS, 1,
++				asid_flush_cpu_ctxt))
++		panic("Unable to initialize ASID allocator for %lu ASIDs\n",
++		      NUM_ASIDS(&asid_info));
++
++	asid_info.active = &active_asids;
++	asid_info.reserved = &reserved_asids;
++
++	pr_info("ASID allocator initialised with %lu entries\n",
++		NUM_CTXT_ASIDS(&asid_info));
++
++	local_flush_tlb_all();
++	return 0;
++}
++early_initcall(asids_init);
+diff -Nur linux-5.4.36/arch/riscv/mm/dma-mapping.c kernel/arch/riscv/mm/dma-mapping.c
+--- linux-5.4.36/arch/riscv/mm/dma-mapping.c	1970-01-01 00:00:00.000000000 +0000
++++ kernel/arch/riscv/mm/dma-mapping.c	2020-09-03 06:01:13.908989796 +0000
+@@ -0,0 +1,70 @@
++// SPDX-License-Identifier: GPL-2.0
++// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
++
++#include <linux/cache.h>
++#include <linux/dma-mapping.h>
++#include <linux/dma-contiguous.h>
++#include <linux/dma-noncoherent.h>
++#include <linux/genalloc.h>
++#include <linux/highmem.h>
++#include <linux/io.h>
++#include <linux/mm.h>
++#include <linux/scatterlist.h>
++#include <linux/types.h>
++#include <linux/version.h>
++#include <asm/cache.h>
++
++void arch_dma_prep_coherent(struct page *page, size_t size)
++{
++	void *ptr = page_address(page);
++
++	memset(ptr, 0, size);
++	dma_wbinv_range(page_to_phys(page), page_to_phys(page) + size);
++}
++
++static inline void cache_op(phys_addr_t paddr, size_t size,
++			    void (*fn)(unsigned long start, unsigned long end))
++{
++	unsigned long start = (unsigned long)paddr;
++
++	fn(start, start + size);
++}
++
++void arch_sync_dma_for_device(struct device *dev, phys_addr_t paddr,
++			      size_t size, enum dma_data_direction dir)
++{
++	switch (dir) {
++	case DMA_TO_DEVICE:
++		cache_op(paddr, size, dma_wb_range);
++		break;
++	case DMA_FROM_DEVICE:
++	case DMA_BIDIRECTIONAL:
++		cache_op(paddr, size, dma_wbinv_range);
++		break;
++	default:
++		BUG();
++	}
++}
++
++void arch_sync_dma_for_cpu(struct device *dev, phys_addr_t paddr,
++			   size_t size, enum dma_data_direction dir)
++{
++	switch (dir) {
++	case DMA_TO_DEVICE:
++		return;
++	case DMA_FROM_DEVICE:
++	case DMA_BIDIRECTIONAL:
++		cache_op(paddr, size, dma_wbinv_range);
++		break;
++	default:
++		BUG();
++	}
++}
++
++pgprot_t arch_dma_mmap_pgprot(struct device *dev, pgprot_t prot,
++		unsigned long attrs)
++{
++	if (attrs & DMA_ATTR_WRITE_COMBINE)
++		return pgprot_writecombine(prot);
++	return pgprot_noncached(prot);
++}
+diff -Nur linux-5.4.36/arch/riscv/mm/fault.c kernel/arch/riscv/mm/fault.c
+--- linux-5.4.36/arch/riscv/mm/fault.c	2020-04-29 14:33:25.000000000 +0000
++++ kernel/arch/riscv/mm/fault.c	2020-09-03 06:01:13.908989796 +0000
+@@ -232,7 +232,7 @@
+ 		 * of a task switch.
+ 		 */
+ 		index = pgd_index(addr);
+-		pgd = (pgd_t *)pfn_to_virt(csr_read(CSR_SATP)) + index;
++		pgd = (pgd_t *)pfn_to_virt(csr_read(CSR_SATP) & SATP_PPN) + index;
+ 		pgd_k = init_mm.pgd + index;
+ 
+ 		if (!pgd_present(*pgd_k))
+diff -Nur linux-5.4.36/arch/riscv/mm/init.c kernel/arch/riscv/mm/init.c
+--- linux-5.4.36/arch/riscv/mm/init.c	2020-04-29 14:33:25.000000000 +0000
++++ kernel/arch/riscv/mm/init.c	2020-09-03 06:01:13.908989796 +0000
+@@ -13,6 +13,8 @@
+ #include <linux/of_fdt.h>
+ #include <linux/libfdt.h>
+ 
++#include <linux/crash_dump.h>
++
+ #include <asm/fixmap.h>
+ #include <asm/tlbflush.h>
+ #include <asm/sections.h>
+@@ -27,6 +29,167 @@
+ 
+ extern char _start[];
+ 
++#ifdef CONFIG_KEXEC_CORE
++static void __init reserve_crashkernel(void)
++{
++	unsigned long long crash_base, crash_size;
++	int ret;
++
++	ret = parse_crashkernel(boot_command_line, memblock_phys_mem_size(),
++			&crash_size, &crash_base);
++	if (ret || !crash_size)
++		return;
++
++	if (crash_base == 0) {
++		crash_base = memblock_find_in_range(0, __pfn_to_phys(max_low_pfn)-1,
++				crash_size, SZ_2M);
++		pr_debug("crash_base: 0x%llx\n", crash_base);
++	}
++
++	memblock_reserve(crash_base, crash_size);
++
++	pr_info("crashkernel reserved: 0x%016llx - 0x%016llx (%lld MB)\n",
++		crash_base, crash_base + crash_size, crash_size >> 20);
++
++	crashk_res.start = crash_base;
++	crashk_res.end = crash_base + crash_size - 1;
++}
++#else
++static void __init reserve_crashkernel(void)
++{
++}
++#endif /* CONFIG_KEXEC_CORE */
++
++#ifdef CONFIG_CRASH_DUMP
++static int __init early_init_dt_scan_elfcorehdr(unsigned long node,
++		const char *uname, int depth, void *data)
++{
++	const __be32 *reg;
++	int len;
++
++	if (depth != 1 || strcmp(uname, "chosen") != 0)
++		return 0;
++
++	reg = of_get_flat_dt_prop(node, "linux,elfcorehdr", &len);
++	if (!reg || (len < (dt_root_addr_cells + dt_root_size_cells)))
++		return 1;
++
++	elfcorehdr_addr = dt_mem_next_cell(dt_root_addr_cells, &reg);
++	elfcorehdr_size = dt_mem_next_cell(dt_root_size_cells, &reg);
++
++	return 1;
++}
++
++/*
++ * reserve_elfcorehdr() - reserves memory for elf core header
++ *
++ * This function reserves the memory occupied by an elf core header
++ * described in the device tree. This region contains all the
++ * information about primary kernel's core image and is used by a dump
++ * capture kernel to access the system memory on primary kernel.
++ */
++static void __init reserve_elfcorehdr(void)
++{
++	of_scan_flat_dt(early_init_dt_scan_elfcorehdr, NULL);
++
++	if (!elfcorehdr_size)
++		return;
++
++	if (memblock_is_region_reserved(elfcorehdr_addr, elfcorehdr_size)) {
++		pr_warn("elfcorehdr is overlapped\n");
++		return;
++	}
++
++	memblock_reserve(elfcorehdr_addr, elfcorehdr_size);
++
++	pr_info("Reserving %lldKB of memory at 0x%llx for elfcorehdr\n",
++		elfcorehdr_size >> 10, elfcorehdr_addr);
++}
++#else
++static void __init reserve_elfcorehdr(void)
++{
++}
++#endif /* CONFIG_CRASH_DUMP */
++
++/*
++ * Standard memory resources
++ */
++static struct resource mem_res[] = {
++	{
++		.name = "Kernel code",
++		.start = 0,
++		.end = 0,
++		.flags = IORESOURCE_SYSTEM_RAM
++	},
++	{
++		.name = "Kernel data",
++		.start = 0,
++		.end = 0,
++		.flags = IORESOURCE_SYSTEM_RAM
++	}
++};
++
++#define kernel_code mem_res[0]
++#define kernel_data mem_res[1]
++
++static int num_standard_resources;
++struct resource *standard_resources;
++
++extern char _start[];
++static void __init request_standard_resources(void)
++{
++	struct memblock_region *region;
++	struct resource *res;
++	unsigned long i = 0;
++	size_t res_size;
++
++	kernel_code.start   = __pa_symbol(_start);
++	kernel_code.end     = __pa_symbol(__init_end - 1);
++	kernel_data.start   = __pa_symbol(_sdata);
++	kernel_data.end     = __pa_symbol(_end - 1);
++
++	num_standard_resources = memblock.memory.cnt;
++	res_size = num_standard_resources * sizeof(*standard_resources);
++	standard_resources = memblock_alloc(res_size, SMP_CACHE_BYTES);
++	if (!standard_resources)
++		panic("%s: Failed to allocate %zu bytes\n", __func__, res_size);
++
++	for_each_memblock(memory, region) {
++		res = &standard_resources[i++];
++		if (memblock_is_nomap(region)) {
++			res->name  = "reserved";
++			res->flags = IORESOURCE_MEM;
++		} else {
++			res->name  = "System RAM";
++			res->flags = IORESOURCE_SYSTEM_RAM | IORESOURCE_BUSY;
++		}
++		res->start = __pfn_to_phys(memblock_region_memory_base_pfn(region));
++		res->end = __pfn_to_phys(memblock_region_memory_end_pfn(region)) - 1;
++
++		request_resource(&iomem_resource, res);
++
++		if (kernel_code.start >= res->start &&
++		    kernel_code.end <= res->end)
++			request_resource(res, &kernel_code);
++		if (kernel_data.start >= res->start &&
++		    kernel_data.end <= res->end)
++			request_resource(res, &kernel_data);
++#ifdef CONFIG_KEXEC_CORE
++		/* Userspace will find "Crash kernel" region in /proc/iomem. */
++		if (crashk_res.end && crashk_res.start >= res->start &&
++		    crashk_res.end <= res->end)
++			request_resource(res, &crashk_res);
++#endif
++	}
++}
++
++void __init riscv_kdump_crash(void)
++{
++	reserve_crashkernel();
++	reserve_elfcorehdr();
++	request_standard_resources();
++}
++
+ static void __init zone_sizes_init(void)
+ {
+ 	unsigned long max_zone_pfns[MAX_NR_ZONES] = { 0, };
+@@ -170,8 +333,8 @@
+ 		set_pte(ptep, pfn_pte(phys >> PAGE_SHIFT, prot));
+ 	} else {
+ 		pte_clear(&init_mm, addr, ptep);
+-		local_flush_tlb_page(addr);
+ 	}
++	local_flush_tlb_page(addr);
+ }
+ 
+ static pte_t *__init get_pte_virt(phys_addr_t pa)
+@@ -457,6 +620,7 @@
+ 	sparse_init();
+ 	setup_zero_page();
+ 	zone_sizes_init();
++	riscv_kdump_crash();
+ }
+ 
+ #ifdef CONFIG_SPARSEMEM_VMEMMAP
+diff -Nur linux-5.4.36/arch/riscv/mm/ioremap.c kernel/arch/riscv/mm/ioremap.c
+--- linux-5.4.36/arch/riscv/mm/ioremap.c	2020-04-29 14:33:25.000000000 +0000
++++ kernel/arch/riscv/mm/ioremap.c	2020-09-03 06:01:13.908989796 +0000
+@@ -50,26 +50,19 @@
+ 	return (void __iomem *)(vaddr + offset);
+ }
+ 
+-/*
+- * ioremap     -   map bus memory into CPU space
+- * @offset:    bus address of the memory
+- * @size:      size of the resource to map
+- *
+- * ioremap performs a platform specific sequence of operations to
+- * make bus memory CPU accessible via the readb/readw/readl/writeb/
+- * writew/writel functions and the other mmio helpers. The returned
+- * address is not guaranteed to be usable directly as a virtual
+- * address.
+- *
+- * Must be freed with iounmap.
+- */
+-void __iomem *ioremap(phys_addr_t offset, unsigned long size)
++void __iomem *__ioremap(phys_addr_t phys_addr, size_t size, pgprot_t prot)
+ {
+-	return __ioremap_caller(offset, size, PAGE_KERNEL,
+-		__builtin_return_address(0));
++	return __ioremap_caller(phys_addr, size, prot,
++				__builtin_return_address(0));
+ }
+-EXPORT_SYMBOL(ioremap);
++EXPORT_SYMBOL(__ioremap);
+ 
++void __iomem *ioremap_cache(phys_addr_t phys_addr, size_t size)
++{
++	return __ioremap_caller(phys_addr, size, PAGE_KERNEL,
++				__builtin_return_address(0));
++}
++EXPORT_SYMBOL(ioremap_cache);
+ 
+ /**
+  * iounmap - Free a IO remapping
+@@ -82,3 +75,16 @@
+ 	vunmap((void *)((unsigned long)addr & PAGE_MASK));
+ }
+ EXPORT_SYMBOL(iounmap);
++
++pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
++			      unsigned long size, pgprot_t vma_prot)
++{
++	if (!pfn_valid(pfn)) {
++		return pgprot_noncached(vma_prot);
++	} else if (file->f_flags & O_SYNC) {
++		return pgprot_writecombine(vma_prot);
++	}
++
++	return vma_prot;
++}
++EXPORT_SYMBOL(phys_mem_access_prot);
+diff -Nur linux-5.4.36/arch/riscv/mm/Makefile kernel/arch/riscv/mm/Makefile
+--- linux-5.4.36/arch/riscv/mm/Makefile	2020-04-29 14:33:25.000000000 +0000
++++ kernel/arch/riscv/mm/Makefile	2020-09-03 06:01:13.908989796 +0000
+@@ -12,6 +12,9 @@
+ obj-y += cacheflush.o
+ obj-y += context.o
+ obj-y += sifive_l2_cache.o
++obj-y += dma-mapping.o
++obj-y += asid.o
++obj-y += context.o
+ 
+ ifeq ($(CONFIG_MMU),y)
+ obj-$(CONFIG_SMP) += tlbflush.o
+diff -Nur linux-5.4.36/arch/riscv/mm/tlbflush.c kernel/arch/riscv/mm/tlbflush.c
+--- linux-5.4.36/arch/riscv/mm/tlbflush.c	2020-04-29 14:33:25.000000000 +0000
++++ kernel/arch/riscv/mm/tlbflush.c	2020-09-03 06:01:13.908989796 +0000
+@@ -2,6 +2,106 @@
+ 
+ #include <linux/mm.h>
+ #include <linux/smp.h>
++
++#define XUANTIE
++#ifdef  XUANTIE
++#include <asm/mmu_context.h>
++
++int c910_mmu_v1_flag = 0;
++
++void flush_tlb_all(void)
++{
++if (c910_mmu_v1_flag) {
++	sync_mmu_v1();
++	sync_mmu_v1();
++	sync_mmu_v1();
++}
++
++	__asm__ __volatile__ ("sfence.vma" : : : "memory");
++}
++
++void flush_tlb_mm(struct mm_struct *mm)
++{
++if (c910_mmu_v1_flag) {
++	int newpid = cpu_asid(mm);
++
++	__asm__ __volatile__ ("sfence.vma zero, %0"
++				:
++				: "r"(newpid)
++				: "memory");
++} else {
++	sync_mmu_v1();
++	sync_mmu_v1();
++	sync_mmu_v1();
++	__asm__ __volatile__ ("sfence.vma" : : : "memory");
++}
++}
++
++void flush_tlb_page(struct vm_area_struct *vma, unsigned long addr)
++{
++if (c910_mmu_v1_flag) {
++	int newpid = cpu_asid(vma->vm_mm);
++
++	addr &= PAGE_MASK;
++
++	__asm__ __volatile__ ("sfence.vma %0, %1"
++				:
++				: "r"(addr), "r"(newpid)
++				: "memory");
++
++} else {
++	addr &= PAGE_MASK;
++
++	sync_mmu_v1();
++	sync_mmu_v1();
++	sync_mmu_v1();
++	__asm__ __volatile__ ("sfence.vma %0"
++				:
++				: "r"(addr)
++				: "memory");
++}
++}
++
++void flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
++			unsigned long end)
++{
++	unsigned long newpid = cpu_asid(vma->vm_mm);
++
++	start &= PAGE_MASK;
++	end   += PAGE_SIZE - 1;
++	end   &= PAGE_MASK;
++
++if (c910_mmu_v1_flag) {
++	while (start < end) {
++		sync_mmu_v1();
++		sync_mmu_v1();
++		sync_mmu_v1();
++		__asm__ __volatile__ ("sfence.vma %0"
++					:
++					: "r"(start)
++					: "memory");
++		start += PAGE_SIZE;
++	}
++} else {
++	while (start < end) {
++		__asm__ __volatile__ ("sfence.vma %0, %1"
++					:
++					: "r"(start), "r"(newpid)
++					: "memory");
++		start += PAGE_SIZE;
++	}
++}
++}
++
++static int __init c910_mmu_v1(char *str)
++{
++	c910_mmu_v1_flag = 1;
++	return 0;
++}
++early_param("c910_mmu_v1", c910_mmu_v1);
++EXPORT_SYMBOL(c910_mmu_v1_flag);
++
++#else
+ #include <asm/sbi.h>
+ 
+ void flush_tlb_all(void)
+@@ -33,3 +133,4 @@
+ {
+ 	__sbi_tlb_flush_range(mm_cpumask(vma->vm_mm), start, end - start);
+ }
++#endif
+diff -Nur linux-5.4.36/drivers/i2c/busses/i2c-designware-master.c kernel/drivers/i2c/busses/i2c-designware-master.c
+--- linux-5.4.36/drivers/i2c/busses/i2c-designware-master.c	2020-04-29 14:33:25.000000000 +0000
++++ kernel/drivers/i2c/busses/i2c-designware-master.c	2020-09-03 06:01:15.387989734 +0000
+@@ -54,6 +54,10 @@
+ 	/* Calculate SCL timing parameters for standard mode if not set */
+ 	if (!dev->ss_hcnt || !dev->ss_lcnt) {
+ 		ic_clk = i2c_dw_clk_rate(dev);
++		/* Fixme begin: If can't get ic_clk from devicetree */
++		if (ic_clk == 0)
++			ic_clk = 50000; // unit: khz Fix
++		/* Fixme end */
+ 		dev->ss_hcnt =
+ 			i2c_dw_scl_hcnt(ic_clk,
+ 					4000,	/* tHD;STA = tHIGH = 4.0 us */
+diff -Nur linux-5.4.36/drivers/mmc/host/Kconfig kernel/drivers/mmc/host/Kconfig
+--- linux-5.4.36/drivers/mmc/host/Kconfig	2020-04-29 14:33:25.000000000 +0000
++++ kernel/drivers/mmc/host/Kconfig	2020-09-03 06:01:15.973989709 +0000
+@@ -736,7 +736,7 @@
+ 
+ config MMC_DW
+ 	tristate "Synopsys DesignWare Memory Card Interface"
+-	depends on ARC || ARM || ARM64 || MIPS || COMPILE_TEST
++	depends on ARC || ARM || ARM64 || MIPS || RISCV || CSKY || COMPILE_TEST
+ 	help
+ 	  This selects support for the Synopsys DesignWare Mobile Storage IP
+ 	  block, this provides host support for SD and MMC interfaces, in both
+diff -Nur linux-5.4.36/drivers/net/ethernet/stmicro/stmmac/dwmac-thead.c kernel/drivers/net/ethernet/stmicro/stmmac/dwmac-thead.c
+--- linux-5.4.36/drivers/net/ethernet/stmicro/stmmac/dwmac-thead.c	1970-01-01 00:00:00.000000000 +0000
++++ kernel/drivers/net/ethernet/stmicro/stmmac/dwmac-thead.c	2020-09-03 06:01:16.358989693 +0000
+@@ -0,0 +1,602 @@
++// SPDX-License-Identifier: GPL-2.0
++
++#include <linux/module.h>
++#include <linux/of.h>
++#include <linux/of_net.h>
++#include <linux/platform_device.h>
++
++#include "stmmac_platform.h"
++
++/* clock registers */
++#define GMAC_CLK_CFG0	0x00
++#define GMAC_CLK_CFG1	0x04
++#define GMAC_CLK_CFG2	0x08
++#define GMAC_CLK_CFG3	0x0C
++#define GMAC_CLK_CFG4	0x10
++#define GMAC_CLK_CFG5	0x14
++#define GMAC_CLK_CFG6	0x18
++
++/* phy interface */
++#define DWMAC_PHYIF_MII_GMII	0
++#define DWMAC_PHYIF_RGMII	1
++#define DWMAC_PHYIF_RMII	4
++/* register bit fields, bit[3]: reserved, bit[2:0]: phy interface */
++#define DWMAC_PHYIF_MASK	0x7
++#define DWMAC_PHYIF_BIT_WIDTH	4
++
++/* TXCLK direction, 1:input, 0:output */
++#define TXCLK_DIR_OUTPUT	0
++#define TXCLK_DIR_INPUT		1
++
++#define GMAC_CLK_PLLOUT_250M	250000000
++#define GMAC_GMII_RGMII_RATE	125000000
++#define GMAC_MII_RATE		25000000
++/* clock divider for speed */
++#define GMAC_CLKDIV_125M	(GMAC_CLK_PLLOUT_250M / GMAC_GMII_RGMII_RATE)
++#define GMAC_CLKDIV_25M		(GMAC_CLK_PLLOUT_250M / GMAC_MII_RATE)
++
++struct thead_dwmac_priv_data {
++	int id;
++	void __iomem *phy_if_reg;
++	void __iomem *txclk_dir_reg;
++	void __iomem *gmac_clk_reg;
++	int interface;
++	struct clk *gmac_pll_clk;
++	unsigned int gmac_pll_clk_freq;
++};
++
++/* set GMAC PHY interface, 0:MII/GMII, 1:RGMII, 4:RMII */
++static void thead_dwmac_set_phy_if(struct platform_device *pdev,
++				   void __iomem *phy_if_reg, int interface,
++				   int devid)
++{
++	struct device *dev = &pdev->dev;
++	unsigned int phyif = PHY_INTERFACE_MODE_MII;
++	volatile uint32_t reg;
++
++	if (phy_if_reg == NULL)
++		return;
++
++	switch (interface)
++	{
++	case PHY_INTERFACE_MODE_MII:
++	case PHY_INTERFACE_MODE_GMII:
++		phyif = DWMAC_PHYIF_MII_GMII;
++		break;
++	case PHY_INTERFACE_MODE_RGMII:
++	case PHY_INTERFACE_MODE_RGMII_TXID:
++	case PHY_INTERFACE_MODE_RGMII_RXID:
++	case PHY_INTERFACE_MODE_RGMII_ID:
++		phyif = DWMAC_PHYIF_RGMII;
++		break;
++	case PHY_INTERFACE_MODE_RMII:
++		phyif = DWMAC_PHYIF_RMII;
++		break;
++	default:
++		dev_err(dev, "phy interface %d not supported\n", interface);
++		return;
++	};
++
++	reg = readl(phy_if_reg);
++	reg &= ~(DWMAC_PHYIF_MASK << (DWMAC_PHYIF_BIT_WIDTH * devid));
++	reg |= (phyif & DWMAC_PHYIF_MASK) << (DWMAC_PHYIF_BIT_WIDTH * devid);
++	writel(reg, phy_if_reg);
++}
++
++/*
++ * set GMAC TXCLK direction
++ *     MII        : TXCLK is input
++ *     GMII/RGMII : TXCLK is output
++ */
++static void thead_dwmac_set_txclk_dir(struct platform_device *pdev,
++				void __iomem *txclk_dir_reg, int interface)
++{
++	struct device *dev = &pdev->dev;
++	unsigned int txclk_dir = TXCLK_DIR_INPUT;
++
++	if (txclk_dir_reg == NULL)
++		return;
++
++	switch (interface)
++	{
++	case PHY_INTERFACE_MODE_MII:
++	case PHY_INTERFACE_MODE_RMII:
++		txclk_dir = TXCLK_DIR_INPUT;
++		break;
++	case PHY_INTERFACE_MODE_GMII:
++	case PHY_INTERFACE_MODE_RGMII:
++	case PHY_INTERFACE_MODE_RGMII_TXID:
++	case PHY_INTERFACE_MODE_RGMII_RXID:
++	case PHY_INTERFACE_MODE_RGMII_ID:
++		txclk_dir = TXCLK_DIR_OUTPUT;
++		break;
++	default:
++		dev_err(dev, "phy interface %d not supported\n", interface);
++		return;
++	};
++
++	writel(txclk_dir, txclk_dir_reg);
++}
++
++static void thead_dwmac_set_clk_source(struct platform_device *pdev,
++				void __iomem *gmac_clk_reg, int interface)
++{
++	struct device *dev = &pdev->dev;
++	volatile uint32_t reg;
++
++	if (gmac_clk_reg == NULL)
++		return;
++
++	reg = readl(gmac_clk_reg + GMAC_CLK_CFG0);
++
++	/* RX clock source */
++	reg |= BIT(7);  /* gmac_rx_clk_sel: extern pin */
++
++	/* TX clock source */
++	if (interface == PHY_INTERFACE_MODE_MII) {
++		reg |= BIT(1);  /* gmac_tx_clk_sel: extern pin */
++		reg &= ~BIT(2); /* gmac_tx_clk_gbit_sel: u_tx_clk_mux */
++	} else if (interface == PHY_INTERFACE_MODE_GMII) {
++		reg &= ~BIT(5); /* gmac_tx_clk_out_sel: GMAC PLL */
++		reg |= BIT(2);  /* gmac_tx_clk_gbit_sel: GMAC PLL */
++	} else if (interface == PHY_INTERFACE_MODE_RGMII
++		|| interface == PHY_INTERFACE_MODE_RGMII_ID
++		|| interface == PHY_INTERFACE_MODE_RGMII_RXID
++		|| interface == PHY_INTERFACE_MODE_RGMII_TXID) {
++		reg &= ~BIT(5); /* gmac_tx_clk_out_sel: GMAC PLL */
++		reg |= BIT(2);  /* gmac_tx_clk_gbit_sel: GMAC PLL */
++	} else {
++		dev_err(dev, "phy interface %d not supported\n", interface);
++		return;
++	}
++
++	writel(reg, gmac_clk_reg + GMAC_CLK_CFG0);
++}
++
++
++/* set clock source */
++static void thead_dwmac_set_clock_delay(struct platform_device *pdev,
++				void __iomem *gmac_clk_reg, int interface)
++{
++	unsigned int delay;
++
++	if (gmac_clk_reg == NULL)
++		return;
++
++	if (of_property_read_u32(pdev->dev.of_node, "rx-clk-delay",
++				 &delay) == 0) {
++		/* RX clk delay */
++		writel(delay, gmac_clk_reg + GMAC_CLK_CFG1);
++		pr_info("RX clk delay: 0x%X\n", delay);
++	}
++
++	if (of_property_read_u32(pdev->dev.of_node, "tx-clk-delay",
++				 &delay) == 0) {
++		/* TX clk delay */
++		writel(delay, gmac_clk_reg + GMAC_CLK_CFG2);
++		pr_info("TX clk delay: 0x%X\n", delay);
++	}
++}
++
++/* set gmac pll divider (u_pll_clk_div) to get 250MHz clock */
++static void thead_dwmac_set_pll_250M(void __iomem *gmac_clk_reg, int interface,
++				unsigned int src_freq)
++{
++	volatile unsigned int reg;
++	unsigned int div = 1;
++
++	if (gmac_clk_reg == NULL)
++		return;
++
++	if (interface == PHY_INTERFACE_MODE_MII) {
++		/* For MII, no internal PLL is used */
++		return;
++	} else if (interface == PHY_INTERFACE_MODE_GMII
++		|| interface == PHY_INTERFACE_MODE_RGMII
++		|| interface == PHY_INTERFACE_MODE_RGMII_ID
++		|| interface == PHY_INTERFACE_MODE_RGMII_RXID
++		|| interface == PHY_INTERFACE_MODE_RGMII_TXID) {
++
++		/* check clock */
++		if ((src_freq == 0) || (src_freq % GMAC_CLK_PLLOUT_250M != 0)) {
++			pr_err("error! invalid gmac pll freq %d\n", src_freq);
++			return;
++		}
++		div = src_freq / GMAC_CLK_PLLOUT_250M;
++
++		/* disable pll_clk_div */
++		reg = readl(gmac_clk_reg + GMAC_CLK_CFG3);
++		reg &= ~BIT(31);
++		writel(reg, gmac_clk_reg + GMAC_CLK_CFG3);
++
++		/* modify divider */
++		writel(div, gmac_clk_reg + GMAC_CLK_CFG3);
++
++		/* enable pll_clk_div */
++		reg = readl(gmac_clk_reg + GMAC_CLK_CFG3);
++		reg |= BIT(31);
++		writel(reg, gmac_clk_reg + GMAC_CLK_CFG3);
++	} else {
++		pr_err("phy interface %d not supported\n", interface);
++		return;
++	}
++}
++
++/* set gmac speed */
++static void thead_dwmac_set_speed(void __iomem *gmac_clk_reg, int interface,
++				unsigned int speed)
++{
++	volatile unsigned int reg;
++
++	if (gmac_clk_reg == NULL)
++		return;
++
++	if (interface == PHY_INTERFACE_MODE_MII) {
++		/* For MII, no internal PLL is used */
++		return;
++	} else if (interface == PHY_INTERFACE_MODE_GMII
++		|| interface == PHY_INTERFACE_MODE_RGMII
++		|| interface == PHY_INTERFACE_MODE_RGMII_ID
++		|| interface == PHY_INTERFACE_MODE_RGMII_RXID
++		|| interface == PHY_INTERFACE_MODE_RGMII_TXID) {
++
++		/* disable gtx_clk_div */
++		reg = readl(gmac_clk_reg + GMAC_CLK_CFG4);
++		reg &= ~BIT(31);
++		writel(reg, gmac_clk_reg + GMAC_CLK_CFG4);
++
++		/*
++		 * modify divider
++		 */
++		/* gtx_clk_div */
++		if (speed == SPEED_1000) {
++			writel(GMAC_CLKDIV_125M, gmac_clk_reg + GMAC_CLK_CFG4);
++		} else if (speed == SPEED_100) {
++			writel(GMAC_CLKDIV_25M, gmac_clk_reg + GMAC_CLK_CFG4);
++		} else {
++			writel(GMAC_CLKDIV_25M / 10, gmac_clk_reg + GMAC_CLK_CFG4);
++		}
++
++		/* enable gtx_clk_div */
++		reg = readl(gmac_clk_reg + GMAC_CLK_CFG4);
++		reg |= BIT(31);
++		writel(reg, gmac_clk_reg + GMAC_CLK_CFG4);
++	} else {
++		pr_err("phy interface %d not supported\n", interface);
++		return;
++	}
++}
++
++/* enable gmac clock */
++static void thead_dwmac_enable_clock(struct platform_device *pdev,
++				void __iomem *gmac_clk_reg, int interface)
++{
++	struct device *dev = &pdev->dev;
++	volatile unsigned int reg;
++
++	if (gmac_clk_reg == NULL)
++		return;
++
++	reg = readl(gmac_clk_reg + GMAC_CLK_CFG0);
++
++	/* enable gmac_hclk */
++	reg |= BIT(14);
++
++	if (interface == PHY_INTERFACE_MODE_MII) {
++		reg |= BIT(8);  /* enable gmac_rx_clk */
++		reg |= BIT(3);  /* enable gmac_tx_clk */
++	} else if (interface == PHY_INTERFACE_MODE_GMII) {
++		reg |= BIT(8);  /* enable gmac_rx_clk */
++		reg |= BIT(3);  /* enable gmac_tx_clk */
++		reg |= BIT(6);  /* enable gmac_tx_clk_out */
++	} else if (interface == PHY_INTERFACE_MODE_RGMII
++		|| interface == PHY_INTERFACE_MODE_RGMII_ID
++		|| interface == PHY_INTERFACE_MODE_RGMII_RXID
++		|| interface == PHY_INTERFACE_MODE_RGMII_TXID) {
++		reg |= BIT(8);  /* enable gmac_rx_clk */
++		reg |= BIT(3);  /* enable gmac_tx_clk */
++		reg |= BIT(6);  /* enable gmac_tx_clk_out */
++		reg |= BIT(9);  /* enable gmac_rx_clk_n */
++		reg |= BIT(4);  /* enable gmac_tx_clk_n */
++	} else {
++		dev_err(dev, "phy interface %d not supported\n", interface);
++		return;
++	}
++
++	writel(reg, gmac_clk_reg + GMAC_CLK_CFG0);
++}
++
++#if 0
++/* disable gmac clock */
++static void thead_dwmac_disable_clock(struct platform_device *pdev,
++				void __iomem *gmac_clk_reg, int interface)
++{
++	struct device *dev = &pdev->dev;
++	volatile unsigned int reg;
++
++	if (gmac_clk_reg == NULL)
++		return;
++
++	reg = readl(gmac_clk_reg + GMAC_CLK_CFG0);
++
++	/* disable gmac_hclk */
++	reg &= ~BIT(14);
++
++	if (interface == PHY_INTERFACE_MODE_MII) {
++		reg &= ~BIT(8); /* disable gmac_rx_clk */
++		reg &= ~BIT(3); /* disable gmac_tx_clk */
++	} else if (interface == PHY_INTERFACE_MODE_GMII) {
++		reg &= ~BIT(8); /* disable gmac_rx_clk */
++		reg &= ~BIT(3); /* disable gmac_tx_clk */
++		reg &= ~BIT(6); /* disable gmac_tx_clk_out */
++	} else if (interface == PHY_INTERFACE_MODE_RGMII
++		|| interface == PHY_INTERFACE_MODE_RGMII_ID
++		|| interface == PHY_INTERFACE_MODE_RGMII_RXID
++		|| interface == PHY_INTERFACE_MODE_RGMII_TXID) {
++		reg &= ~BIT(8); /* disable gmac_rx_clk */
++		reg &= ~BIT(3); /* disable gmac_tx_clk */
++		reg &= ~BIT(6); /* disable gmac_tx_clk_out */
++		reg &= ~BIT(9); /* disable gmac_rx_clk_n */
++		reg &= ~BIT(4); /* disable gmac_tx_clk_n */
++	} else {
++		dev_err(dev, "phy interface %d not supported\n", interface);
++		return;
++	}
++
++	writel(reg, gmac_clk_reg + GMAC_CLK_CFG0);
++}
++#endif
++
++static int thead_dwmac_init(struct platform_device *pdev, void *bsp_priv)
++{
++	struct thead_dwmac_priv_data *thead_plat_dat = bsp_priv;
++	struct device *dev = &pdev->dev;
++	struct device_node *np = pdev->dev.of_node;
++	struct resource *res;
++	void __iomem *ptr;
++	struct clk *clktmp;
++	int ret;
++
++	thead_plat_dat->id = of_alias_get_id(np, "ethernet");
++	if (thead_plat_dat->id < 0) {
++		thead_plat_dat->id = 0;
++	}
++	dev_info(dev, "id: %d\n", thead_plat_dat->id);
++
++	thead_plat_dat->interface = of_get_phy_mode(dev->of_node);
++	dev_info(dev, "phy interface: %d\n", thead_plat_dat->interface);
++
++	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy_if_reg");
++	if ((res != NULL) && (resource_type(res) == IORESOURCE_MEM)) {
++		ptr = devm_ioremap(dev, res->start, resource_size(res));
++		if (!ptr) {
++			dev_err(dev, "phy interface register not exist, skipped it\n");
++		} else {
++			thead_plat_dat->phy_if_reg = ptr;
++		}
++	}
++
++	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "txclk_dir_reg");
++	ptr = devm_ioremap_resource(dev, res);
++	if (IS_ERR(ptr)) {
++		dev_err(dev, "txclk_dir register not exist, skipped it\n");
++	} else {
++		thead_plat_dat->txclk_dir_reg = ptr;
++	}
++
++	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "clk_mgr_reg");
++	ptr = devm_ioremap_resource(dev, res);
++	if (IS_ERR(ptr)) {
++		dev_err(dev, "gmac_clk register not exist, skipped it\n");
++	} else {
++		thead_plat_dat->gmac_clk_reg = ptr;
++	}
++
++	/* get gmac pll clk */
++	clktmp = devm_clk_get(dev, "gmac_pll_clk");
++	if (IS_ERR(clktmp)) {
++		dev_err(dev, "gmac_pll_clk not exist, skipped it\n");
++	} else {
++		thead_plat_dat->gmac_pll_clk = clktmp;
++
++		ret = clk_prepare_enable(thead_plat_dat->gmac_pll_clk);
++		if (ret) {
++			dev_err(dev, "Failed to enable clk 'gmac_pll_clk'\n");
++			return -1;
++		}
++
++		thead_plat_dat->gmac_pll_clk_freq =
++				clk_get_rate(thead_plat_dat->gmac_pll_clk);
++	}
++
++	thead_dwmac_set_phy_if(pdev, thead_plat_dat->phy_if_reg,
++				thead_plat_dat->interface, thead_plat_dat->id);
++
++	thead_dwmac_set_txclk_dir(pdev, thead_plat_dat->txclk_dir_reg,
++				thead_plat_dat->interface);
++
++	thead_dwmac_set_clk_source(pdev, thead_plat_dat->gmac_clk_reg,
++				thead_plat_dat->interface);
++	thead_dwmac_set_clock_delay(pdev, thead_plat_dat->gmac_clk_reg,
++				thead_plat_dat->interface);
++
++	thead_dwmac_set_pll_250M(thead_plat_dat->gmac_clk_reg,
++				thead_plat_dat->interface,
++				thead_plat_dat->gmac_pll_clk_freq);
++
++	/* default speed is 1Gbps */
++	thead_dwmac_set_speed(thead_plat_dat->gmac_clk_reg,
++				thead_plat_dat->interface, SPEED_1000);
++
++	thead_dwmac_enable_clock(pdev, thead_plat_dat->gmac_clk_reg,
++				thead_plat_dat->interface);
++	return 0;
++}
++
++static void thead_dwmac_fix_speed(void *bsp_priv, unsigned int speed)
++{
++	struct thead_dwmac_priv_data *thead_plat_dat = bsp_priv;
++
++	thead_dwmac_set_speed(thead_plat_dat->gmac_clk_reg,
++				thead_plat_dat->interface, speed);
++}
++
++/**
++ * dwmac1000_validate_mcast_bins - validates the number of Multicast filter bins
++ * @mcast_bins: Multicast filtering bins
++ * Description:
++ * this function validates the number of Multicast filtering bins specified
++ * by the configuration through the device tree. The Synopsys GMAC supports
++ * 64 bins, 128 bins, or 256 bins. "bins" refer to the division of CRC
++ * number space. 64 bins correspond to 6 bits of the CRC, 128 corresponds
++ * to 7 bits, and 256 refers to 8 bits of the CRC. Any other setting is
++ * invalid and will cause the filtering algorithm to use Multicast
++ * promiscuous mode.
++ */
++static int dwmac1000_validate_mcast_bins(int mcast_bins)
++{
++	int x = mcast_bins;
++
++	switch (x) {
++	case HASH_TABLE_SIZE:
++	case 128:
++	case 256:
++		break;
++	default:
++		x = 0;
++		pr_info("Hash table entries set to unexpected value %d",
++			mcast_bins);
++		break;
++	}
++	return x;
++}
++
++/**
++ * dwmac1000_validate_ucast_entries - validate the Unicast address entries
++ * @ucast_entries: number of Unicast address entries
++ * Description:
++ * This function validates the number of Unicast address entries supported
++ * by a particular Synopsys 10/100/1000 controller. The Synopsys controller
++ * supports 1..32, 64, or 128 Unicast filter entries for it's Unicast filter
++ * logic. This function validates a valid, supported configuration is
++ * selected, and defaults to 1 Unicast address if an unsupported
++ * configuration is selected.
++ */
++static int dwmac1000_validate_ucast_entries(int ucast_entries)
++{
++	int x = ucast_entries;
++
++	switch (x) {
++	case 1 ... 32:
++	case 64:
++	case 128:
++		break;
++	default:
++		x = 1;
++		pr_info("Unicast table entries set to unexpected value %d\n",
++			ucast_entries);
++		break;
++	}
++	return x;
++}
++
++static int thead_dwmac_probe(struct platform_device *pdev)
++{
++	struct plat_stmmacenet_data *plat_dat;
++	struct stmmac_resources stmmac_res;
++	struct thead_dwmac_priv_data *thead_plat_dat;
++	struct device *dev = &pdev->dev;
++	struct device_node *np = pdev->dev.of_node;
++	int ret;
++
++	thead_plat_dat = devm_kzalloc(dev, sizeof(*thead_plat_dat), GFP_KERNEL);
++	if (thead_plat_dat == NULL) {
++		dev_err(&pdev->dev, "allocate memory failed\n");
++		return -ENOMEM;
++	}
++
++	ret = stmmac_get_platform_resources(pdev, &stmmac_res);
++	if (ret)
++		return ret;
++
++	if (pdev->dev.of_node) {
++		plat_dat = stmmac_probe_config_dt(pdev, &stmmac_res.mac);
++		if (IS_ERR(plat_dat)) {
++			dev_err(&pdev->dev, "dt configuration failed\n");
++			return PTR_ERR(plat_dat);
++		}
++	} else {
++		plat_dat = dev_get_platdata(&pdev->dev);
++		if (!plat_dat) {
++			dev_err(&pdev->dev, "no platform data provided\n");
++			return  -EINVAL;
++		}
++
++		/* Set default value for multicast hash bins */
++		plat_dat->multicast_filter_bins = HASH_TABLE_SIZE;
++
++		/* Set default value for unicast filter entries */
++		plat_dat->unicast_filter_entries = 1;
++	}
++
++	/* Custom initialisation (if needed) */
++	if (plat_dat->init) {
++		ret = plat_dat->init(pdev, plat_dat->bsp_priv);
++		if (ret)
++			goto err_remove_config_dt;
++	}
++
++	/* populate bsp private data */
++	plat_dat->bsp_priv = thead_plat_dat;
++	plat_dat->fix_mac_speed = thead_dwmac_fix_speed;
++	of_property_read_u32(np, "max-frame-size", &plat_dat->maxmtu);
++	of_property_read_u32(np, "snps,multicast-filter-bins",
++			     &plat_dat->multicast_filter_bins);
++	of_property_read_u32(np, "snps,perfect-filter-entries",
++			     &plat_dat->unicast_filter_entries);
++	plat_dat->unicast_filter_entries = dwmac1000_validate_ucast_entries(
++				       plat_dat->unicast_filter_entries);
++	plat_dat->multicast_filter_bins = dwmac1000_validate_mcast_bins(
++				      plat_dat->multicast_filter_bins);
++	plat_dat->has_gmac = 1;
++	plat_dat->pmt = 1;
++
++	ret = thead_dwmac_init(pdev, plat_dat->bsp_priv);
++	if (ret)
++		goto err_exit;
++
++	ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res);
++	if (ret)
++		goto err_exit;
++
++	return 0;
++
++err_exit:
++	if (plat_dat->exit)
++		plat_dat->exit(pdev, plat_dat->bsp_priv);
++err_remove_config_dt:
++	if (pdev->dev.of_node)
++		stmmac_remove_config_dt(pdev, plat_dat);
++
++	return ret;
++}
++
++static const struct of_device_id thead_dwmac_match[] = {
++	{ .compatible = "thead,dwmac"},
++	{ }
++};
++MODULE_DEVICE_TABLE(of, thead_dwmac_match);
++
++static struct platform_driver thead_dwmac_driver = {
++	.probe  = thead_dwmac_probe,
++	.remove = stmmac_pltfr_remove,
++	.driver = {
++		.name           = "thead_dwmac_eth",
++		.pm		= &stmmac_pltfr_pm_ops,
++		.of_match_table = of_match_ptr(thead_dwmac_match),
++	},
++};
++module_platform_driver(thead_dwmac_driver);
++
++MODULE_DESCRIPTION("T-HEAD dwmac driver");
++MODULE_LICENSE("GPL v2");
+diff -Nur linux-5.4.36/drivers/net/ethernet/stmicro/stmmac/Makefile kernel/drivers/net/ethernet/stmicro/stmmac/Makefile
+--- linux-5.4.36/drivers/net/ethernet/stmicro/stmmac/Makefile	2020-04-29 14:33:25.000000000 +0000
++++ kernel/drivers/net/ethernet/stmicro/stmmac/Makefile	2020-09-03 06:01:16.356989693 +0000
+@@ -1,5 +1,5 @@
+ # SPDX-License-Identifier: GPL-2.0
+-obj-$(CONFIG_STMMAC_ETH) += stmmac.o
++obj-$(CONFIG_STMMAC_ETH) += stmmac.o dwmac-thead.o
+ stmmac-objs:= stmmac_main.o stmmac_ethtool.o stmmac_mdio.o ring_mode.o	\
+ 	      chain_mode.o dwmac_lib.o dwmac1000_core.o dwmac1000_dma.o	\
+ 	      dwmac100_core.o dwmac100_dma.o enh_desc.o norm_desc.o	\
+diff -Nur linux-5.4.36/drivers/perf/Kconfig kernel/drivers/perf/Kconfig
+--- linux-5.4.36/drivers/perf/Kconfig	2020-04-29 14:33:25.000000000 +0000
++++ kernel/drivers/perf/Kconfig	2020-09-03 06:01:16.736989677 +0000
+@@ -71,6 +71,14 @@
+ 	  system, control logic. The PMU allows counting various events related
+ 	  to DSU.
+ 
++config THEAD_XT_V1_PMU
++	bool "T-HEAD XuanTie v1 Performance Monitoring Unit"
++	depends on RISCV
++	def_bool y
++	help
++	  T-HEAD XuanTie PMU support various hardware event, including cycles,
++	  instructions, cache access/miss, LSU event and etc.
++
+ config FSL_IMX8_DDR_PMU
+ 	tristate "Freescale i.MX8 DDR perf monitor"
+ 	depends on ARCH_MXC
+diff -Nur linux-5.4.36/drivers/perf/Makefile kernel/drivers/perf/Makefile
+--- linux-5.4.36/drivers/perf/Makefile	2020-04-29 14:33:25.000000000 +0000
++++ kernel/drivers/perf/Makefile	2020-09-03 06:01:16.736989677 +0000
+@@ -12,3 +12,4 @@
+ obj-$(CONFIG_THUNDERX2_PMU) += thunderx2_pmu.o
+ obj-$(CONFIG_XGENE_PMU) += xgene_pmu.o
+ obj-$(CONFIG_ARM_SPE_PMU) += arm_spe_pmu.o
++obj-$(CONFIG_THEAD_XT_V1_PMU) += thead_xt_pmu_v1.o
+diff -Nur linux-5.4.36/drivers/perf/thead_xt_pmu_v1.c kernel/drivers/perf/thead_xt_pmu_v1.c
+--- linux-5.4.36/drivers/perf/thead_xt_pmu_v1.c	1970-01-01 00:00:00.000000000 +0000
++++ kernel/drivers/perf/thead_xt_pmu_v1.c	2020-09-03 06:01:16.738989677 +0000
+@@ -0,0 +1,768 @@
++// SPDX-License-Identifier: GPL-2.0
++/* Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd. */
++
++#include <linux/errno.h>
++#include <linux/interrupt.h>
++#include <linux/module.h>
++#include <linux/of.h>
++#include <linux/perf_event.h>
++#include <linux/platform_device.h>
++#include <linux/smp.h>
++#include <asm/perf_event.h>
++#include <asm/sbi.h>
++
++#define RISCV_PMU_CYCLE		0
++#define RISCV_PMU_TIME		1
++#undef RISCV_PMU_INSTRET
++#define RISCV_PMU_INSTRET	2
++#define RISCV_PMU_L1ICAC	3	/* ICache Access */
++#define RISCV_PMU_L1ICMC	4	/* ICache Miss */
++#define RISCV_PMU_IUTLBMC	5	/* I-UTLB Miss */
++#define RISCV_PMU_DUTLBMC	6	/* D-UTLB Miss */
++#define RISCV_PMU_JTLBMC	7	/* JTLB Miss Counter */
++
++#define RISCV_PMU_CBMC		8	/* Cond-br-mispredict */
++#define RISCV_PMU_CBIC		9	/* Cond-br-instruction */
++#define RISCV_PMU_IBMC		10	/* Indirect Branch Mispredict */
++#define RISCV_PMU_IBIC		11	/* Indirect Branch Instruction */
++#define RISCV_PMU_LSUSFC	12	/* LSU Spec Fail */
++#define RISCV_PMU_STC		13	/* Store Instruction */
++
++#define RISCV_PMU_L1DCRAC	14	/* L1 DCache Read Access */
++#define RISCV_PMU_L1DCRMC	15	/* L1 DCache Read Miss */
++#define RISCV_PMU_L1DCWAC	16	/* L1 DCache Write Access */
++#define RISCV_PMU_L1DCWMC	17	/* L1 DCache Write Miss */
++
++#define RISCV_PMU_L2CRAC	18	/* L2 Cache Read Access */
++#define RISCV_PMU_L2CRMC	19	/* L2 Cache Read Miss */
++#define RISCV_PMU_L2CWAC	20	/* L2 Cache Write Access */
++#define RISCV_PMU_L2CWMC	21	/* L2 Cache Write Miss */
++
++#define RISCV_PMU_RFLFC		22	/* RF Launch Fail */
++#define RISCV_PMU_RFRLFC	23	/* RF Reg Launch Fail */
++#define RISCV_PMU_RFIC		24	/* RF Instruction */
++
++#define RISCV_PMU_LSUC4SC	25	/* LSU Cross 4K Stall */
++#define RISCV_PMU_LSUOSC	26	/* LSU Other Stall */
++#define RISCV_PMU_LSUSQDC	27	/* LSU SQ Discard */
++#define RISCV_PMU_LSUSQDDC	28	/* LSU SQ Data Discard */
++
++#define SCOUNTERINTEN		0x5c4
++#define SCOUNTEROF		0x5c5
++#define SCOUNTERBASE		0x5e0
++
++#define WRITE_COUNTER(idx, value) \
++		csr_write(SCOUNTERBASE + idx, value)
++
++/* The events for a given PMU register set. */
++struct pmu_hw_events {
++	/*
++	 * The events that are active on the PMU for the given index.
++	 */
++	struct perf_event *events[RISCV_MAX_COUNTERS];
++
++	/*
++	 * A 1 bit for an index indicates that the counter is being used for
++	 * an event. A 0 means that the counter can be used.
++	 */
++	unsigned long used_mask[BITS_TO_LONGS(RISCV_MAX_COUNTERS)];
++};
++
++static struct riscv_pmu_t {
++	struct pmu		      pmu;
++	struct pmu_hw_events __percpu   *hw_events;
++	struct platform_device	  *plat_device;
++	u64			     max_period;
++} riscv_pmu;
++
++/*
++ * Hardware & cache maps and their methods
++ */
++
++static const int riscv_hw_event_map[] = {
++	[PERF_COUNT_HW_CPU_CYCLES]			= RISCV_PMU_CYCLE,
++	[PERF_COUNT_HW_INSTRUCTIONS]			= RISCV_PMU_INSTRET,
++
++	[PERF_COUNT_HW_CACHE_REFERENCES]		= RISCV_PMU_L1ICAC,
++	[PERF_COUNT_HW_CACHE_MISSES]			= RISCV_PMU_L1ICMC,
++
++	[PERF_COUNT_HW_BRANCH_INSTRUCTIONS]		= RISCV_PMU_CBIC,
++	[PERF_COUNT_HW_BRANCH_MISSES]			= RISCV_PMU_CBMC,
++
++	[PERF_COUNT_HW_BUS_CYCLES]			= RISCV_PMU_IBMC,
++	[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND]		= RISCV_PMU_IBIC,
++	[PERF_COUNT_HW_STALLED_CYCLES_BACKEND]		= RISCV_PMU_LSUSFC,
++	[PERF_COUNT_HW_REF_CPU_CYCLES]			= RISCV_PMU_STC,
++};
++
++#define C(x) PERF_COUNT_HW_CACHE_##x
++static const int riscv_cache_event_map[PERF_COUNT_HW_CACHE_MAX]
++[PERF_COUNT_HW_CACHE_OP_MAX]
++[PERF_COUNT_HW_CACHE_RESULT_MAX] = {
++	[C(L1D)] = {
++		[C(OP_READ)] = {
++			[C(RESULT_ACCESS)] = RISCV_PMU_L1DCRAC,
++			[C(RESULT_MISS)] = RISCV_PMU_L1DCRMC,
++		},
++		[C(OP_WRITE)] = {
++			[C(RESULT_ACCESS)] = RISCV_PMU_L1DCWAC,
++			[C(RESULT_MISS)] = RISCV_PMU_L1DCWMC,
++		},
++		[C(OP_PREFETCH)] = {
++			[C(RESULT_ACCESS)] = RISCV_OP_UNSUPP,
++			[C(RESULT_MISS)] = RISCV_OP_UNSUPP,
++		},
++	},
++	[C(L1I)] = {
++		[C(OP_READ)] = {
++			[C(RESULT_ACCESS)] = RISCV_OP_UNSUPP,
++			[C(RESULT_MISS)] = RISCV_OP_UNSUPP,
++		},
++		[C(OP_WRITE)] = {
++			[C(RESULT_ACCESS)] = RISCV_OP_UNSUPP,
++			[C(RESULT_MISS)] = RISCV_OP_UNSUPP,
++		},
++		[C(OP_PREFETCH)] = {
++			[C(RESULT_ACCESS)] = RISCV_OP_UNSUPP,
++			[C(RESULT_MISS)] = RISCV_OP_UNSUPP,
++		},
++	},
++	[C(LL)] = {
++		[C(OP_READ)] = {
++			[C(RESULT_ACCESS)] = RISCV_PMU_L2CRAC,
++			[C(RESULT_MISS)] = RISCV_PMU_L2CRMC,
++		},
++		[C(OP_WRITE)] = {
++			[C(RESULT_ACCESS)] = RISCV_PMU_L2CWAC,
++			[C(RESULT_MISS)] = RISCV_PMU_L2CWMC,
++		},
++		[C(OP_PREFETCH)] = {
++			[C(RESULT_ACCESS)] = RISCV_OP_UNSUPP,
++			[C(RESULT_MISS)] = RISCV_OP_UNSUPP,
++		},
++	},
++	[C(DTLB)] = {
++		[C(OP_READ)] = {
++			[C(RESULT_ACCESS)] = RISCV_OP_UNSUPP,
++			[C(RESULT_MISS)] = RISCV_OP_UNSUPP,
++		},
++		[C(OP_WRITE)] = {
++			[C(RESULT_ACCESS)] = RISCV_OP_UNSUPP,
++			[C(RESULT_MISS)] = RISCV_OP_UNSUPP,
++		},
++		[C(OP_PREFETCH)] = {
++			[C(RESULT_ACCESS)] = RISCV_OP_UNSUPP,
++			[C(RESULT_MISS)] = RISCV_OP_UNSUPP,
++		},
++	},
++	[C(ITLB)] = {
++		[C(OP_READ)] = {
++			[C(RESULT_ACCESS)] = RISCV_OP_UNSUPP,
++			[C(RESULT_MISS)] = RISCV_OP_UNSUPP,
++		},
++		[C(OP_WRITE)] = {
++			[C(RESULT_ACCESS)] = RISCV_OP_UNSUPP,
++			[C(RESULT_MISS)] = RISCV_OP_UNSUPP,
++		},
++		[C(OP_PREFETCH)] = {
++			[C(RESULT_ACCESS)] = RISCV_OP_UNSUPP,
++			[C(RESULT_MISS)] = RISCV_OP_UNSUPP,
++		},
++	},
++	[C(BPU)] = {
++		[C(OP_READ)] = {
++			[C(RESULT_ACCESS)] = RISCV_OP_UNSUPP,
++			[C(RESULT_MISS)] = RISCV_OP_UNSUPP,
++		},
++		[C(OP_WRITE)] = {
++			[C(RESULT_ACCESS)] = RISCV_OP_UNSUPP,
++			[C(RESULT_MISS)] = RISCV_OP_UNSUPP,
++		},
++		[C(OP_PREFETCH)] = {
++			[C(RESULT_ACCESS)] = RISCV_OP_UNSUPP,
++			[C(RESULT_MISS)] = RISCV_OP_UNSUPP,
++		},
++	},
++	[C(NODE)] = {
++		[C(OP_READ)] = {
++			[C(RESULT_ACCESS)] = RISCV_OP_UNSUPP,
++			[C(RESULT_MISS)] = RISCV_OP_UNSUPP,
++		},
++		[C(OP_WRITE)] = {
++			[C(RESULT_ACCESS)] = RISCV_OP_UNSUPP,
++			[C(RESULT_MISS)] = RISCV_OP_UNSUPP,
++		},
++		[C(OP_PREFETCH)] = {
++			[C(RESULT_ACCESS)] = RISCV_OP_UNSUPP,
++			[C(RESULT_MISS)] = RISCV_OP_UNSUPP,
++		},
++	},
++};
++
++/*
++ * Low-level functions: reading/writing counters
++ */
++static inline u64 read_counter(int idx)
++{
++	u64 val = 0;
++
++	switch (idx) {
++	case RISCV_PMU_CYCLE:
++		val = csr_read(cycle);
++		break;
++	case RISCV_PMU_INSTRET:
++		val = csr_read(instret);
++		break;
++	case RISCV_PMU_L1ICAC:
++		val = csr_read(hpmcounter3);
++		break;
++	case RISCV_PMU_L1ICMC:
++		val = csr_read(hpmcounter4);
++		break;
++	case RISCV_PMU_IUTLBMC:
++		val = csr_read(hpmcounter5);
++		break;
++	case RISCV_PMU_DUTLBMC:
++		val = csr_read(hpmcounter6);
++		break;
++	case RISCV_PMU_JTLBMC:
++		val = csr_read(hpmcounter7);
++		break;
++	case RISCV_PMU_CBMC:
++		val = csr_read(hpmcounter8);
++		break;
++	case RISCV_PMU_CBIC:
++		val = csr_read(hpmcounter9);
++		break;
++	case RISCV_PMU_IBMC:
++		val = csr_read(hpmcounter10);
++		break;
++	case RISCV_PMU_IBIC:
++		val = csr_read(hpmcounter11);
++		break;
++	case RISCV_PMU_LSUSFC:
++		val = csr_read(hpmcounter12);
++		break;
++	case RISCV_PMU_STC:
++		val = csr_read(hpmcounter13);
++		break;
++	case RISCV_PMU_L1DCRAC:
++		val = csr_read(hpmcounter14);
++		break;
++	case RISCV_PMU_L1DCRMC:
++		val = csr_read(hpmcounter15);
++		break;
++	case RISCV_PMU_L1DCWAC:
++		val = csr_read(hpmcounter16);
++		break;
++	case RISCV_PMU_L1DCWMC:
++		val = csr_read(hpmcounter17);
++		break;
++	case RISCV_PMU_L2CRAC:
++		val = csr_read(hpmcounter18);
++		break;
++	case RISCV_PMU_L2CRMC:
++		val = csr_read(hpmcounter19);
++		break;
++	case RISCV_PMU_L2CWAC:
++		val = csr_read(hpmcounter20);
++		break;
++	case RISCV_PMU_L2CWMC:
++		val = csr_read(hpmcounter21);
++		break;
++	case RISCV_PMU_RFLFC:
++		val = csr_read(hpmcounter22);
++		break;
++	case RISCV_PMU_RFRLFC:
++		val = csr_read(hpmcounter23);
++		break;
++	case RISCV_PMU_RFIC:
++		val = csr_read(hpmcounter24);
++		break;
++	case RISCV_PMU_LSUC4SC:
++		val = csr_read(hpmcounter25);
++		break;
++	case RISCV_PMU_LSUOSC:
++		val = csr_read(hpmcounter26);
++		break;
++	case RISCV_PMU_LSUSQDC:
++		val = csr_read(hpmcounter27);
++		break;
++	case RISCV_PMU_LSUSQDDC:
++		val = csr_read(hpmcounter28);
++		break;
++	default:
++		WARN_ON_ONCE(idx < 0 ||	idx > RISCV_MAX_COUNTERS);
++		return -EINVAL;
++	}
++
++	return val;
++}
++
++static inline void write_counter(int idx, u64 value)
++{
++	switch (idx) {
++	case RISCV_PMU_CYCLE:
++		WRITE_COUNTER(RISCV_PMU_CYCLE, value);
++		break;
++	case RISCV_PMU_INSTRET:
++		WRITE_COUNTER(RISCV_PMU_INSTRET, value);
++		break;
++	case RISCV_PMU_L1ICAC:
++		WRITE_COUNTER(RISCV_PMU_L1ICAC, value);
++		break;
++	case RISCV_PMU_L1ICMC:
++		WRITE_COUNTER(RISCV_PMU_L1ICMC, value);
++		break;
++	case RISCV_PMU_IUTLBMC:
++		WRITE_COUNTER(RISCV_PMU_IUTLBMC, value);
++		break;
++	case RISCV_PMU_DUTLBMC:
++		WRITE_COUNTER(RISCV_PMU_DUTLBMC, value);
++		break;
++	case RISCV_PMU_JTLBMC:
++		WRITE_COUNTER(RISCV_PMU_JTLBMC, value);
++		break;
++	case RISCV_PMU_CBMC:
++		WRITE_COUNTER(RISCV_PMU_CBMC, value);
++		break;
++	case RISCV_PMU_CBIC:
++		WRITE_COUNTER(RISCV_PMU_CBIC, value);
++		break;
++	case RISCV_PMU_IBMC:
++		WRITE_COUNTER(RISCV_PMU_IBMC, value);
++		break;
++	case RISCV_PMU_IBIC:
++		WRITE_COUNTER(RISCV_PMU_IBIC, value);
++		break;
++	case RISCV_PMU_LSUSFC:
++		WRITE_COUNTER(RISCV_PMU_LSUSFC, value);
++		break;
++	case RISCV_PMU_STC:
++		WRITE_COUNTER(RISCV_PMU_STC, value);
++		break;
++	case RISCV_PMU_L1DCRAC:
++		WRITE_COUNTER(RISCV_PMU_L1DCRAC, value);
++		break;
++	case RISCV_PMU_L1DCRMC:
++		WRITE_COUNTER(RISCV_PMU_L1DCRMC, value);
++		break;
++	case RISCV_PMU_L1DCWAC:
++		WRITE_COUNTER(RISCV_PMU_L1DCWAC, value);
++		break;
++	case RISCV_PMU_L1DCWMC:
++		WRITE_COUNTER(RISCV_PMU_L1DCWMC, value);
++		break;
++	case RISCV_PMU_L2CRAC:
++		WRITE_COUNTER(RISCV_PMU_L2CRAC, value);
++		break;
++	case RISCV_PMU_L2CRMC:
++		WRITE_COUNTER(RISCV_PMU_L2CRMC, value);
++		break;
++	case RISCV_PMU_L2CWAC:
++		WRITE_COUNTER(RISCV_PMU_L2CWAC, value);
++		break;
++	case RISCV_PMU_L2CWMC:
++		WRITE_COUNTER(RISCV_PMU_L2CWMC, value);
++		break;
++	case RISCV_PMU_RFLFC:
++		WRITE_COUNTER(RISCV_PMU_RFLFC, value);
++		break;
++	case RISCV_PMU_RFRLFC:
++		WRITE_COUNTER(RISCV_PMU_RFRLFC, value);
++		break;
++	case RISCV_PMU_RFIC:
++		WRITE_COUNTER(RISCV_PMU_RFIC, value);
++		break;
++	case RISCV_PMU_LSUC4SC:
++		WRITE_COUNTER(RISCV_PMU_LSUC4SC, value);
++		break;
++	case RISCV_PMU_LSUOSC:
++		WRITE_COUNTER(RISCV_PMU_LSUOSC, value);
++		break;
++	case RISCV_PMU_LSUSQDC:
++		WRITE_COUNTER(RISCV_PMU_LSUSQDC, value);
++		break;
++	case RISCV_PMU_LSUSQDDC:
++		WRITE_COUNTER(RISCV_PMU_LSUSQDDC, value);
++		break;
++	default:
++		WARN_ON_ONCE(idx < 0 ||	idx > RISCV_MAX_COUNTERS);
++	}
++}
++
++int riscv_pmu_event_is_frequent(int idx)
++{
++	return  idx >= RISCV_PMU_CYCLE &&
++		idx <= RISCV_PMU_L1DCWMC;
++}
++
++int riscv_pmu_event_set_period(struct perf_event *event)
++{
++	struct hw_perf_event *hwc = &event->hw;
++	s64 left = local64_read(&hwc->period_left);
++	s64 period = hwc->sample_period;
++	int ret = 0;
++
++	if (period < 4096 && period != 0 &&
++	    riscv_pmu_event_is_frequent(hwc->idx)) {
++		hwc->sample_period = period = 4096;
++	}
++
++	if (unlikely(left <= -period)) {
++		left = period;
++		local64_set(&hwc->period_left, left);
++		hwc->last_period = period;
++		ret = 1;
++	}
++
++	if (unlikely(left <= 0)) {
++		left += period;
++		local64_set(&hwc->period_left, left);
++		hwc->last_period = period;
++		ret = 1;
++	}
++
++	if (left < 0)
++		left = riscv_pmu.max_period;
++
++	/*
++	 * The hw event starts counting from this event offset,
++	 * mark it to be able to extract future "deltas":
++	 */
++	local64_set(&hwc->prev_count, (u64)(-left));
++	csr_write(SCOUNTEROF, csr_read(SCOUNTEROF) & ~BIT(hwc->idx));
++	write_counter(hwc->idx, (u64)(-left));
++
++	perf_event_update_userpage(event);
++
++	return ret;
++}
++
++static void riscv_perf_event_update(struct perf_event *event,
++				   struct hw_perf_event *hwc)
++{
++	uint64_t prev_raw_count = local64_read(&hwc->prev_count);
++	/*
++	 * Sign extend count value to 64bit, otherwise delta calculation
++	 * would be incorrect when overflow occurs.
++	 */
++	uint64_t new_raw_count = read_counter(hwc->idx);
++	int64_t delta = new_raw_count - prev_raw_count;
++
++	/*
++	 * We aren't afraid of hwc->prev_count changing beneath our feet
++	 * because there's no way for us to re-enter this function anytime.
++	 */
++	local64_set(&hwc->prev_count, new_raw_count);
++	local64_add(delta, &event->count);
++	local64_sub(delta, &hwc->period_left);
++}
++
++static void riscv_pmu_read(struct perf_event *event)
++{
++	riscv_perf_event_update(event, &event->hw);
++}
++
++static int riscv_pmu_cache_event(u64 config)
++{
++	unsigned int cache_type, cache_op, cache_result;
++
++	cache_type      = (config >>  0) & 0xff;
++	cache_op	= (config >>  8) & 0xff;
++	cache_result    = (config >> 16) & 0xff;
++
++	if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
++		return -EINVAL;
++	if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
++		return -EINVAL;
++	if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
++		return -EINVAL;
++
++	return riscv_cache_event_map[cache_type][cache_op][cache_result];
++}
++
++static int riscv_pmu_event_init(struct perf_event *event)
++{
++	struct hw_perf_event *hwc = &event->hw;
++	int ret;
++
++	switch (event->attr.type) {
++	case PERF_TYPE_HARDWARE:
++		if (event->attr.config >= PERF_COUNT_HW_MAX)
++			return -ENOENT;
++		ret = riscv_hw_event_map[event->attr.config];
++		if (ret == RISCV_OP_UNSUPP)
++			return -ENOENT;
++		hwc->idx = ret;
++		break;
++	case PERF_TYPE_HW_CACHE:
++		ret = riscv_pmu_cache_event(event->attr.config);
++		if (ret == RISCV_OP_UNSUPP)
++			return -ENOENT;
++		hwc->idx = ret;
++		break;
++	case PERF_TYPE_RAW:
++		if (event->attr.config < 0 || event->attr.config >
++		    RISCV_MAX_COUNTERS)
++			return -ENOENT;
++		hwc->idx = event->attr.config;
++		break;
++	default:
++		return -ENOENT;
++	}
++
++	return 0;
++}
++
++static void riscv_pmu_enable(struct pmu *pmu)
++{
++}
++
++/* stops all counters */
++static void riscv_pmu_disable(struct pmu *pmu)
++{
++}
++
++static void riscv_pmu_start(struct perf_event *event, int flags)
++{
++	unsigned long flg;
++	struct hw_perf_event *hwc = &event->hw;
++	int idx = hwc->idx;
++
++	if (WARN_ON_ONCE(idx == -1))
++		return;
++
++	if (flags & PERF_EF_RELOAD)
++		WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE));
++
++	hwc->state = 0;
++
++	riscv_pmu_event_set_period(event);
++
++	local_irq_save(flg);
++
++	csr_write(SCOUNTERINTEN, BIT(idx) | csr_read(SCOUNTERINTEN));
++
++	local_irq_restore(flg);
++}
++
++static void riscv_pmu_stop_event(struct perf_event *event)
++{
++	unsigned long flg;
++	struct hw_perf_event *hwc = &event->hw;
++	int idx = hwc->idx;
++
++	local_irq_save(flg);
++
++	csr_write(SCOUNTERINTEN, ~BIT(idx) & csr_read(SCOUNTERINTEN));
++
++	local_irq_restore(flg);
++}
++
++static void riscv_pmu_stop(struct perf_event *event, int flags)
++{
++	if (!(event->hw.state & PERF_HES_STOPPED)) {
++		riscv_pmu_stop_event(event);
++		event->hw.state |= PERF_HES_STOPPED;
++	}
++
++	if ((flags & PERF_EF_UPDATE) &&
++	    !(event->hw.state & PERF_HES_UPTODATE)) {
++		riscv_perf_event_update(event, &event->hw);
++		event->hw.state |= PERF_HES_UPTODATE;
++	}
++}
++
++static void riscv_pmu_del(struct perf_event *event, int flags)
++{
++	struct pmu_hw_events *hw_events = this_cpu_ptr(riscv_pmu.hw_events);
++	struct hw_perf_event *hwc = &event->hw;
++
++	riscv_pmu_stop(event, PERF_EF_UPDATE);
++
++	hw_events->events[hwc->idx] = NULL;
++
++	perf_event_update_userpage(event);
++}
++
++/* allocate hardware counter and optionally start counting */
++static int riscv_pmu_add(struct perf_event *event, int flags)
++{
++	struct pmu_hw_events *hw_events = this_cpu_ptr(riscv_pmu.hw_events);
++	struct hw_perf_event *hwc = &event->hw;
++
++	hw_events->events[hwc->idx] = event;
++
++	hwc->state = PERF_HES_UPTODATE | PERF_HES_STOPPED;
++
++	if (flags & PERF_EF_START)
++		riscv_pmu_start(event, PERF_EF_RELOAD);
++
++	perf_event_update_userpage(event);
++
++	return 0;
++}
++
++irqreturn_t riscv_pmu_handle_irq(void)
++{
++	struct perf_sample_data data;
++	struct pmu_hw_events *cpuc = this_cpu_ptr(riscv_pmu.hw_events);
++	struct pt_regs *regs;
++	int idx;
++
++	/*
++	 * Did an overflow occur?
++	 */
++	if (!csr_read(SCOUNTEROF))
++		return IRQ_NONE;
++
++	/*
++	 * Handle the counter(s) overflow(s)
++	 */
++	regs = get_irq_regs();
++
++	for (idx = 0; idx < RISCV_MAX_COUNTERS; ++idx) {
++		struct perf_event *event = cpuc->events[idx];
++		struct hw_perf_event *hwc;
++
++		/* Ignore if we don't have an event. */
++		if (!event)
++			continue;
++		/*
++		 * We have a single interrupt for all counters. Check that
++		 * each counter has overflowed before we process it.
++		 */
++		if (!(csr_read(SCOUNTEROF) & BIT(idx)))
++			continue;
++
++		hwc = &event->hw;
++		riscv_perf_event_update(event, &event->hw);
++		perf_sample_data_init(&data, 0, hwc->last_period);
++		riscv_pmu_event_set_period(event);
++
++		if (perf_event_overflow(event, &data, regs))
++			riscv_pmu_stop_event(event);
++	}
++
++	/*
++	 * Handle the pending perf events.
++	 *
++	 * Note: this call *must* be run with interrupts disabled. For
++	 * platforms that can have the PMU interrupts raised as an NMI, this
++	 * will not work.
++	 */
++	irq_work_run();
++
++	return IRQ_HANDLED;
++}
++
++static void riscv_pmu_free_irq(void)
++{
++	int irq;
++	struct platform_device *pmu_device = riscv_pmu.plat_device;
++
++	irq = platform_get_irq(pmu_device, 0);
++	if (irq >= 0)
++		free_percpu_irq(irq, this_cpu_ptr(riscv_pmu.hw_events));
++}
++
++static int init_hw_perf_events(void)
++{
++	riscv_pmu.hw_events = alloc_percpu_gfp(struct pmu_hw_events,
++					      GFP_KERNEL);
++	if (!riscv_pmu.hw_events) {
++		pr_info("failed to allocate per-cpu PMU data.\n");
++		return -ENOMEM;
++	}
++
++	riscv_pmu.pmu = (struct pmu) {
++		.pmu_enable     = riscv_pmu_enable,
++		.pmu_disable    = riscv_pmu_disable,
++		.event_init     = riscv_pmu_event_init,
++		.add	    = riscv_pmu_add,
++		.del	    = riscv_pmu_del,
++		.start	  = riscv_pmu_start,
++		.stop	   = riscv_pmu_stop,
++		.read	   = riscv_pmu_read,
++	};
++
++	return 0;
++}
++
++static int riscv_pmu_starting_cpu(unsigned int cpu)
++{
++	sbi_set_pmu(1);
++	csr_set(sie, SIE_SMIE);
++	return 0;
++}
++
++static int riscv_pmu_dying_cpu(unsigned int cpu)
++{
++	csr_clear(sie, SIE_SMIE);
++	return 0;
++}
++
++int riscv_pmu_device_probe(struct platform_device *pdev,
++			  const struct of_device_id *of_table)
++{
++	int ret;
++
++	ret = init_hw_perf_events();
++	if (ret) {
++		pr_notice("[perf] failed to probe PMU!\n");
++		return ret;
++	}
++	riscv_pmu.max_period = ULONG_MAX;
++	riscv_pmu.plat_device = pdev;
++
++	ret = cpuhp_setup_state(CPUHP_AP_PERF_RISCV_ONLINE, "perf riscv:online",
++				riscv_pmu_starting_cpu,
++				riscv_pmu_dying_cpu);
++	if (ret) {
++		riscv_pmu_free_irq();
++		free_percpu(riscv_pmu.hw_events);
++		return ret;
++	}
++
++	ret = perf_pmu_register(&riscv_pmu.pmu, "thead_xt_pmu", PERF_TYPE_RAW);
++	if (ret) {
++		riscv_pmu_free_irq();
++		free_percpu(riscv_pmu.hw_events);
++	}
++
++	return ret;
++}
++
++const static struct of_device_id riscv_pmu_of_device_ids[] = {
++	{.compatible = "riscv,thead_xt_pmu"},
++	{.compatible = "riscv,c910_pmu"},
++	{},
++};
++
++static int riscv_pmu_dev_probe(struct platform_device *pdev)
++{
++	return riscv_pmu_device_probe(pdev, riscv_pmu_of_device_ids);
++}
++
++static struct platform_driver riscv_pmu_driver = {
++	.driver = {
++		   .name = "thead_xt_pmu",
++		   .of_match_table = riscv_pmu_of_device_ids,
++		   },
++	.probe = riscv_pmu_dev_probe,
++};
++
++int __init riscv_pmu_probe(void)
++{
++	int ret;
++
++	ret = platform_driver_register(&riscv_pmu_driver);
++	if (ret)
++		pr_notice("[perf] PMU initialization failed\n");
++	else
++		pr_notice("[perf] PMU initialization done\n");
++
++	return ret;
++}
++device_initcall(riscv_pmu_probe);
+diff -Nur linux-5.4.36/drivers/rtc/rtc-xgene.c kernel/drivers/rtc/rtc-xgene.c
+--- linux-5.4.36/drivers/rtc/rtc-xgene.c	2020-04-29 14:33:25.000000000 +0000
++++ kernel/drivers/rtc/rtc-xgene.c	2020-09-14 01:45:17.783702016 +0000
+@@ -26,11 +26,13 @@
+ #define  RTC_CCR_MASK		BIT(1)
+ #define  RTC_CCR_EN		BIT(2)
+ #define  RTC_CCR_WEN		BIT(3)
++#define  RTC_CCR_PSCLR		BIT(4)
+ #define RTC_STAT		0x10
+ #define  RTC_STAT_BIT		BIT(0)
+ #define RTC_RSTAT		0x14
+ #define RTC_EOI			0x18
+ #define RTC_VER			0x1C
++#define RTC_CPSR		0x20
+ 
+ struct xgene_rtc_dev {
+ 	struct rtc_device *rtc;
+@@ -140,6 +142,7 @@
+ 	struct resource *res;
+ 	int ret;
+ 	int irq;
++	u32 freq;
+ 
+ 	pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
+ 	if (!pdata)
+@@ -175,8 +178,15 @@
+ 	if (ret)
+ 		return ret;
+ 
+-	/* Turn on the clock and the crystal */
+-	writel(RTC_CCR_EN, pdata->csr_base + RTC_CCR);
++	freq = clk_get_rate(pdata->clk);
++	if (freq) {
++		writel(freq, pdata->csr_base + RTC_CPSR);
++		/* Turn on the clock and prescaler counter */
++		writel(RTC_CCR_EN | RTC_CCR_PSCLR, pdata->csr_base + RTC_CCR);
++	} else {
++		/* Turn on the clock and the crystal */
++		writel(RTC_CCR_EN, pdata->csr_base + RTC_CCR);
++	}
+ 
+ 	ret = device_init_wakeup(&pdev->dev, 1);
+ 	if (ret) {
+diff -Nur linux-5.4.36/include/linux/cpuhotplug.h kernel/include/linux/cpuhotplug.h
+--- linux-5.4.36/include/linux/cpuhotplug.h	2020-04-29 14:33:25.000000000 +0000
++++ kernel/include/linux/cpuhotplug.h	2020-09-03 06:01:17.919989627 +0000
+@@ -174,6 +174,7 @@
+ 	CPUHP_AP_PERF_POWERPC_CORE_IMC_ONLINE,
+ 	CPUHP_AP_PERF_POWERPC_THREAD_IMC_ONLINE,
+ 	CPUHP_AP_PERF_POWERPC_TRACE_IMC_ONLINE,
++	CPUHP_AP_PERF_RISCV_ONLINE,
+ 	CPUHP_AP_WATCHDOG_ONLINE,
+ 	CPUHP_AP_WORKQUEUE_ONLINE,
+ 	CPUHP_AP_RCUTREE_ONLINE,
+diff -Nur linux-5.4.36/include/uapi/linux/elf.h kernel/include/uapi/linux/elf.h
+--- linux-5.4.36/include/uapi/linux/elf.h	2020-04-29 14:33:25.000000000 +0000
++++ kernel/include/uapi/linux/elf.h	2020-09-03 06:01:18.158989617 +0000
+@@ -428,6 +428,7 @@
+ #define NT_MIPS_DSP	0x800		/* MIPS DSP ASE registers */
+ #define NT_MIPS_FP_MODE	0x801		/* MIPS floating-point mode */
+ #define NT_MIPS_MSA	0x802		/* MIPS SIMD registers */
++#define NT_RISCV_VECTOR	0x900		/* RISC-V vector registers */
+ 
+ /* Note header in a PT_NOTE section */
+ typedef struct elf32_note {
+diff -Nur linux-5.4.36/include/uapi/linux/kexec.h kernel/include/uapi/linux/kexec.h
+--- linux-5.4.36/include/uapi/linux/kexec.h	2020-04-29 14:33:25.000000000 +0000
++++ kernel/include/uapi/linux/kexec.h	2020-09-03 06:01:18.167989617 +0000
+@@ -42,6 +42,7 @@
+ #define KEXEC_ARCH_MIPS_LE (10 << 16)
+ #define KEXEC_ARCH_MIPS    ( 8 << 16)
+ #define KEXEC_ARCH_AARCH64 (183 << 16)
++#define KEXEC_ARCH_RISCV   (243 << 16)
+ 
+ /* The artificial cap on the number of segments passed to kexec_load. */
+ #define KEXEC_SEGMENT_MAX 16
+diff -Nur linux-5.4.36/kernel/Kconfig.hz kernel/kernel/Kconfig.hz
+--- linux-5.4.36/kernel/Kconfig.hz	2020-04-29 14:33:25.000000000 +0000
++++ kernel/kernel/Kconfig.hz	2020-09-03 06:01:18.218989615 +0000
+@@ -16,6 +16,8 @@
+ 	 environment leading to NR_CPUS * HZ number of timer interrupts
+ 	 per second.
+ 
++	config HZ_12
++		bool "12 HZ"
+ 
+ 	config HZ_100
+ 		bool "100 HZ"
+@@ -50,6 +52,7 @@
+ 
+ config HZ
+ 	int
++	default 12 if HZ_12
+ 	default 100 if HZ_100
+ 	default 250 if HZ_250
+ 	default 300 if HZ_300

+ 0 - 24
recipes-kernel/linux/linux-mainline-common.inc

@@ -1,24 +0,0 @@
-DESCRIPTION = "Mainline Linux Kernel"
-SECTION = "kernel"
-LICENSE = "GPLv2"
-LIC_FILES_CHKSUM = "file://${S}/COPYING;md5=bbea815ee2795b2f4230826c0c6b8814"
-
-inherit kernel
-require recipes-kernel/linux/linux-yocto.inc
-
-LINUX_VERSION_EXTENSION = ""
-
-PV = "${LINUX_VERSION}+git${SRCPV}"
-
-KCONFIG_MODE="--alldefconfig"
-
-KBUILD_DEFCONFIG_qemuriscv32 = "rv32_defconfig"
-KBUILD_DEFCONFIG_qemuriscv64 = "defconfig"
-KBUILD_DEFCONFIG_freedom-u540 = "defconfig"
-
-COMPATIBLE_MACHINE = "(qemuriscv32|qemuriscv64|freedom-u540)"
-
-KERNEL_DEVICETREE_freedom-u540 = "sifive/${RISCV_SBI_FDT}"
-
-KERNEL_FEATURES_remove = "features/debug/printk.scc"
-KERNEL_FEATURES_remove = "features/kernel-sample/kernel-sample.scc"

+ 0 - 17
recipes-kernel/linux/linux-mainline_5.4.bb

@@ -1,17 +0,0 @@
-require recipes-kernel/linux/linux-mainline-common.inc
-
-LINUX_VERSION ?= "5.4.x"
-KERNEL_VERSION_SANITY_SKIP="1"
-
-BRANCH = "linux-5.4.y"
-SRCREV = "${AUTOREV}"
-SRC_URI = " \
-    git://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git;branch=${BRANCH} \
-"
-
-SRC_URI_append_freedom-u540 = " \
-    file://extra.cfg \
-    file://0001-PCI-microsemi-Add-host-driver-for-Microsemi-PCIe-con.patch \
-    file://0002-Microsemi-PCIe-expansion-board-DT-entry.patch \
-    file://0003-HACK-Revert-of-device-Really-only-set-bus-DMA-mask-w.patch \
-"

+ 35 - 0
recipes-kernel/linux/linux-thead_5.4.36.bb

@@ -0,0 +1,35 @@
+inherit kernel
+require recipes-kernel/linux/linux-yocto.inc
+
+LIC_FILES_CHKSUM = "file://COPYING;md5=bbea815ee2795b2f4230826c0c6b8814"
+
+FILESEXTRAPATHS_prepend := "${THISDIR}/files/xuantie-c910:"
+
+SRC_URI = " \
+    https://cdn.kernel.org/pub/linux/kernel/v5.x/linux-${PV}.tar.xz;name=kernel \
+    file://xuantie-linux-5.4.36.patch \
+    file://light-c910-dts.patch \
+    file://light-c910_defconfig \
+    file://qemu-c910_defconfig \
+"
+
+SRC_URI[kernel.md5sum] = "4c4edf3e7d127e4f1a471aa3a370f3e7"
+SRC_URI[kernel.sha256sum] = "b9faea98122e8316af8fb428c942e81797b5d28a8fc59a24a4e47959e3765b8d"
+
+
+LINUX_VERSION ?= "${PV}"
+LINUX_VERSION_EXTENSION ?= "-thead"
+
+SRCREV="${AUTOREV}"
+
+DEPENDS += "elfutils-native"
+
+COMPATIBLE_MACHINE = "${MACHINE}"
+
+S = "${WORKDIR}/linux-${PV}"
+
+# KBUILD_DEFCONFIG_qemu64-c910 = "qemux-c910_defconfig"
+# KBUILD_DEFCONFIG_light-c910 = "light-c910_defconfig"
+# KBUILD_DEFCONFIG_ice-c910 = "ice-c910_defconfig"
+
+KCONFIG_MODE="--alldefconfig"

+ 6 - 4
setup.sh

@@ -36,10 +36,11 @@ export BASH_SOURCE="openembedded-core/oe-init-build-env"
 
 # add the missing layers
 echo "Adding layers"
-bitbake-layers add-layer ../meta-openembedded/meta-oe
-bitbake-layers add-layer ../meta-openembedded/meta-python
-bitbake-layers add-layer ../meta-openembedded/meta-multimedia
-bitbake-layers add-layer ../meta-openembedded/meta-networking
+#bitbake-layers add-layer ../meta-openembedded/meta-oe
+#bitbake-layers add-layer ../meta-openembedded/meta-python
+#bitbake-layers add-layer ../meta-openembedded/meta-multimedia
+#bitbake-layers add-layer ../meta-openembedded/meta-networking
+bitbake-layers add-layer ../meta-external-toolchain
 bitbake-layers add-layer ../meta-riscv
 
 # fix the configuration
@@ -72,6 +73,7 @@ DISTRO_FEATURES_append = " largefile opengl ptest multiarch wayland pam  systemd
 DISTRO_FEATURES_BACKFILL_CONSIDERED += "sysvinit"
 VIRTUAL-RUNTIME_init_manager = "systemd"
 HOSTTOOLS_NONFATAL_append = " ssh"
+DISTRO_FEATURES_BACKFILL_CONSIDERED += "gobject-introspection-data"
 EOF
 
 echo "To build an image run"

+ 5 - 5
tools/manifests/riscv-yocto.xml

@@ -6,11 +6,11 @@
   <default remote="aone" revision="master" />
   
 
-  <project name="meta-riscv" remote="aone" path="meta-riscv" revision="master" />
-  <project name="openembedded-core" remote="gitee_thead_yocoto" path="openembedded-core" revision="master" />
-  <project name="bitbake" remote="gitee_thead_yocoto" path="openembedded-core/bitbake" revision="master" />
-  <project name="meta-openembedded" remote="gitee_thead_yocoto" path="meta-openembedded" revision="master" />
-  <project name="meta-external-toolchain" remote="aone" path="meta-external-toolchain" revision="master" />
+  <project name="meta-riscv" remote="openembedded" path="meta-riscv" revision="master" />
+  <project name="openembedded-core" remote="openembedded" path="openembedded-core" revision="master" />
+  <project name="bitbake" remote="openembedded" path="openembedded-core/bitbake" revision="master" />
+  <project name="meta-openembedded" remote="openembedded" path="meta-openembedded" revision="master" />
+  <project name="meta-external-toolchain" remote="openembedded" path="meta-external-toolchain" revision="master" />
 
 </manifest>