0001-PCI-microsemi-Add-host-driver-for-Microsemi-PCIe-con.patch 23 KB

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  1. From 3e5cd0fb40635b75140d8cc3b38d66eaaefcf901 Mon Sep 17 00:00:00 2001
  2. From: Daire McNamara <daire.mcnamara@microchip.com>
  3. Date: Fri, 15 Feb 2019 16:24:24 +0000
  4. Subject: [PATCH 1/4] PCI: microsemi: Add host driver for Microsemi PCIe
  5. controller
  6. This patch adds support to the Microsemi/Microchip PolarFire
  7. PCIe controller when configured in host (Root Complex) mode.
  8. Signed-off-by: Daire McNamara <daire.mcnamara@microchip.com>
  9. Upstream-Status: Inappropriate [not author]
  10. ---
  11. drivers/pci/controller/Kconfig | 8 +
  12. drivers/pci/controller/Makefile | 1 +
  13. drivers/pci/controller/pcie-microsemi.c | 764 ++++++++++++++++++++++++
  14. 3 files changed, 773 insertions(+)
  15. create mode 100644 drivers/pci/controller/pcie-microsemi.c
  16. diff --git a/drivers/pci/controller/Kconfig b/drivers/pci/controller/Kconfig
  17. index fe9f9f13ce11..800b0b61dedf 100644
  18. --- a/drivers/pci/controller/Kconfig
  19. +++ b/drivers/pci/controller/Kconfig
  20. @@ -281,5 +281,13 @@ config VMD
  21. To compile this driver as a module, choose M here: the
  22. module will be called vmd.
  23. +config PCIE_MICROSEMI
  24. + bool "Microsemi AXI PCIe host bridge support"
  25. + depends on PCI_MSI && OF
  26. + help
  27. + Say 'Y' here if you want kernel to support the Microsemi AXI PCIe
  28. + Host Bridge driver.
  29. +
  30. +
  31. source "drivers/pci/controller/dwc/Kconfig"
  32. endmenu
  33. diff --git a/drivers/pci/controller/Makefile b/drivers/pci/controller/Makefile
  34. index d56a507495c5..c3b76ff221be 100644
  35. --- a/drivers/pci/controller/Makefile
  36. +++ b/drivers/pci/controller/Makefile
  37. @@ -28,6 +28,7 @@ obj-$(CONFIG_PCIE_ROCKCHIP_HOST) += pcie-rockchip-host.o
  38. obj-$(CONFIG_PCIE_MEDIATEK) += pcie-mediatek.o
  39. obj-$(CONFIG_PCIE_MOBIVEIL) += pcie-mobiveil.o
  40. obj-$(CONFIG_PCIE_TANGO_SMP8759) += pcie-tango.o
  41. +obj-$(CONFIG_PCIE_MICROSEMI) += pcie-microsemi.o
  42. obj-$(CONFIG_VMD) += vmd.o
  43. # pcie-hisi.o quirks are needed even without CONFIG_PCIE_DW
  44. obj-y += dwc/
  45. diff --git a/drivers/pci/controller/pcie-microsemi.c b/drivers/pci/controller/pcie-microsemi.c
  46. new file mode 100644
  47. index 000000000000..60e185bebc60
  48. --- /dev/null
  49. +++ b/drivers/pci/controller/pcie-microsemi.c
  50. @@ -0,0 +1,764 @@
  51. +// SPDX-License-Identifier: GPL-2.0+
  52. +/*
  53. + * PCIe host controller driver for Microsemi AXI PCIe Bridge
  54. + *
  55. + * Copyright (c) 2018 - 2019 Microsemi Corporation.
  56. + *
  57. + * Based on:
  58. + * pcie-rcar.c
  59. + * pcie-xilinx.c
  60. + * pcie-altera.c
  61. + */
  62. +
  63. +#include <linux/bitmap.h>
  64. +#include <linux/interrupt.h>
  65. +#include <linux/irq.h>
  66. +#include <linux/irqdomain.h>
  67. +#include <linux/kernel.h>
  68. +#include <linux/init.h>
  69. +#include <linux/msi.h>
  70. +#include <linux/of_address.h>
  71. +#include <linux/of_pci.h>
  72. +#include <linux/of_platform.h>
  73. +#include <linux/of_irq.h>
  74. +#include <linux/pci.h>
  75. +#include <linux/platform_device.h>
  76. +
  77. +#include "../pci.h"
  78. +
  79. +/* ECAM definitions */
  80. +#define ECAM_BUS_NUM_SHIFT 20
  81. +#define ECAM_DEV_NUM_SHIFT 12
  82. +
  83. +/* Number of MSI IRQs */
  84. +#define MICROSEMI_NUM_MSI_IRQS 32
  85. +#define MICROSEMI_NUM_MSI_IRQS_CODED 5
  86. +
  87. +/* PCIe Bridge Phy and Controller Phy offsets */
  88. +#define MICROSEMI_PCIE0_BRIDGE_ADDR 0x00004000u
  89. +#define MICROSEMI_PCIE0_CTRL_ADDR 0x00006000u
  90. +
  91. +#define MICROSEMI_PCIE1_BRIDGE_ADDR 0x00008000u
  92. +#define MICROSEMI_PCIE1_CTRL_ADDR 0x0000a000u
  93. +
  94. +/* PCIe Controller Phy Regs */
  95. +#define MICROSEMI_SEC_ERROR_INT 0x28
  96. +#define SEC_ERROR_INT_TX_RAM_SEC_ERR_INT GENMASK(3, 0)
  97. +#define SEC_ERROR_INT_RX_RAM_SEC_ERR_INT GENMASK(7, 4)
  98. +#define SEC_ERROR_INT_PCIE2AXI_RAM_SEC_ERR_INT GENMASK(11, 8)
  99. +#define SEC_ERROR_INT_AXI2PCIE_RAM_SEC_ERR_INT GENMASK(15, 12)
  100. +#define MICROSEMI_SEC_ERROR_INT_MASK 0x2c
  101. +#define MICROSEMI_DED_ERROR_INT 0x30
  102. +#define DED_ERROR_INT_TX_RAM_DED_ERR_INT GENMASK(3, 0)
  103. +#define DED_ERROR_INT_RX_RAM_DED_ERR_INT GENMASK(7, 4)
  104. +#define DED_ERROR_INT_PCIE2AXI_RAM_DED_ERR_INT GENMASK(11, 8)
  105. +#define DED_ERROR_INT_AXI2PCIE_RAM_DED_ERR_INT GENMASK(15, 12)
  106. +#define MICROSEMI_DED_ERROR_INT_MASK 0x34
  107. +#define MICROSEMI_ECC_CONTROL 0x38
  108. +#define ECC_CONTROL_AXI2PCIE_RAM_ECC_BYPASS BIT(27)
  109. +#define ECC_CONTROL_PCIE2AXI_RAM_ECC_BYPASS BIT(26)
  110. +#define ECC_CONTROL_RX_RAM_ECC_BYPASS BIT(25)
  111. +#define ECC_CONTROL_TX_RAM_ECC_BYPASS BIT(24)
  112. +#define MICROSEMI_LTSSM_STATE 0x5c
  113. +#define MICROSEMI_LTSSM_L0_STATE 0x10
  114. +#define MICROSEMI_PCIE_EVENT_INT 0x14c
  115. +#define PCIE_EVENT_INT_L2_EXIT_INT BIT(0)
  116. +#define PCIE_EVENT_INT_HOTRST_EXIT_INT BIT(1)
  117. +#define PCIE_EVENT_INT_DLUP_EXIT_INT BIT(2)
  118. +#define PCIE_EVENT_INT_L2_EXIT_INT_MASK BIT(16)
  119. +#define PCIE_EVENT_INT_HOTRST_EXIT_INT_MASK BIT(17)
  120. +#define PCIE_EVENT_INT_DLUP_EXIT_INT_MASK BIT(18)
  121. +
  122. +/* PCIe Bridge Phy Regs */
  123. +#define MICROSEMI_PCIE_PCI_IDS_DW1 0x9c
  124. +#define MICROSEMI_IMASK_LOCAL 0x180
  125. +#define MICROSEMI_PCIE_LOCAL_INT_ENABLE 0x0f000000u
  126. +#define MICROSEMI_PCI_INTS 0x0f000000u
  127. +#define MICROSEMI_PM_MSI_INT_SHIFT 24
  128. +#define MICROSEMI_PCIE_ENABLE_MSI 0x10000000u
  129. +#define MICROSEMI_MSI_INT 0x10000000u
  130. +#define MICROSEMI_MSI_INT_SHIFT 28
  131. +#define MICROSEMI_ISTATUS_LOCAL 0x184
  132. +#define MICROSEMI_IMASK_HOST 0x188
  133. +#define MICROSEMI_ISTATUS_HOST 0x18c
  134. +#define MICROSEMI_ISTATUS_MSI 0x194
  135. +
  136. +/* PCIe AXI slave table init defines */
  137. +#define MICROSEMI_ATR0_AXI4_SLV0_SRCADDR_PARAM 0x800u
  138. +#define ATR_SIZE_SHIFT 1
  139. +#define ATR_IMPL_ENABLE 1
  140. +#define MICROSEMI_ATR0_AXI4_SLV0_SRC_ADDR 0x804u
  141. +#define MICROSEMI_ATR0_AXI4_SLV0_TRSL_ADDR_LSB 0x808u
  142. +#define MICROSEMI_ATR0_AXI4_SLV0_TRSL_ADDR_UDW 0x80cu
  143. +#define MICROSEMI_ATR0_AXI4_SLV0_TRSL_PARAM 0x810u
  144. +#define MICROSEMI_PCIE_TX_RX_INTERFACE 0x00000000u
  145. +#define MICROSEMI_PCIE_CONFIG_INTERFACE 0x00000001u
  146. +
  147. +#define MICROSEMI_ATR0_AXI4_SLV_SIZE 32
  148. +
  149. +/* PCIe Master table init defines */
  150. +#define MICROSEMI_ATR0_PCIE_WIN0_SRCADDR_31_12 0x600u
  151. +#define MICROSEMI_ATR0_PCIE_WIN0_SIZE 0x1f
  152. +#define MICROSEMI_ATR0_PCIE_WIN0_SIZE_SHIFT 1
  153. +#define MICROSEMI_ATR0_PCIE_WIN0_SRCADDR_63_32 0x604u
  154. +
  155. +#define MICROSEMI_MSI_MSG_ADDR 0x190u
  156. +
  157. +/* PCIe Config space MSI capability structure */
  158. +#define MSI_CAP_CTRL_OFFSET 0xe0u
  159. +#define MSI_ENABLE (0x01u << 16)
  160. +#define MSI_ENABLE_MULTI (MICROSEMI_NUM_MSI_IRQS_CODED << 20)
  161. +#define MSI_MSG_ADDR_OFFSET 0xe4u
  162. +#define MSI_MSG_UPPER_ADDR_OFFSET 0xe8u
  163. +#define MSI_MSG_DATA_OFFSET 0xf0u
  164. +
  165. +/**
  166. + * struct microsemi_pcie_port - PCIe port information
  167. + * @pcie_base_addr: IO Mapped Register Base
  168. + * @axi_base_addr: AMBA Mapped Register Base
  169. + * @irq: Interrupt number
  170. + * @root_busno: Root Bus number
  171. + * @dev: Device pointer
  172. + * @msi_domain: MSI IRQ domain pointer
  173. + * @leg_domain: Legacy IRQ domain pointer
  174. + * @resources: Bus Resources
  175. + */
  176. +struct microsemi_pcie_port {
  177. + struct platform_device *pdev;
  178. + void __iomem *pcie_base_addr;
  179. + void __iomem *axi_base_addr;
  180. + void __iomem *bridge_base_addr;
  181. + void __iomem *ctrl_base_addr;
  182. + int bridge;
  183. + u32 irq;
  184. + u8 root_busno;
  185. + struct device *dev;
  186. + struct irq_domain *msi_domain;
  187. + struct irq_domain *leg_domain;
  188. + struct list_head resources;
  189. + struct mutex lock; /* protect bitmap variable */
  190. + DECLARE_BITMAP(msi_irq_in_use, MICROSEMI_NUM_MSI_IRQS);
  191. +};
  192. +
  193. +static inline u32 pcie_read(struct microsemi_pcie_port *port, u32 reg)
  194. +{
  195. + return readl(port->pcie_base_addr + reg);
  196. +}
  197. +
  198. +static inline void pcie_write(struct microsemi_pcie_port *port,
  199. + u32 val, u32 reg)
  200. +{
  201. + writel(val, port->pcie_base_addr + reg);
  202. +}
  203. +
  204. +static void microsemi_pcie_enable(struct microsemi_pcie_port *port)
  205. +{
  206. + u32 enb;
  207. +
  208. + enb = readl(port->bridge_base_addr + MICROSEMI_LTSSM_STATE);
  209. + enb |= MICROSEMI_LTSSM_L0_STATE;
  210. + writel(enb, port->bridge_base_addr + MICROSEMI_LTSSM_STATE);
  211. +}
  212. +
  213. +/**
  214. + * microsemi_pcie_valid_device - Check if a valid device is present on bus
  215. + * @bus: PCI Bus structure
  216. + * @devfn: device/function
  217. + *
  218. + * Return: 'true' on success and 'false' if invalid device is found
  219. + */
  220. +static bool microsemi_pcie_valid_device(struct pci_bus *bus, unsigned int devfn)
  221. +{
  222. + struct microsemi_pcie_port *port = bus->sysdata;
  223. +
  224. + /* Only one device down on each root port */
  225. + if (bus->number == port->root_busno && devfn > 0)
  226. + return false;
  227. +
  228. + return true;
  229. +}
  230. +
  231. +/**
  232. + * microsemi_pcie_map_bus - Get configuration base
  233. + * @bus: PCI Bus structure
  234. + * @devfn: Device/function
  235. + * @where: Offset from base
  236. + *
  237. + * Return: Base address of the configuration space needed to be
  238. + * accessed.
  239. + */
  240. +static void __iomem *microsemi_pcie_map_bus(struct pci_bus *bus,
  241. + unsigned int devfn, int where)
  242. +{
  243. + struct microsemi_pcie_port *port = bus->sysdata;
  244. + int relbus;
  245. +
  246. + if (!microsemi_pcie_valid_device(bus, devfn))
  247. + return NULL;
  248. +
  249. + relbus = (bus->number << ECAM_BUS_NUM_SHIFT) |
  250. + (devfn << ECAM_DEV_NUM_SHIFT);
  251. +
  252. + return port->pcie_base_addr + relbus + where;
  253. +}
  254. +
  255. +/* PCIe operations */
  256. +static struct pci_ops microsemi_pcie_ops = {
  257. + .map_bus = microsemi_pcie_map_bus,
  258. + .read = pci_generic_config_read,
  259. + .write = pci_generic_config_write,
  260. +};
  261. +
  262. +/* MSI functions */
  263. +
  264. +/**
  265. + * microsemi_pcie_destroy_msi - Free MSI number
  266. + * @irq: IRQ to be freed
  267. + */
  268. +static void microsemi_pcie_destroy_msi(unsigned int irq)
  269. +{
  270. + struct microsemi_pcie_port *port =
  271. + msi_desc_to_pci_sysdata(irq_get_msi_desc(irq));
  272. + irq_hw_number_t hwirq = irqd_to_hwirq(irq_get_irq_data(irq));
  273. +
  274. + if (!port)
  275. + return;
  276. +
  277. + if (!test_bit(hwirq, port->msi_irq_in_use))
  278. + dev_err(port->dev, "trying to free unused MSI%d\n", irq);
  279. + else
  280. + clear_bit(hwirq, port->msi_irq_in_use);
  281. +}
  282. +
  283. +/**
  284. + * microsemi_pcie_assign_msi - Allocate MSI number
  285. + *
  286. + * Return: A valid IRQ on success and error value on failure.
  287. + */
  288. +static int microsemi_pcie_assign_msi(struct microsemi_pcie_port *port)
  289. +{
  290. + int pos;
  291. +
  292. + mutex_lock(&port->lock);
  293. + pos = find_first_zero_bit(port->msi_irq_in_use, MICROSEMI_NUM_MSI_IRQS);
  294. + if (pos < MICROSEMI_NUM_MSI_IRQS) {
  295. + set_bit(pos, port->msi_irq_in_use);
  296. + } else {
  297. + mutex_unlock(&port->lock);
  298. + return -ENOSPC;
  299. + }
  300. +
  301. + mutex_unlock(&port->lock);
  302. + return pos;
  303. +}
  304. +
  305. +/**
  306. + * microsemi_msi_teardown_irq - Destroy the MSI
  307. + * @chip: MSI Chip descriptor
  308. + * @irq: MSI IRQ to destroy
  309. + */
  310. +static void microsemi_msi_teardown_irq(struct msi_controller *chip,
  311. + unsigned int irq)
  312. +{
  313. + microsemi_pcie_destroy_msi(irq);
  314. + irq_dispose_mapping(irq);
  315. +}
  316. +
  317. +/**
  318. + * microsemi_pcie_msi_setup_irq - Setup MSI request
  319. + * @chip: MSI chip pointer
  320. + * @pdev: PCIe device pointer
  321. + * @desc: MSI descriptor pointer
  322. + *
  323. + * Return: '0' on success and error value on failure
  324. + */
  325. +static int microsemi_pcie_msi_setup_irq(struct msi_controller *chip,
  326. + struct pci_dev *pdev,
  327. + struct msi_desc *desc)
  328. +{
  329. + struct microsemi_pcie_port *port = pdev->bus->sysdata;
  330. + unsigned int irq;
  331. + int hwirq;
  332. + struct msi_msg msg;
  333. +
  334. + hwirq = microsemi_pcie_assign_msi(port);
  335. + if (hwirq < 0)
  336. + return hwirq;
  337. +
  338. + irq = irq_create_mapping(port->msi_domain, hwirq);
  339. + if (!irq)
  340. + return -EINVAL;
  341. +
  342. + irq_set_msi_desc(irq, desc);
  343. +
  344. + msg.address_hi = upper_32_bits(MICROSEMI_MSI_MSG_ADDR);
  345. + msg.address_lo = lower_32_bits(MICROSEMI_MSI_MSG_ADDR);
  346. + msg.data = hwirq;
  347. +
  348. + pci_write_msi_msg(irq, &msg);
  349. +
  350. + return 0;
  351. +}
  352. +
  353. +/* MSI Chip Descriptor */
  354. +static struct msi_controller microsemi_pcie_msi_chip = {
  355. + .setup_irq = microsemi_pcie_msi_setup_irq,
  356. + .teardown_irq = microsemi_msi_teardown_irq,
  357. +};
  358. +
  359. +/* HW Interrupt Chip Descriptor */
  360. +static struct irq_chip microsemi_msi_irq_chip = {
  361. + .name = "Microsemi PCIe MSI",
  362. + .irq_enable = pci_msi_unmask_irq,
  363. + .irq_disable = pci_msi_mask_irq,
  364. + .irq_mask = pci_msi_mask_irq,
  365. + .irq_unmask = pci_msi_unmask_irq,
  366. +};
  367. +
  368. +/**
  369. + * microsemi_pcie_msi_map - Set the handler for the MSI and mark IRQ as valid
  370. + * @domain: IRQ domain
  371. + * @irq: Virtual IRQ number
  372. + * @hwirq: HW interrupt number
  373. + *
  374. + * Return: Always returns 0.
  375. + */
  376. +static int microsemi_pcie_msi_map(struct irq_domain *domain, unsigned int irq,
  377. + irq_hw_number_t hwirq)
  378. +{
  379. + irq_set_chip_and_handler(irq, &microsemi_msi_irq_chip,
  380. + handle_simple_irq);
  381. + irq_set_chip_data(irq, domain->host_data);
  382. +
  383. + return 0;
  384. +}
  385. +
  386. +/* IRQ Domain operations */
  387. +static const struct irq_domain_ops msi_domain_ops = {
  388. + .map = microsemi_pcie_msi_map,
  389. +};
  390. +
  391. +/**
  392. + * microsemi_pcie_enable_msi - Enable MSI support
  393. + * @port: PCIe port information
  394. + */
  395. +static void microsemi_pcie_enable_msi(struct microsemi_pcie_port *port)
  396. +{
  397. + u32 cap_ctrl;
  398. +
  399. + cap_ctrl = pcie_read(port, MSI_CAP_CTRL_OFFSET);
  400. +
  401. + pcie_write(port, cap_ctrl | MSI_ENABLE_MULTI |
  402. + MSI_ENABLE, MSI_CAP_CTRL_OFFSET);
  403. + pcie_write(port, MICROSEMI_MSI_MSG_ADDR, MSI_MSG_ADDR_OFFSET);
  404. +}
  405. +
  406. +/* INTx Functions */
  407. +
  408. +/**
  409. + * microsemi_pcie_intx_map - Set the handler for the INTx and mark IRQ as valid
  410. + * @domain: IRQ domain
  411. + * @irq: Virtual IRQ number
  412. + * @hwirq: HW interrupt number
  413. + *
  414. + * Return: Always returns 0.
  415. + */
  416. +static int microsemi_pcie_intx_map(struct irq_domain *domain, unsigned int irq,
  417. + irq_hw_number_t hwirq)
  418. +{
  419. + irq_set_chip_and_handler(irq, &dummy_irq_chip, handle_simple_irq);
  420. + irq_set_chip_data(irq, domain->host_data);
  421. +
  422. + return 0;
  423. +}
  424. +
  425. +/* INTx IRQ Domain operations */
  426. +static const struct irq_domain_ops intx_domain_ops = {
  427. + .map = microsemi_pcie_intx_map,
  428. + .xlate = pci_irqd_intx_xlate,
  429. +};
  430. +
  431. +/* PCIe HW Functions */
  432. +
  433. +/**
  434. + * microsemi_pcie_intr_handler - Interrupt Service Handler
  435. + * @irq: IRQ number
  436. + * @data: PCIe port information
  437. + *
  438. + * Return: IRQ_HANDLED on success and IRQ_NONE on failure
  439. + */
  440. +static irqreturn_t microsemi_pcie_intr_handler(int irq, void *data)
  441. +{
  442. + struct microsemi_pcie_port *port = (struct microsemi_pcie_port *)data;
  443. + struct device *dev = port->dev;
  444. + unsigned long status;
  445. + unsigned long msi;
  446. + u32 bit;
  447. + u32 virq;
  448. +
  449. + status = readl(port->bridge_base_addr + MICROSEMI_ISTATUS_LOCAL);
  450. +
  451. + /* Might be sharing interrupt line. Check if interrupt is for us */
  452. + if (!status)
  453. + return IRQ_NONE;
  454. +
  455. + status = (status & MICROSEMI_PCI_INTS) >> MICROSEMI_PM_MSI_INT_SHIFT;
  456. + for_each_set_bit(bit, &status, PCI_NUM_INTX) {
  457. + /* clear that interrupt bit */
  458. + writel(1 << (bit + MICROSEMI_PM_MSI_INT_SHIFT),
  459. + port->bridge_base_addr + MICROSEMI_ISTATUS_LOCAL);
  460. + virq = irq_find_mapping(port->leg_domain, bit);
  461. +
  462. + if (virq)
  463. + generic_handle_irq(virq);
  464. + else
  465. + dev_err(dev, "unexpected IRQ, INT%d\n", bit);
  466. + }
  467. +
  468. + status = readl(port->bridge_base_addr + MICROSEMI_ISTATUS_LOCAL);
  469. + if (status & MICROSEMI_MSI_INT) {
  470. + /* Clear the ISTATUS MSI bit */
  471. + writel((1 << MICROSEMI_MSI_INT_SHIFT),
  472. + port->bridge_base_addr + MICROSEMI_ISTATUS_LOCAL);
  473. + msi = readl(port->bridge_base_addr + MICROSEMI_ISTATUS_MSI);
  474. + for_each_set_bit(bit, &msi, MICROSEMI_NUM_MSI_IRQS) {
  475. + /* clear that MSI interrupt bit */
  476. + writel((1 << bit),
  477. + port->bridge_base_addr + MICROSEMI_ISTATUS_MSI);
  478. + virq = irq_find_mapping(port->msi_domain, bit);
  479. + if (virq)
  480. + generic_handle_irq(virq);
  481. + else
  482. + dev_err(dev, "unexpected IRQ, INT%d\n", bit);
  483. + }
  484. + }
  485. +
  486. + return IRQ_HANDLED;
  487. +}
  488. +
  489. +/**
  490. + * microsemi_pcie_init_irq_domain - Initialize IRQ domain
  491. + * @port: PCIe port information
  492. + *
  493. + * Return: '0' on success and error value on failure
  494. + */
  495. +static int microsemi_pcie_init_irq_domain(struct microsemi_pcie_port *port)
  496. +{
  497. + struct device *dev = port->dev;
  498. + struct device_node *node = dev->of_node;
  499. + struct device_node *pcie_intc_node;
  500. +
  501. + /* Setup INTx */
  502. + pcie_intc_node = of_get_next_child(node, NULL);
  503. + if (!pcie_intc_node) {
  504. + dev_err(dev, "no PCIe INTx node found\n");
  505. + return -ENODEV;
  506. + }
  507. +
  508. + port->leg_domain = irq_domain_add_linear(pcie_intc_node, PCI_NUM_INTX,
  509. + &intx_domain_ops,
  510. + port);
  511. + if (!port->leg_domain) {
  512. + dev_err(dev, "failed to get a INTx IRQ domain\n");
  513. + return -ENODEV;
  514. + }
  515. +
  516. + /* Setup MSI */
  517. + if (IS_ENABLED(CONFIG_PCI_MSI)) {
  518. + port->msi_domain =
  519. + irq_domain_add_linear(node,
  520. + MICROSEMI_NUM_MSI_IRQS,
  521. + &msi_domain_ops,
  522. + &microsemi_pcie_msi_chip);
  523. + if (!port->msi_domain) {
  524. + dev_err(dev, "failed to get an MSI IRQ domain\n");
  525. + return -ENODEV;
  526. + }
  527. + microsemi_pcie_enable_msi(port);
  528. + }
  529. +
  530. + /* Enable interrupts */
  531. + writel(MICROSEMI_PCIE_ENABLE_MSI | MICROSEMI_PCIE_LOCAL_INT_ENABLE,
  532. + port->bridge_base_addr + MICROSEMI_IMASK_LOCAL);
  533. +
  534. + return 0;
  535. +}
  536. +
  537. +/**
  538. + * microsemi_pcie_init_port - Parse Device tree, Initialize hardware
  539. + * @port: PCIe port information
  540. + *
  541. + * Return: '0' on success and error value on failure
  542. + */
  543. +static int microsemi_pcie_init_port(struct microsemi_pcie_port *port)
  544. +{
  545. + struct device *dev = port->dev;
  546. + struct device_node *node = dev->of_node;
  547. + struct of_pci_range_parser parser;
  548. + struct of_pci_range range;
  549. + struct resource regs;
  550. + struct resource regs1;
  551. + resource_size_t size;
  552. + u32 atr_sz;
  553. + const char *type;
  554. + int err;
  555. + u32 val;
  556. + int index = 1;
  557. +
  558. + type = of_get_property(node, "device_type", NULL);
  559. + if (!type || strcmp(type, "pci")) {
  560. + dev_err(dev, "invalid \"device_type\" %s\n", type);
  561. + return -EINVAL;
  562. + }
  563. +
  564. + /* Only supporting bridge 1 */
  565. + port->bridge = 1;
  566. +
  567. + mutex_init(&port->lock);
  568. +
  569. + err = of_address_to_resource(node, 0, &regs);
  570. + if (err) {
  571. + dev_err(dev, "missing \"reg\" property\n");
  572. + return err;
  573. + }
  574. +
  575. + port->pcie_base_addr = devm_pci_remap_cfg_resource(dev, &regs);
  576. + if (IS_ERR(port->pcie_base_addr))
  577. + return PTR_ERR(port->pcie_base_addr);
  578. +
  579. + err = of_address_to_resource(node, 1, &regs1);
  580. + if (err) {
  581. + dev_err(dev, "missing \"reg\" property\n");
  582. + return err;
  583. + }
  584. +
  585. + port->axi_base_addr = devm_ioremap_resource(dev, &regs1);
  586. + if (IS_ERR(port->axi_base_addr))
  587. + return PTR_ERR(port->axi_base_addr);
  588. +
  589. + if (port->bridge == 0) {
  590. + port->bridge_base_addr = port->axi_base_addr
  591. + + MICROSEMI_PCIE0_BRIDGE_ADDR;
  592. + port->ctrl_base_addr = port->axi_base_addr
  593. + + MICROSEMI_PCIE0_CTRL_ADDR;
  594. + } else {
  595. + port->bridge_base_addr = port->axi_base_addr
  596. + + MICROSEMI_PCIE1_BRIDGE_ADDR;
  597. + port->ctrl_base_addr = port->axi_base_addr
  598. + + MICROSEMI_PCIE1_CTRL_ADDR;
  599. + }
  600. +
  601. + port->irq = irq_of_parse_and_map(node, 0);
  602. +
  603. + err = devm_request_irq(dev, port->irq, microsemi_pcie_intr_handler,
  604. + IRQF_SHARED | IRQF_NO_THREAD,
  605. + "microsemi-pcie", port);
  606. + if (err) {
  607. + dev_err(dev, "unable to request IRQ%d\n", port->irq);
  608. + return err;
  609. + }
  610. +
  611. + microsemi_pcie_enable(port);
  612. +
  613. + /* Clear and Disable interrupts */
  614. + val = ECC_CONTROL_AXI2PCIE_RAM_ECC_BYPASS
  615. + | ECC_CONTROL_PCIE2AXI_RAM_ECC_BYPASS
  616. + | ECC_CONTROL_RX_RAM_ECC_BYPASS
  617. + | ECC_CONTROL_TX_RAM_ECC_BYPASS;
  618. + writel(val, port->ctrl_base_addr + MICROSEMI_ECC_CONTROL);
  619. +
  620. + val = PCIE_EVENT_INT_L2_EXIT_INT
  621. + | PCIE_EVENT_INT_HOTRST_EXIT_INT
  622. + | PCIE_EVENT_INT_DLUP_EXIT_INT
  623. + | PCIE_EVENT_INT_L2_EXIT_INT_MASK
  624. + | PCIE_EVENT_INT_HOTRST_EXIT_INT_MASK
  625. + | PCIE_EVENT_INT_DLUP_EXIT_INT_MASK;
  626. + writel(val, port->ctrl_base_addr + MICROSEMI_PCIE_EVENT_INT);
  627. +
  628. + val = SEC_ERROR_INT_TX_RAM_SEC_ERR_INT
  629. + | SEC_ERROR_INT_RX_RAM_SEC_ERR_INT
  630. + | SEC_ERROR_INT_PCIE2AXI_RAM_SEC_ERR_INT
  631. + | SEC_ERROR_INT_AXI2PCIE_RAM_SEC_ERR_INT;
  632. + writel(val, port->ctrl_base_addr + MICROSEMI_SEC_ERROR_INT);
  633. + writel(val, port->ctrl_base_addr + MICROSEMI_SEC_ERROR_INT_MASK);
  634. +
  635. + val = DED_ERROR_INT_TX_RAM_DED_ERR_INT
  636. + | DED_ERROR_INT_RX_RAM_DED_ERR_INT
  637. + | DED_ERROR_INT_PCIE2AXI_RAM_DED_ERR_INT
  638. + | DED_ERROR_INT_AXI2PCIE_RAM_DED_ERR_INT;
  639. + writel(val, port->ctrl_base_addr + MICROSEMI_DED_ERROR_INT);
  640. + writel(val, port->ctrl_base_addr + MICROSEMI_DED_ERROR_INT_MASK);
  641. +
  642. + writel(0x00000000, port->bridge_base_addr + MICROSEMI_IMASK_LOCAL);
  643. + writel(GENMASK(31, 0),
  644. + port->bridge_base_addr + MICROSEMI_ISTATUS_LOCAL);
  645. + writel(0x00000000, port->bridge_base_addr + MICROSEMI_IMASK_HOST);
  646. + writel(GENMASK(31, 0), port->bridge_base_addr + MICROSEMI_ISTATUS_HOST);
  647. +
  648. + /* Configure Address Translation Table 0 for PCIe config space */
  649. + writel(MICROSEMI_PCIE_CONFIG_INTERFACE,
  650. + port->bridge_base_addr + MICROSEMI_ATR0_AXI4_SLV0_TRSL_PARAM);
  651. +
  652. + size = resource_size(&regs);
  653. +
  654. + atr_sz = find_first_bit((const unsigned long *)&size, 64) - 1;
  655. +
  656. + writel(lower_32_bits(regs.start)
  657. + | atr_sz << ATR_SIZE_SHIFT | ATR_IMPL_ENABLE,
  658. + port->bridge_base_addr
  659. + + MICROSEMI_ATR0_AXI4_SLV0_SRCADDR_PARAM);
  660. +
  661. + writel(lower_32_bits(regs.start),
  662. + port->bridge_base_addr + MICROSEMI_ATR0_AXI4_SLV0_TRSL_ADDR_LSB);
  663. +
  664. + if (of_pci_range_parser_init(&parser, node)) {
  665. + dev_err(dev, "missing \"ranges\" property\n");
  666. + return -EINVAL;
  667. + }
  668. +
  669. + for_each_of_pci_range(&parser, &range) {
  670. + switch (range.flags & IORESOURCE_TYPE_BITS) {
  671. + case IORESOURCE_MEM:
  672. + size = range.size;
  673. + atr_sz =
  674. + find_first_bit((const unsigned long *)&size, 64)
  675. + - 1;
  676. +
  677. + /* Configure Address Translation Table index for PCIe
  678. + * mem space
  679. + */
  680. + writel(MICROSEMI_PCIE_TX_RX_INTERFACE,
  681. + port->bridge_base_addr
  682. + + (index * MICROSEMI_ATR0_AXI4_SLV_SIZE)
  683. + + MICROSEMI_ATR0_AXI4_SLV0_TRSL_PARAM);
  684. +
  685. + writel(lower_32_bits(range.cpu_addr)
  686. + | (atr_sz << ATR_SIZE_SHIFT)
  687. + | ATR_IMPL_ENABLE,
  688. + port->bridge_base_addr
  689. + + (index * MICROSEMI_ATR0_AXI4_SLV_SIZE)
  690. + + MICROSEMI_ATR0_AXI4_SLV0_SRCADDR_PARAM);
  691. +
  692. + writel(lower_32_bits(range.pci_addr),
  693. + port->bridge_base_addr
  694. + + (index * MICROSEMI_ATR0_AXI4_SLV_SIZE)
  695. + + MICROSEMI_ATR0_AXI4_SLV0_TRSL_ADDR_LSB);
  696. +
  697. + break;
  698. + }
  699. + index++;
  700. + }
  701. +
  702. + writel(readl(port->bridge_base_addr
  703. + + MICROSEMI_ATR0_PCIE_WIN0_SRCADDR_31_12)
  704. + | (MICROSEMI_ATR0_PCIE_WIN0_SIZE
  705. + << MICROSEMI_ATR0_PCIE_WIN0_SIZE_SHIFT),
  706. + port->bridge_base_addr +
  707. + MICROSEMI_ATR0_PCIE_WIN0_SRCADDR_31_12);
  708. +
  709. + writel(0x0,
  710. + port->bridge_base_addr + MICROSEMI_ATR0_PCIE_WIN0_SRCADDR_63_32);
  711. +
  712. + writel((readl(port->bridge_base_addr + MICROSEMI_PCIE_PCI_IDS_DW1)
  713. + & 0xffff)
  714. + | (PCI_CLASS_BRIDGE_PCI << 16),
  715. + port->bridge_base_addr + MICROSEMI_PCIE_PCI_IDS_DW1);
  716. +
  717. + return 0;
  718. +}
  719. +
  720. +/**
  721. + * microsemi_pcie_probe - Probe function
  722. + * @pdev: Platform device pointer
  723. + *
  724. + * Return: '0' on success and error value on failure
  725. + */
  726. +static int microsemi_pcie_probe(struct platform_device *pdev)
  727. +{
  728. + struct device *dev = &pdev->dev;
  729. + struct microsemi_pcie_port *port;
  730. + struct pci_bus *bus, *child;
  731. + struct pci_host_bridge *bridge;
  732. + int err;
  733. + resource_size_t iobase = 0;
  734. + LIST_HEAD(res);
  735. +
  736. + if (!dev->of_node)
  737. + return -ENODEV;
  738. +
  739. + bridge = devm_pci_alloc_host_bridge(dev, sizeof(*port));
  740. + if (!bridge)
  741. + return -ENODEV;
  742. +
  743. + port = pci_host_bridge_priv(bridge);
  744. +
  745. + port->dev = dev;
  746. + port->pdev = pdev;
  747. +
  748. + err = microsemi_pcie_init_port(port);
  749. + if (err) {
  750. + dev_err(dev, "PCIe port initialization failed\n");
  751. + return err;
  752. + }
  753. +
  754. + err = microsemi_pcie_init_irq_domain(port);
  755. + if (err) {
  756. + dev_err(dev, "failed creating IRQ domain\n");
  757. + return err;
  758. + }
  759. +
  760. + err = devm_of_pci_get_host_bridge_resources(dev, 0, 0xff, &res,
  761. + &iobase);
  762. + if (err) {
  763. + dev_err(dev, "getting bridge resources failed\n");
  764. + return err;
  765. + }
  766. +
  767. + err = devm_request_pci_bus_resources(dev, &res);
  768. + if (err)
  769. + goto error;
  770. +
  771. + list_splice_init(&res, &bridge->windows);
  772. + bridge->dev.parent = dev;
  773. + bridge->sysdata = port;
  774. + bridge->busnr = 0;
  775. + bridge->ops = &microsemi_pcie_ops;
  776. + bridge->map_irq = of_irq_parse_and_map_pci;
  777. + bridge->swizzle_irq = pci_common_swizzle;
  778. +
  779. +#ifdef CONFIG_PCI_MSI
  780. + microsemi_pcie_msi_chip.dev = dev;
  781. + bridge->msi = &microsemi_pcie_msi_chip;
  782. +#endif
  783. + err = pci_scan_root_bus_bridge(bridge);
  784. + if (err < 0)
  785. + goto error;
  786. +
  787. + bus = bridge->bus;
  788. +
  789. + pci_assign_unassigned_bus_resources(bus);
  790. + list_for_each_entry(child, &bus->children, node)
  791. + pcie_bus_configure_settings(child);
  792. + pci_bus_add_devices(bus);
  793. +
  794. + return 0;
  795. +
  796. +error:
  797. + pci_free_resource_list(&res);
  798. + return err;
  799. +}
  800. +
  801. +static const struct of_device_id microsemi_pcie_of_match[] = {
  802. + { .compatible = "microsemi,ms-pf-axi-pcie-host", },
  803. + {}
  804. +};
  805. +
  806. +static struct platform_driver microsemi_pcie_driver = {
  807. + .driver = {
  808. + .name = "microsemi-pcie",
  809. + .of_match_table = microsemi_pcie_of_match,
  810. + .suppress_bind_attrs = true,
  811. + },
  812. + .probe = microsemi_pcie_probe,
  813. +};
  814. +builtin_platform_driver(microsemi_pcie_driver);
  815. --
  816. 2.22.0