light-evb.dtsi 50 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * Copyright (C) 2021 Alibaba Group Holding Limited.
  4. */
  5. #include <dt-bindings/pinctrl/light-fm-left-pinctrl.h>
  6. #include <dt-bindings/pinctrl/light-fm-right-pinctrl.h>
  7. #include <dt-bindings/pinctrl/light-fm-aon-pinctrl.h>
  8. #include <dt-bindings/clock/light-fm-ap-clock.h>
  9. #include <dt-bindings/soc/thead,light-iopmp.h>
  10. / {
  11. compatible = "thead,light";
  12. #address-cells = <2>;
  13. #size-cells = <2>;
  14. aliases {
  15. ethernet0 = &gmac0;
  16. ethernet1 = &gmac1;
  17. gpio0 = &gpio0;
  18. gpio1 = &gpio1;
  19. gpio2 = &gpio2;
  20. gpio3 = &gpio3;
  21. i2c0 = &i2c0;
  22. i2c2 = &i2c2;
  23. i2c3 = &i2c3;
  24. i2c4 = &i2c4;
  25. mmc0 = &emmc;
  26. mmc1 = &sdhci0;
  27. serial0 = &uart0;
  28. serial1 = &uart1;
  29. serial2 = &uart2;
  30. serial3 = &uart3;
  31. serial4 = &uart4;
  32. serial5 = &uart5;
  33. spi0 = &spi0;
  34. spi1 = &qspi0;
  35. spi2 = &qspi1;
  36. vivcam0 = &vvcam_sensor0;
  37. vivcam1 = &vvcam_sensor1;
  38. vivcam2= &vvcam_sensor2;
  39. vivcam3= &vvcam_sensor3;
  40. vivcam4= &vvcam_sensor4;
  41. vivcam5= &vvcam_sensor5;
  42. vivcam6= &vvcam_sensor6;
  43. };
  44. memory@0 {
  45. device_type = "memory";
  46. reg = <0x0 0x00000000 0x1 0x00000000>;
  47. };
  48. resmem: reserved-memory {
  49. #address-cells = <2>;
  50. #size-cells = <2>;
  51. ranges;
  52. /* global autoconfigured region for contiguous allocations */
  53. linux,cma {
  54. compatible = "shared-dma-pool";
  55. reusable;
  56. size = <0 0x14000000>;
  57. alloc-ranges = <0 0x20000000 0 0x40000000>;
  58. linux,cma-default;
  59. };
  60. };
  61. cpus: cpus {
  62. #address-cells = <1>;
  63. #size-cells = <0>;
  64. timebase-frequency = <3000000>;
  65. c910_0: cpu@0 {
  66. device_type = "cpu";
  67. reg = <0>;
  68. status = "okay";
  69. compatible = "riscv";
  70. riscv,isa = "rv64imafdcvsu";
  71. mmu-type = "riscv,sv39";
  72. cpu-freq = "1.848Ghz";
  73. cpu-icache = "64KB";
  74. cpu-dcache = "64KB";
  75. cpu-l2cache = "1MB";
  76. cpu-tlb = "1024 4-ways";
  77. cpu-cacheline = "64Bytes";
  78. cpu-vector = "0.7.1";
  79. operating-points = <
  80. /* kHz uV */
  81. 300000 600000
  82. 800000 700000
  83. 1500000 800000
  84. 1848000 1000000
  85. >;
  86. light,dvddm-operating-points = <
  87. /* kHz uV */
  88. 300000 750000
  89. 800000 800000
  90. 1500000 800000
  91. 1848000 1000000
  92. >;
  93. clock-latency = <61036>;
  94. clocks = <&clk C910_CCLK>,
  95. <&clk C910_CCLK_I0>,
  96. <&clk CPU_PLL1_FOUTPOSTDIV>,
  97. <&clk CPU_PLL0_FOUTPOSTDIV>;
  98. clock-names = "c910_cclk", "c910_cclk_i0",
  99. "cpu_pll1_foutpostdiv", "cpu_pll0_foutpostdiv";
  100. dvdd-supply = <&dvdd_cpu_reg>;
  101. dvddm-supply = <&dvddm_cpu_reg>;
  102. cpu0_intc: interrupt-controller {
  103. #interrupt-cells = <1>;
  104. compatible = "riscv,cpu-intc";
  105. interrupt-controller;
  106. };
  107. };
  108. c910_1: cpu@1 {
  109. device_type = "cpu";
  110. reg = <1>;
  111. status = "okay";
  112. compatible = "riscv";
  113. riscv,isa = "rv64imafdcvsu";
  114. mmu-type = "riscv,sv39";
  115. cpu-freq = "1.848Ghz";
  116. cpu-icache = "64KB";
  117. cpu-dcache = "64KB";
  118. cpu-l2cache = "1MB";
  119. cpu-tlb = "1024 4-ways";
  120. cpu-cacheline = "64Bytes";
  121. cpu-vector = "0.7.1";
  122. operating-points = <
  123. /* kHz uV */
  124. 300000 600000
  125. 800000 700000
  126. 1500000 800000
  127. 1848000 1000000
  128. >;
  129. light,dvddm-operating-points = <
  130. /* kHz uV */
  131. 300000 750000
  132. 800000 800000
  133. 1500000 800000
  134. 1848000 1000000
  135. >;
  136. clock-latency = <61036>;
  137. clocks = <&clk C910_CCLK>,
  138. <&clk C910_CCLK_I0>,
  139. <&clk CPU_PLL1_FOUTPOSTDIV>,
  140. <&clk CPU_PLL0_FOUTPOSTDIV>;
  141. clock-names = "c910_cclk", "c910_cclk_i0",
  142. "cpu_pll1_foutpostdiv", "cpu_pll0_foutpostdiv";
  143. dvdd-supply = <&dvdd_cpu_reg>;
  144. dvddm-supply = <&dvddm_cpu_reg>;
  145. cpu1_intc: interrupt-controller {
  146. #interrupt-cells = <1>;
  147. compatible = "riscv,cpu-intc";
  148. interrupt-controller;
  149. };
  150. };
  151. c910_2: cpu@2 {
  152. device_type = "cpu";
  153. reg = <2>;
  154. status = "okay";
  155. compatible = "riscv";
  156. riscv,isa = "rv64imafdcvsu";
  157. mmu-type = "riscv,sv39";
  158. cpu-freq = "1.848Ghz";
  159. cpu-icache = "64KB";
  160. cpu-dcache = "64KB";
  161. cpu-l2cache = "1MB";
  162. cpu-tlb = "1024 4-ways";
  163. cpu-cacheline = "64Bytes";
  164. cpu-vector = "0.7.1";
  165. operating-points = <
  166. /* kHz uV */
  167. 300000 600000
  168. 800000 700000
  169. 1500000 800000
  170. 1848000 1000000
  171. >;
  172. light,dvddm-operating-points = <
  173. /* kHz uV */
  174. 300000 750000
  175. 800000 800000
  176. 1500000 800000
  177. 1848000 1000000
  178. >;
  179. clock-latency = <61036>;
  180. clocks = <&clk C910_CCLK>,
  181. <&clk C910_CCLK_I0>,
  182. <&clk CPU_PLL1_FOUTPOSTDIV>,
  183. <&clk CPU_PLL0_FOUTPOSTDIV>;
  184. clock-names = "c910_cclk", "c910_cclk_i0",
  185. "cpu_pll1_foutpostdiv", "cpu_pll0_foutpostdiv";
  186. dvdd-supply = <&dvdd_cpu_reg>;
  187. dvddm-supply = <&dvddm_cpu_reg>;
  188. cpu2_intc: interrupt-controller {
  189. #interrupt-cells = <1>;
  190. compatible = "riscv,cpu-intc";
  191. interrupt-controller;
  192. };
  193. };
  194. c910_3: cpu@3 {
  195. device_type = "cpu";
  196. reg = <3>;
  197. status = "okay";
  198. compatible = "riscv";
  199. riscv,isa = "rv64imafdcvsu";
  200. mmu-type = "riscv,sv39";
  201. cpu-freq = "1.848Ghz";
  202. cpu-icache = "64KB";
  203. cpu-dcache = "64KB";
  204. cpu-l2cache = "1MB";
  205. cpu-tlb = "1024 4-ways";
  206. cpu-cacheline = "64Bytes";
  207. cpu-vector = "0.7.1";
  208. operating-points = <
  209. /* kHz uV */
  210. 300000 600000
  211. 800000 700000
  212. 1500000 800000
  213. 1848000 1000000
  214. >;
  215. light,dvddm-operating-points = <
  216. /* kHz uV */
  217. 300000 750000
  218. 800000 800000
  219. 1500000 800000
  220. 1848000 1000000
  221. >;
  222. clock-latency = <61036>;
  223. clocks = <&clk C910_CCLK>,
  224. <&clk C910_CCLK_I0>,
  225. <&clk CPU_PLL1_FOUTPOSTDIV>,
  226. <&clk CPU_PLL0_FOUTPOSTDIV>;
  227. clock-names = "c910_cclk", "c910_cclk_i0",
  228. "cpu_pll1_foutpostdiv", "cpu_pll0_foutpostdiv";
  229. dvdd-supply = <&dvdd_cpu_reg>;
  230. dvddm-supply = <&dvddm_cpu_reg>;
  231. cpu3_intc: interrupt-controller {
  232. #interrupt-cells = <1>;
  233. compatible = "riscv,cpu-intc";
  234. interrupt-controller;
  235. };
  236. };
  237. };
  238. display-subsystem {
  239. compatible = "verisilicon,display-subsystem";
  240. ports = <&dpu_disp0>, <&dpu_disp1>;
  241. status = "disabled";
  242. };
  243. dpu-encoders {
  244. compatible = "simple-bus";
  245. #address-cells = <1>;
  246. #size-cells = <0>;
  247. dpu_enc0: dpu-encoder@0 {
  248. /* default encoder is DSI */
  249. compatible = "verisilicon,dsi-encoder";
  250. reg = <0>;
  251. status = "disabled";
  252. ports {
  253. #address-cells = <1>;
  254. #size-cells = <0>;
  255. /* input */
  256. port@0 {
  257. reg = <0>;
  258. enc0_in: endpoint {
  259. remote-endpoint = <&disp0_out>;
  260. };
  261. };
  262. };
  263. };
  264. dpu_enc1: dpu-encoder@1 {
  265. /* default encoder is DSI */
  266. compatible = "verisilicon,dsi-encoder";
  267. reg = <1>;
  268. status = "disabled";
  269. ports {
  270. #address-cells = <1>;
  271. #size-cells = <0>;
  272. /* input */
  273. port@0 {
  274. reg = <0>;
  275. enc1_in: endpoint {
  276. remote-endpoint = <&disp1_out>;
  277. };
  278. };
  279. };
  280. };
  281. };
  282. soc {
  283. compatible = "simple-bus";
  284. #address-cells = <2>;
  285. #size-cells = <2>;
  286. ranges;
  287. reset: reset-sample {
  288. compatible = "thead,reset-sample";
  289. plic-delegate = <0xff 0xd81ffffc>;
  290. entry-reg = <0xff 0xff019050>;
  291. entry-cnt = <4>;
  292. control-reg = <0xff 0xff015004>;
  293. control-val = <0x1c>;
  294. csr-copy = <0x7f3 0x7c0 0x7c1 0x7c2 0x7c3 0x7c5 0x7cc>;
  295. };
  296. clint0: clint@ffdc000000 {
  297. compatible = "riscv,clint0";
  298. interrupts-extended = <
  299. &cpu0_intc 3 &cpu0_intc 7
  300. &cpu1_intc 3 &cpu1_intc 7
  301. &cpu2_intc 3 &cpu2_intc 7
  302. &cpu3_intc 3 &cpu3_intc 7
  303. >;
  304. reg = <0xff 0xdc000000 0x0 0x04000000>;
  305. clint,has-no-64bit-mmio;
  306. };
  307. intc: interrupt-controller@ffd8000000 {
  308. #interrupt-cells = <1>;
  309. compatible = "riscv,plic0";
  310. interrupt-controller;
  311. interrupts-extended = <
  312. &cpu0_intc 0xffffffff &cpu0_intc 9
  313. &cpu1_intc 0xffffffff &cpu1_intc 9
  314. &cpu2_intc 0xffffffff &cpu2_intc 9
  315. &cpu3_intc 0xffffffff &cpu3_intc 9
  316. >;
  317. reg = <0xff 0xd8000000 0x0 0x04000000>;
  318. reg-names = "control";
  319. riscv,max-priority = <7>;
  320. riscv,ndev = <240>;
  321. };
  322. clocks {
  323. compatible = "simple-bus";
  324. #address-cells = <1>;
  325. #size-cells = <0>;
  326. dummy_clock_apb: apb-clock@0 {
  327. compatible = "fixed-clock";
  328. reg = <0>; /* Not address, just for index */
  329. clock-frequency = <62500000>;
  330. clock-output-names = "dummy_clock_apb";
  331. #clock-cells = <0>;
  332. };
  333. dummy_clock_ref: ref-clock@1 {
  334. compatible = "fixed-clock";
  335. reg = <1>; /* Not address, just for index */
  336. clock-frequency = <50000000>;
  337. clock-output-names = "dummy_clock_ref";
  338. #clock-cells = <0>;
  339. };
  340. dummy_clock_suspend: suspend-clock@2 {
  341. compatible = "fixed-clock";
  342. reg = <2>; /* Not address, just for index */
  343. clock-frequency = <50000000>;
  344. clock-output-names = "dummy_clock_suspend";
  345. #clock-cells = <0>;
  346. };
  347. dummy_clock_rtc: rtc-clock@3 {
  348. compatible = "fixed-clock";
  349. reg = <3>; /* Not address, just for index */
  350. clock-frequency = <32768>;
  351. clock-output-names = "dummy_clock_rtc";
  352. #clock-cells = <0>;
  353. };
  354. dummy_clock_ahb: ahb-clock@4 {
  355. compatible = "fixed-clock";
  356. reg = <4>; /* Not address, just for index */
  357. clock-frequency = <50000000>;
  358. clock-output-names = "dummy_clock_ahb";
  359. #clock-cells = <0>;
  360. };
  361. dummy_clock_npu: npu-clock@5 {
  362. compatible = "fixed-clock";
  363. reg = <5>; /* Not address, just for index */
  364. clock-frequency = <24000000>;
  365. clock-output-names = "dummy_clock_npu";
  366. #clock-cells = <0>;
  367. };
  368. dummy_clock_gpu: gpu-clock@6 {
  369. compatible = "fixed-clock";
  370. reg = <6>; /* Not address, just for index */
  371. clock-frequency = <18000000>;
  372. clock-output-names = "dummy_clock_gpu";
  373. #clock-cells = <0>;
  374. };
  375. dummy_clock_dphy_ref: dphy-ref-clock@7 {
  376. compatible = "fixed-clock";
  377. reg = <7>; /* Not address, just for index */
  378. clock-frequency = <24000000>;
  379. clock-output-names = "dummy_clock_dphy_ref";
  380. #clock-cells = <0>;
  381. };
  382. dummy_clock_dphy_cfg: dphy-cfg-clock@8 {
  383. compatible = "fixed-clock";
  384. reg = <8>; /* Not address, just for index */
  385. clock-frequency = <24000000>;
  386. clock-output-names = "dummy_clock_dphy_cfg";
  387. #clock-cells = <0>;
  388. };
  389. dummy_clock_dpu_pixel0: dpu-pixel-clock@9 {
  390. compatible = "fixed-clock";
  391. reg = <9>;
  392. clock-frequency = <72000000>;
  393. clock-output-names = "dummy_clock_dpu_pixel0";
  394. #clock-cells = <0>;
  395. };
  396. dummy_clock_dpu_pixel1: dpu-pixel-clock@10 {
  397. compatible = "fixed-clock";
  398. reg = <10>;
  399. clock-frequency = <74250000>;
  400. clock-output-names = "dummy_clock_dpu_pixel1";
  401. #clock-cells = <0>;
  402. };
  403. osc_32k: clock-osc-32k@11 {
  404. compatible = "fixed-clock";
  405. reg = <11>;
  406. #clock-cells = <0>;
  407. clock-frequency = <32768>;
  408. clock-output-names = "osc_32k";
  409. };
  410. osc_24m: clock-osc-24m@12 {
  411. compatible = "fixed-clock";
  412. reg = <12>;
  413. #clock-cells = <0>;
  414. clock-frequency = <24000000>;
  415. clock-output-names = "osc_24m";
  416. };
  417. rc_24m: clock-rc-24m@13 {
  418. compatible = "fixed-clock";
  419. reg = <13>;
  420. #clock-cells = <0>;
  421. clock-frequency = <24000000>;
  422. clock-output-names = "rc_24m";
  423. };
  424. dummy_clock_eip: eip-clock@14 {
  425. compatible = "fixed-clock";
  426. reg = <14>; /* Not address, just for index */
  427. clock-frequency = <400000000>;
  428. clock-output-names = "dummy_clock_eip";
  429. #clock-cells = <0>;
  430. };
  431. dummy_clock_spi: spi-clock@15 {
  432. compatible = "fixed-clock";
  433. reg = <15>; /* Not address, just for index */
  434. clock-frequency = <396000000>;
  435. clock-output-names = "dummy_clock_spi";
  436. #clock-cells = <0>;
  437. };
  438. dummy_clock_qspi: spi-clock@16 {
  439. compatible = "fixed-clock";
  440. reg = <15>; /* Not address, just for index */
  441. clock-frequency = <792000000>;
  442. clock-output-names = "dummy_clock_qspi";
  443. #clock-cells = <0>;
  444. };
  445. dummy_gmac_ahb: gmac-ahb-clock@16 {
  446. compatible = "fixed-clock";
  447. reg = <16>;
  448. clock-frequency = <250000000>;
  449. clock-output-names = "dummy_gmac_ahb";
  450. #clock-cells = <0>;
  451. };
  452. dummy_clock_gmac: gmac-clock@17 {
  453. compatible = "fixed-clock";
  454. reg = <17>;
  455. clock-frequency = <500000000>;
  456. clock-output-names = "dummy_clock_gmac";
  457. #clock-cells = <0>;
  458. };
  459. dummy_clock_sdhci: sdhci-clock@18 {
  460. compatible = "fixed-clock";
  461. reg = <18>; /* Not address, just for index */
  462. clock-frequency = <198000000>;
  463. clock-output-names = "dummy_clock_sdhci";
  464. #clock-cells = <0>;
  465. };
  466. dummy_clock_aonsys_clk: aonsys-clk-clock@19 {
  467. compatible = "fixed-clock";
  468. reg = <19>; /* Not address, just for index */
  469. clock-frequency = <73728000>;
  470. clock-output-names = "dummy_clock_aonsys_clk";
  471. #clock-cells = <0>;
  472. };
  473. dummy_clock_uart_sclk: uart-sclk-clock@20 {
  474. compatible = "fixed-clock";
  475. reg = <20>; /* Not address, just for index */
  476. clock-frequency = <100000000>;
  477. clock-output-names = "dummy_clock_uart_sclk";
  478. #clock-cells = <0>;
  479. };
  480. };
  481. iso7816: iso7816-card@fff7f30000 {
  482. compatible = "thead,light-iso7816-card";
  483. reg = <0xff 0xf7f30000 0x0 0x4000>;
  484. pinctrl-names = "default";
  485. pinctrl-0 = <&pinctrl_iso7816>;
  486. interrupts = <69>;
  487. interrupt-parent = <&intc>;
  488. status = "disabled";
  489. };
  490. teesys_syscon: teesys-reg@ffff200000 {
  491. compatible = "syscon";
  492. reg = <0xff 0xff200000 0x0 0x10000>;
  493. };
  494. nvmem_controller: efuse@ffff210000 {
  495. compatible = "thead,light-fm-efuse", "syscon";
  496. reg = <0xff 0xff210000 0x0 0x10000>;
  497. thead,teesys = <&teesys_syscon>;
  498. #address-cells = <1>;
  499. #size-cells = <1>;
  500. gmac0_mac_address: mac-address@176 {
  501. reg = <0xb0 6>;
  502. };
  503. gmac1_mac_address: mac-address@184 {
  504. reg = <0xb8 6>;
  505. };
  506. };
  507. gpio0: gpio@ffec005000 {
  508. compatible = "snps,dw-apb-gpio";
  509. reg = <0xff 0xec005000 0x0 0x1000>;
  510. #address-cells = <1>;
  511. #size-cells = <0>;
  512. gpio0_porta: gpio0-controller@0 {
  513. compatible = "snps,dw-apb-gpio-port";
  514. gpio-controller;
  515. #gpio-cells = <2>;
  516. nr-gpios-snps = <32>;
  517. reg = <0>;
  518. interrupt-controller;
  519. #interrupt-cells = <2>;
  520. interrupt-parent = <&intc>;
  521. interrupts = <56>;
  522. };
  523. };
  524. gpio1: gpio@ffec006000 {
  525. compatible = "snps,dw-apb-gpio";
  526. reg = <0xff 0xec006000 0x0 0x1000>;
  527. #address-cells = <1>;
  528. #size-cells = <0>;
  529. gpio1_porta: gpio1-controller@0 {
  530. compatible = "snps,dw-apb-gpio-port";
  531. gpio-controller;
  532. #gpio-cells = <2>;
  533. nr-gpios-snps = <32>;
  534. reg = <0>;
  535. interrupt-controller;
  536. #interrupt-cells = <2>;
  537. interrupt-parent = <&intc>;
  538. interrupts = <57>;
  539. };
  540. };
  541. gpio2: gpio@ffe7f34000 {
  542. compatible = "snps,dw-apb-gpio";
  543. reg = <0xff 0xe7f34000 0x0 0x1000>;
  544. #address-cells = <1>;
  545. #size-cells = <0>;
  546. gpio2_porta: gpio2-controller@0 {
  547. compatible = "snps,dw-apb-gpio-port";
  548. gpio-controller;
  549. #gpio-cells = <2>;
  550. nr-gpios-snps = <32>;
  551. reg = <0>;
  552. interrupt-controller;
  553. #interrupt-cells = <2>;
  554. interrupt-parent = <&intc>;
  555. interrupts = <58>;
  556. };
  557. };
  558. gpio3: gpio@ffe7f38000 {
  559. compatible = "snps,dw-apb-gpio";
  560. reg = <0xff 0xe7f38000 0x0 0x1000>;
  561. #address-cells = <1>;
  562. #size-cells = <0>;
  563. gpio3_porta: gpio3-controller@0 {
  564. compatible = "snps,dw-apb-gpio-port";
  565. gpio-controller;
  566. #gpio-cells = <2>;
  567. nr-gpios-snps = <32>;
  568. reg = <0>;
  569. interrupt-controller;
  570. #interrupt-cells = <2>;
  571. interrupt-parent = <&intc>;
  572. interrupts = <59>;
  573. };
  574. };
  575. ao_gpio4: gpio@fffff52000 {
  576. compatible = "snps,dw-apb-gpio";
  577. reg = <0xff 0xfff52000 0x0 0x1000>;
  578. #address-cells = <1>;
  579. #size-cells = <0>;
  580. ao_gpio4_porta: ao_gpio4-controller@0 {
  581. compatible = "snps,dw-apb-gpio-port";
  582. gpio-controller;
  583. #gpio-cells = <2>;
  584. nr-gpios-snps = <32>;
  585. reg = <0>;
  586. interrupt-controller;
  587. #interrupt-cells = <2>;
  588. interrupt-parent = <&intc>;
  589. interrupts = <55>;
  590. };
  591. };
  592. ao_gpio: gpio@fffff41000 {
  593. compatible = "snps,dw-apb-gpio";
  594. reg = <0xff 0xfff41000 0x0 0x1000>;
  595. #address-cells = <1>;
  596. #size-cells = <0>;
  597. ao_gpio_porta: ao_gpio-controller@0 {
  598. compatible = "snps,dw-apb-gpio-port";
  599. gpio-controller;
  600. #gpio-cells = <2>;
  601. nr-gpios-snps = <32>;
  602. reg = <0>;
  603. interrupt-controller;
  604. #interrupt-cells = <2>;
  605. interrupt-parent = <&intc>;
  606. interrupts = <76>;
  607. };
  608. };
  609. padctrl1_apsys: pinctrl1-apsys@ffe7f3c000 {
  610. compatible = "thead,light-fm-left-pinctrl";
  611. reg = <0xff 0xe7f3c000 0x0 0x1000>;
  612. status = "okay";
  613. };
  614. padctrl0_apsys: padctrl0-apsys@ffec007000 {
  615. compatible = "thead,light-fm-right-pinctrl";
  616. reg = <0xff 0xec007000 0x0 0x1000>;
  617. status = "okay";
  618. };
  619. pwm: pwm@ffec01c000 {
  620. compatible = "thead,pwm-light";
  621. reg = <0xff 0xec01c000 0x0 0x4000>;
  622. #pwm-cells = <2>;
  623. clocks = <&clk CLKGEN_PWM_PCLK>,
  624. <&clk CLKGEN_PWM_CCLK>;
  625. clock-names = "pclk", "cclk";
  626. pinctrl-names = "default";
  627. pinctrl-0 = <&pinctrl_pwm>;
  628. };
  629. timer0: timer@ffefc32000 {
  630. compatible = "snps,dw-apb-timer";
  631. reg = <0xff 0xefc32000 0x0 0x14>;
  632. clocks = <&dummy_clock_apb>;
  633. clock-names = "timer";
  634. clock-frequency = <62500000>;
  635. interrupts = <16>;
  636. interrupt-parent = <&intc>;
  637. status = "okay";
  638. };
  639. timer1: timer@ffefc32014 {
  640. compatible = "snps,dw-apb-timer";
  641. reg = <0xff 0xefc32014 0x0 0x14>;
  642. clocks = <&dummy_clock_apb>;
  643. clock-names = "timer";
  644. clock-frequency = <62500000>;
  645. interrupts = <17>;
  646. interrupt-parent = <&intc>;
  647. status = "okay";
  648. };
  649. timer2: timer@ffefc32028 {
  650. compatible = "snps,dw-apb-timer";
  651. reg = <0xff 0xefc32028 0x0 0x14>;
  652. clocks = <&dummy_clock_apb>;
  653. clock-names = "timer";
  654. clock-frequency = <62500000>;
  655. interrupts = <18>;
  656. interrupt-parent = <&intc>;
  657. status = "disabled";
  658. };
  659. timer3: timer@ffefc3203c {
  660. compatible = "snps,dw-apb-timer";
  661. reg = <0xff 0xefc3203c 0x0 0x14>;
  662. clocks = <&dummy_clock_apb>;
  663. clock-names = "timer";
  664. clock-frequency = <62500000>;
  665. interrupts = <19>;
  666. interrupt-parent = <&intc>;
  667. status = "disabled";
  668. };
  669. padctrl_aosys: padctrl-aosys@fffff4a000 {
  670. compatible = "thead,light-fm-aon-pinctrl";
  671. reg = <0xff 0xfff4a000 0x0 0x2000>;
  672. status = "okay";
  673. };
  674. timer4: timer@ffffc33000 {
  675. compatible = "snps,dw-apb-timer";
  676. reg = <0xff 0xffc33000 0x0 0x14>;
  677. clocks = <&dummy_clock_apb>;
  678. clock-names = "timer";
  679. clock-frequency = <62500000>;
  680. interrupts = <20>;
  681. interrupt-parent = <&intc>;
  682. status = "disabled";
  683. };
  684. timer5: timer@ffffc33014 {
  685. compatible = "snps,dw-apb-timer";
  686. reg = <0xff 0xffc33014 0x0 0x14>;
  687. clocks = <&dummy_clock_apb>;
  688. clock-names = "timer";
  689. clock-frequency = <62500000>;
  690. interrupts = <21>;
  691. interrupt-parent = <&intc>;
  692. status = "disabled";
  693. };
  694. timer6: timer@ffffc33028 {
  695. compatible = "snps,dw-apb-timer";
  696. reg = <0xff 0xffc33028 0x0 0x14>;
  697. clocks = <&dummy_clock_apb>;
  698. clock-names = "timer";
  699. clock-frequency = <62500000>;
  700. interrupts = <22>;
  701. interrupt-parent = <&intc>;
  702. status = "disabled";
  703. };
  704. timer7: timer@ffffc3303c {
  705. compatible = "snps,dw-apb-timer";
  706. reg = <0xff 0xffc3303c 0x0 0x14>;
  707. clocks = <&dummy_clock_apb>;
  708. clock-names = "timer";
  709. clock-frequency = <62500000>;
  710. interrupts = <23>;
  711. interrupt-parent = <&intc>;
  712. status = "disabled";
  713. };
  714. uart0: serial@ffe7014000 { /* Normal serial, for C910 log */
  715. compatible = "snps,dw-apb-uart";
  716. reg = <0xff 0xe7014000 0x0 0x4000>;
  717. interrupt-parent = <&intc>;
  718. interrupts = <36>;
  719. clocks = <&clk CLKGEN_UART0_SCLK>;
  720. clock-names = "baudclk";
  721. reg-shift = <2>;
  722. reg-io-width = <4>;
  723. hw-flow-control = "unsupport";
  724. status = "okay";
  725. };
  726. uart1: serial@ffe7f00000 { /* Normal serial, for C902 log */
  727. compatible = "snps,dw-apb-uart";
  728. reg = <0xff 0xe7f00000 0x0 0x4000>;
  729. interrupt-parent = <&intc>;
  730. interrupts = <37>;
  731. clocks = <&clk CLKGEN_UART1_SCLK>;
  732. clock-names = "baudclk";
  733. reg-shift = <2>;
  734. reg-io-width = <4>;
  735. hw-flow-control = "unsupport";
  736. status = "okay";
  737. };
  738. uart2: serial@ffec010000 { /* IRDA supported serial, not in 85P bit */
  739. compatible = "snps,dw-apb-uart";
  740. reg = <0xff 0xec010000 0x0 0x4000>;
  741. interrupt-parent = <&intc>;
  742. interrupts = <38>;
  743. clocks = <&clk CLKGEN_UART2_SCLK>;
  744. clock-names = "baudclk";
  745. reg-shift = <2>;
  746. reg-io-width = <4>;
  747. hw-flow-control = "unsupport";
  748. status = "disabled";
  749. };
  750. uart3: serial@ffe7f04000 { /* IRDA supported serial, not in 85P bit */
  751. compatible = "snps,dw-apb-uart";
  752. reg = <0xff 0xe7f04000 0x0 0x4000>;
  753. interrupt-parent = <&intc>;
  754. interrupts = <39>;
  755. clocks = <&clk CLKGEN_UART3_SCLK>;
  756. clock-names = "baudclk";
  757. reg-shift = <2>;
  758. reg-io-width = <4>;
  759. hw-flow-control = "unsupport";
  760. status = "disabled";
  761. };
  762. uart4: serial@fff7f08000 { /* High Speed with Flow Ctrol serial */
  763. compatible = "snps,dw-apb-uart";
  764. reg = <0xff 0xf7f08000 0x0 0x4000>;
  765. interrupt-parent = <&intc>;
  766. interrupts = <40>;
  767. clocks = <&clk CLKGEN_UART4_SCLK>;
  768. clock-names = "baudclk";
  769. reg-shift = <2>;
  770. reg-io-width = <4>;
  771. hw-flow-control = "support";
  772. status = "okay";
  773. };
  774. uart5: serial@fff7f0c000 { /* Normal serial, for external SE, not in 85P bit */
  775. compatible = "snps,dw-apb-uart";
  776. reg = <0xff 0xf7f0c000 0x0 0x4000>;
  777. interrupt-parent = <&intc>;
  778. interrupts = <41>;
  779. clocks = <&clk CLKGEN_UART5_SCLK>;
  780. clock-names = "baudclk";
  781. reg-shift = <2>;
  782. reg-io-width = <4>;
  783. hw-flow-control = "unsupport";
  784. status = "disabled";
  785. };
  786. adc: adc@ffec020000 {
  787. compatible = "thead,light-adc";
  788. reg = <0xff 0xfff51000 0x0 0x2000>;
  789. interrupt-parent = <&intc>;
  790. interrupts = <61>;
  791. clocks = <&dummy_clock_aonsys_clk>;
  792. clock-names = "adc";
  793. /* ADC pin is proprietary,no need to config pinctrl */
  794. status = "disabled";
  795. };
  796. spi0: spi@ffe700c000 {
  797. compatible = "snps,dw-apb-ssi";
  798. reg = <0xff 0xe700c000 0x0 0x1000>;
  799. pinctrl-names = "default";
  800. pinctrl-0 = <&pinctrl_spi0>;
  801. interrupt-parent = <&intc>;
  802. interrupts = <54>;
  803. clocks = <&dummy_clock_spi>;
  804. num-cs = <2>;
  805. #address-cells = <1>;
  806. #size-cells = <0>;
  807. };
  808. qspi0: spi@ffea000000 {
  809. compatible = "snps,dw-apb-ssi-quad";
  810. reg = <0xff 0xea000000 0x0 0x1000>;
  811. pinctrl-names = "default";
  812. pinctrl-0 = <&pinctrl_qspi0>;
  813. interrupt-parent = <&intc>;
  814. interrupts = <52>;
  815. clocks = <&dummy_clock_qspi>;
  816. #address-cells = <1>;
  817. #size-cells = <0>;
  818. };
  819. qspi1: spi@fff8000000 {
  820. compatible = "snps,dw-apb-ssi-quad";
  821. reg = <0xff 0xf8000000 0x0 0x1000>;
  822. pinctrl-names = "default";
  823. pinctrl-0 = <&pinctrl_qspi1>;
  824. interrupt-parent = <&intc>;
  825. interrupts = <53>;
  826. clocks = <&dummy_clock_spi>;
  827. #address-cells = <1>;
  828. #size-cells = <0>;
  829. };
  830. g2d: gc620@ffecc80000 {
  831. compatible = "thead,c910-gc620";
  832. reg = <0xff 0xecc80000 0x0 0x40000>;
  833. interrupt-parent = <&intc>;
  834. interrupts = <101>;
  835. interrupt-names = "irq_2d";
  836. status = "okay";
  837. };
  838. dsi0: dw-mipi-dsi@ffef500000 {
  839. compatible = "thead,light-mipi-dsi", "simple-bus", "syscon";
  840. reg = <0xff 0xef500000 0x0 0x10000>;
  841. status = "disabled";
  842. dphy_0: dsi0-dphy {
  843. compatible = "thead,light-mipi-dphy";
  844. regmap = <&dsi0>;
  845. vosys-regmap = <&vosys_reg>;
  846. clocks = <&dummy_clock_dphy_ref>,
  847. <&dummy_clock_dphy_cfg>,
  848. <&dummy_clock_apb>;
  849. clock-names = "refclk", "cfgclk", "pclk";
  850. #phy-cells = <0>;
  851. };
  852. dhost_0: dsi0-host {
  853. compatible = "verisilicon,dw-mipi-dsi";
  854. regmap = <&dsi0>;
  855. interrupt-parent = <&intc>;
  856. interrupts = <129>;
  857. clocks = <&dummy_clock_dphy_ref>, <&dummy_clock_apb>;
  858. clock-names = "ref", "pclk";
  859. phys = <&dphy_0>;
  860. phy-names = "dphy";
  861. #address-cells = <1>;
  862. #size-cells = <0>;
  863. };
  864. };
  865. dsi1: dw-mipi-dsi@ffef510000 {
  866. compatible = "thead,light-mipi-dsi", "simple-bus", "syscon";
  867. reg = <0xff 0xef510000 0x0 0x10000>;
  868. status = "disabled";
  869. dphy_1: dsi1-dphy {
  870. compatible = "thead,light-mipi-dphy";
  871. regmap = <&dsi1>;
  872. vosys-regmap = <&vosys_reg>;
  873. clocks = <&dummy_clock_dphy_ref>,
  874. <&dummy_clock_dphy_cfg>,
  875. <&dummy_clock_apb>;
  876. clock-names = "refclk", "cfgclk", "pclk";
  877. #phy-cells = <0>;
  878. };
  879. dhost_1: dsi1-host {
  880. compatible = "verisilicon,dw-mipi-dsi";
  881. regmap = <&dsi1>;
  882. interrupt-parent = <&intc>;
  883. interrupts = <129>;
  884. clocks = <&dummy_clock_dphy_ref>, <&dummy_clock_apb>;
  885. clock-names = "ref", "pclk";
  886. phys = <&dphy_1>;
  887. phy-names = "dphy";
  888. #address-cells = <1>;
  889. #size-cells = <0>;
  890. };
  891. };
  892. vosys_reg: vosys@ffef528000 {
  893. compatible = "thead,light-vo-subsys", "syscon";
  894. reg = <0xff 0xef528000 0x0 0x1000>;
  895. status = "okay";
  896. };
  897. hdmi_tx: dw-hdmi-tx@ffef540000 {
  898. compatible = "thead,light-hdmi-tx";
  899. reg = <0xff 0xef540000 0x0 0x40000>;
  900. interrupt-parent = <&intc>;
  901. interrupts = <111>;
  902. clocks = <&dummy_clock_apb>, <&dummy_clock_dphy_ref>;
  903. clock-names = "iahb", "isfr";
  904. reg-io-width = <4>;
  905. phy_version = <301>;
  906. /* TODO: add phy property */
  907. status = "disabled";
  908. };
  909. dpu: dc8200@ffef600000 {
  910. compatible = "verisilicon,dc8200";
  911. #address-cells = <1>;
  912. #size-cells = <0>;
  913. reg = <0xff 0xef600000 0x0 0x100>,
  914. <0xff 0xef600800 0x0 0x2000>,
  915. <0xff 0xef630010 0x0 0x60>;
  916. interrupt-parent = <&intc>;
  917. interrupts = <93>;
  918. clocks = <&dummy_clock_apb>,
  919. <&clk DPU0_PLL_DIV_CLK>,
  920. <&clk DPU1_PLL_DIV_CLK>,
  921. <&dummy_clock_ahb>;
  922. clock-names = "core_clk", "pix_clk0", "pix_clk1", "axi_clk";
  923. status = "disabled";
  924. dpu_disp0: port@0 {
  925. reg = <0>;
  926. disp0_out: endpoint {
  927. remote-endpoint = <&enc0_in>;
  928. };
  929. };
  930. dpu_disp1: port@1 {
  931. reg = <1>;
  932. disp1_out: endpoint {
  933. remote-endpoint = <&enc1_in>;
  934. };
  935. };
  936. };
  937. watchdog0: watchdog@ffefc30000 {
  938. compatible = "snps,dw-wdt";
  939. reg = <0xff 0xefc30000 0x0 0x1000>;
  940. interrupt-parent = <&intc>;
  941. interrupts = <24>;
  942. clocks = <&dummy_clock_apb>;
  943. clock-names = "baudclk";
  944. status = "okay";
  945. };
  946. watchdog1: watchdog@ffefc31000 {
  947. compatible = "snps,dw-wdt";
  948. reg = <0xff 0xefc31000 0x0 0x1000>;
  949. interrupt-parent = <&intc>;
  950. interrupts = <25>;
  951. clocks = <&dummy_clock_apb>;
  952. clock-names = "baudclk";
  953. status = "okay";
  954. };
  955. rtc: rtc@fffff40000 {
  956. compatible = "apm,xgene-rtc";
  957. reg = <0xff 0xfff40000 0x0 0x1000>;
  958. interrupt-parent = <&intc>;
  959. interrupts = <74>;
  960. clocks = <&dummy_clock_rtc>;
  961. clock-names = "rtc";
  962. status = "okay";
  963. };
  964. usb: dwc3@ffe7040000 {
  965. compatible = "snps,dwc3";
  966. reg = <0xff 0xe7040000 0x0 0x10000>;
  967. interrupt-parent = <&intc>;
  968. interrupts = <68>;
  969. clocks = <&dummy_clock_ref>, <&dummy_clock_apb>, <&dummy_clock_suspend>;
  970. clock-names = "ref", "bus_early", "suspend";
  971. reg-shift = <2>;
  972. reg-io-width = <4>;
  973. maximum-speed = "super-speed";
  974. dr_mode = "host";
  975. dma-mask = <0xf 0xffffffff>;
  976. snps,usb3_lpm_capable;
  977. snps,dis_u3_susphy_quirk;
  978. status = "okay";
  979. };
  980. pmu: pmu@0 {
  981. compatible = "riscv,c910_pmu";
  982. reg = <0 0 0 0>; /* Not address, just for index */
  983. };
  984. clk: clock-controller@ffef010000 {
  985. compatible = "thead,light-fm-ree-clk";
  986. reg = <0xff 0xef010000 0x0 0x1000>;
  987. #clock-cells = <1>;
  988. clocks = <&osc_32k>, <&osc_24m>, <&rc_24m>;
  989. clock-names = "osc_32k", "osc_24m", "rc_24m";
  990. status = "okay";
  991. };
  992. sys_reg: sys_reg@ffef010100 {
  993. compatible = "thead,light_sys_reg";
  994. reg = <0xff 0xef010100 0x0 0x100>;
  995. status = "okay";
  996. };
  997. dmac0: dmac@ffefc00000 {
  998. compatible = "snps,axi-dma-1.01a";
  999. reg = <0xff 0xefc00000 0x0 0x1000>;
  1000. interrupt-parent = <&intc>;
  1001. interrupts = <27>;
  1002. clocks = <&dummy_clock_apb>, <&dummy_clock_apb>;
  1003. clock-names = "core-clk", "cfgr-clk";
  1004. #dma-cells = <1>;
  1005. dma-channels = <4>;
  1006. snps,block-size = <65536 65536 65536 65536>;
  1007. snps,priority = <0 1 2 3>;
  1008. snps,dma-masters = <1>;
  1009. snps,data-width = <4>;
  1010. snps,axi-max-burst-len = <16>;
  1011. status = "okay";
  1012. };
  1013. dmac1: tee_dmac@ffff340000 {
  1014. compatible = "snps,axi-dma-1.01a";
  1015. reg = <0xff 0xff340000 0x0 0x1000>;
  1016. interrupt-parent = <&intc>;
  1017. interrupts = <150>;
  1018. clocks = <&dummy_clock_apb>, <&dummy_clock_apb>;
  1019. clock-names = "core-clk", "cfgr-clk";
  1020. #dma-cells = <1>;
  1021. dma-channels = <4>;
  1022. snps,block-size = <65536 65536 65536 65536>;
  1023. snps,priority = <0 1 2 3>;
  1024. snps,dma-masters = <1>;
  1025. snps,data-width = <4>;
  1026. snps,axi-max-burst-len = <16>;
  1027. status = "okay";
  1028. };
  1029. stmmac_axi_setup: stmmac-axi-config {
  1030. snps,wr_osr_lmt = <3>;
  1031. snps,rd_osr_lmt = <3>;
  1032. snps,blen = <16 8 4 0 0 0 0>;
  1033. };
  1034. gmac0: ethernet@ffe7070000 {
  1035. compatible = "thead,light-dwmac";
  1036. reg = <0xff 0xe7070000 0x0 0x2000
  1037. 0xff 0xec00301c 0x0 0x4
  1038. 0xff 0xec003020 0x0 0x4
  1039. 0xff 0xec003000 0x0 0x1c>;
  1040. reg-names = "gmac", "phy_if_reg", "txclk_dir_reg", "clk_mgr_reg";
  1041. interrupt-parent = <&intc>;
  1042. interrupts = <66>;
  1043. interrupt-names = "macirq";
  1044. clocks = <&clk CLKGEN_GMAC0_HCLK>, <&clk CLKGEN_GMAC0_CCLK>;
  1045. clock-names = "stmmaceth", "gmac_pll_clk";
  1046. snps,pbl = <32>;
  1047. snps,fixed-burst;
  1048. snps,axi-config = <&stmmac_axi_setup>;
  1049. nvmem-cells = <&gmac0_mac_address>;
  1050. nvmem-cell-names = "mac-address";
  1051. };
  1052. gmac1: ethernet@ffe7060000 {
  1053. compatible = "thead,light-dwmac";
  1054. reg = <0xff 0xe7060000 0x0 0x2000
  1055. 0xff 0xec00401c 0x0 0x4
  1056. 0xff 0xec004020 0x0 0x4
  1057. 0xff 0xec004000 0x0 0x1c>;
  1058. reg-names = "gmac", "phy_if_reg", "txclk_dir_reg", "clk_mgr_reg";
  1059. interrupt-parent = <&intc>;
  1060. interrupts = <67>;
  1061. interrupt-names = "macirq";
  1062. clocks = <&clk CLKGEN_GMAC1_HCLK>, <&clk CLKGEN_GMAC1_CCLK>;
  1063. clock-names = "stmmaceth", "gmac_pll_clk";
  1064. snps,pbl = <32>;
  1065. snps,fixed-burst;
  1066. snps,axi-config = <&stmmac_axi_setup>;
  1067. nvmem-cells = <&gmac1_mac_address>;
  1068. nvmem-cell-names = "mac-address";
  1069. };
  1070. emmc: sdhci@ffe7080000 {
  1071. compatible = "snps,dwcmshc-sdhci";
  1072. reg = <0xff 0xe7080000 0x0 0x10000
  1073. 0xff 0xef014060 0x0 0x4>;
  1074. interrupt-parent = <&intc>;
  1075. interrupts = <62>;
  1076. interrupt-names = "sdhciirq";
  1077. clocks = <&dummy_clock_sdhci>;
  1078. clock-names = "core";
  1079. };
  1080. sdhci0: sd@ffe7090000 {
  1081. compatible = "snps,dwcmshc-sdhci";
  1082. reg = <0xff 0xe7090000 0x0 0x10000
  1083. 0xff 0xef014064 0x0 0x4>;
  1084. interrupt-parent = <&intc>;
  1085. interrupts = <64>;
  1086. interrupt-names = "sdhci0irq";
  1087. clocks = <&dummy_clock_sdhci>;
  1088. clock-names = "core";
  1089. };
  1090. sdhci1: sd@ffe70a0000 {
  1091. compatible = "snps,dwcmshc-sdhci";
  1092. reg = <0xff 0xe70a0000 0x0 0x10000
  1093. 0xff 0xef014064 0x0 0x4>;
  1094. interrupt-parent = <&intc>;
  1095. interrupts = <71>;
  1096. interrupt-names = "sdhci1irq";
  1097. clocks = <&dummy_clock_sdhci>;
  1098. clock-names = "core";
  1099. };
  1100. hwspinlock: hwspinlock@ffefc10000 {
  1101. compatible = "light,hwspinlock";
  1102. reg = <0xff 0xefc10000 0x0 0x10000>;
  1103. status = "disabled";
  1104. };
  1105. npu: vha@fffc800000 {
  1106. compatible = "img,ax3386-nna";
  1107. reg = <0xff 0xfc800000 0x0 0x100000>;
  1108. interrupt-parent = <&intc>;
  1109. interrupts = <113>;
  1110. interrupt-names = "npuirq";
  1111. clocks = <&dummy_clock_npu>;
  1112. clock-names = "dummy_clock_npu";
  1113. vha_clk_rate = <24000000>;
  1114. ldo_vha-supply = <&npu>;
  1115. dma-mask = <0xf 0xffffffff>;
  1116. status = "disabled";
  1117. };
  1118. gpu: gpu@ffef400000 {
  1119. compatible = "img,gpu";
  1120. reg = <0xff 0xef400000 0x0 0x100000>;
  1121. interrupt-parent = <&intc>;
  1122. interrupts = <102>;
  1123. interrupt-names = "gpuirq";
  1124. clocks = <&dummy_clock_gpu>;
  1125. clock-names = "dummy_clock_gpu";
  1126. gpu_clk_rate = <18000000>;
  1127. dma-mask = <0xf 0xffffffff>;
  1128. status = "disabled";
  1129. };
  1130. fce: fce@fffcc50000 {
  1131. compatible = "thead,light-fce";
  1132. reg = <0xff 0xfcc50000 0x0 0x10000>;
  1133. interrupt-parent = <&intc>;
  1134. interrupts = <100>;
  1135. interrupt-names = "fceirq";
  1136. dma-mask = <0xf 0xffffffff>;
  1137. status = "disabled";
  1138. };
  1139. vdec: vdec@ffecc00000 {
  1140. compatible = "thead,light-vc8000d";
  1141. reg = <0xff 0xecc00000 0x0 0x8000>;
  1142. interrupt-parent = <&intc>;
  1143. interrupts = <131>;
  1144. status = "disabled";
  1145. };
  1146. venc: venc@ffecc10000 {
  1147. compatible = "thead,light-vc8000e";
  1148. reg = <0xff 0xecc10000 0x0 0x8000>;
  1149. interrupt-parent = <&intc>;
  1150. interrupts = <133>;
  1151. status = "disabled";
  1152. };
  1153. isp_venc_shake: shake@ffe4078000 {
  1154. compatible = "thead,light-ivs";
  1155. reg = <0xff 0xe4078000 0x0 0x1000>;
  1156. interrupt-parent = <&intc>;
  1157. interrupts = <158>;
  1158. status = "disabled";
  1159. };
  1160. vidmem: vidmem@ffecc08000 {
  1161. compatible = "thead,light-vidmem";
  1162. reg = <0xff 0xecc08000 0x0 0x1000>;
  1163. status = "disabled";
  1164. };
  1165. light_i2s: light_i2s@ffe7034000 {
  1166. #sound-dai-cells = <1>;
  1167. compatible = "light,light-i2s";
  1168. reg = <0xff 0xe7034000 0x0 0x4000>;
  1169. pinctrl-names = "default";
  1170. pinctrl-0 = <&pinctrl_audio_i2s0>;
  1171. light,mode = "i2s-master";
  1172. interrupt-parent = <&intc>;
  1173. interrupts = <70>;
  1174. dmas = <&dmac0 35>, <&dmac0 39>;
  1175. dma-names = "tx", "rx";
  1176. light,dma_maxburst = <4>;
  1177. #dma-cells = <1>;
  1178. clocks = <&dummy_clock_apb>;
  1179. clock-names = "pclk";
  1180. status = "disabled";
  1181. };
  1182. i2c0: i2c@ffe7f20000 {
  1183. compatible = "snps,designware-i2c";
  1184. reg = <0xff 0xe7f20000 0x0 0x4000>;
  1185. interrupt-parent = <&intc>;
  1186. interrupts = <44>;
  1187. clocks = <&dummy_clock_apb>;
  1188. clock-frequency = <100000>;
  1189. ss_hcnt = /bits/ 16 <0x104>;
  1190. ss_lcnt = /bits/ 16 <0xec>;
  1191. fs_hcnt = /bits/ 16 <0x37>;
  1192. fs_lcnt = /bits/ 16 <0x42>;
  1193. fp_hcnt = /bits/ 16 <0x14>;
  1194. fp_lcnt = /bits/ 16 <0x1a>;
  1195. hs_hcnt = /bits/ 16 <0x2>;
  1196. hs_lcnt = /bits/ 16 <0x7>;
  1197. #address-cells = <1>;
  1198. #size-cells = <0>;
  1199. };
  1200. i2c1: i2c@ffe7f24000 {
  1201. compatible = "snps,designware-i2c";
  1202. reg = <0xff 0xe7f24000 0x0 0x4000>;
  1203. interrupt-parent = <&intc>;
  1204. interrupts = <45>;
  1205. clocks = <&dummy_clock_apb>;
  1206. clock-frequency = <100000>;
  1207. ss_hcnt = /bits/ 16 <0x104>;
  1208. ss_lcnt = /bits/ 16 <0xec>;
  1209. fs_hcnt = /bits/ 16 <0x37>;
  1210. fs_lcnt = /bits/ 16 <0x42>;
  1211. fp_hcnt = /bits/ 16 <0x14>;
  1212. fp_lcnt = /bits/ 16 <0x1a>;
  1213. hs_hcnt = /bits/ 16 <0x2>;
  1214. hs_lcnt = /bits/ 16 <0x6>;
  1215. #address-cells = <1>;
  1216. #size-cells = <0>;
  1217. };
  1218. i2c2: i2c@ffec00c000{
  1219. compatible = "snps,designware-i2c";
  1220. reg = <0xff 0xec00c000 0x0 0x4000>;
  1221. interrupt-parent = <&intc>;
  1222. interrupts = <46>;
  1223. clocks = <&dummy_clock_apb>;
  1224. clock-frequency = <100000>;
  1225. ss_hcnt = /bits/ 16 <0x104>;
  1226. ss_lcnt = /bits/ 16 <0xec>;
  1227. fs_hcnt = /bits/ 16 <0x37>;
  1228. fs_lcnt = /bits/ 16 <0x42>;
  1229. fp_hcnt = /bits/ 16 <0x14>;
  1230. fp_lcnt = /bits/ 16 <0x1a>;
  1231. hs_hcnt = /bits/ 16 <0x2>;
  1232. hs_lcnt = /bits/ 16 <0x7>;
  1233. status = "disabled";
  1234. #address-cells = <1>;
  1235. #size-cells = <0>;
  1236. };
  1237. i2c3: i2c@ffec014000{
  1238. compatible = "snps,designware-i2c";
  1239. reg = <0xff 0xec014000 0x0 0x4000>;
  1240. interrupt-parent = <&intc>;
  1241. interrupts = <47>;
  1242. clocks = <&dummy_clock_apb>;
  1243. clock-frequency = <100000>;
  1244. ss_hcnt = /bits/ 16 <0x104>;
  1245. ss_lcnt = /bits/ 16 <0xec>;
  1246. fs_hcnt = /bits/ 16 <0x37>;
  1247. fs_lcnt = /bits/ 16 <0x42>;
  1248. fp_hcnt = /bits/ 16 <0x14>;
  1249. fp_lcnt = /bits/ 16 <0x1a>;
  1250. hs_hcnt = /bits/ 16 <0x2>;
  1251. hs_lcnt = /bits/ 16 <0x7>;
  1252. status = "disabled";
  1253. #address-cells = <1>;
  1254. #size-cells = <0>;
  1255. };
  1256. i2c4: i2c@ffe7f28000{
  1257. compatible = "snps,designware-i2c";
  1258. reg = <0xff 0xe7f28000 0x0 0x4000>;
  1259. interrupt-parent = <&intc>;
  1260. interrupts = <48>;
  1261. clocks = <&dummy_clock_apb>;
  1262. clock-frequency = <100000>;
  1263. ss_hcnt = /bits/ 16 <0x104>;
  1264. ss_lcnt = /bits/ 16 <0xec>;
  1265. fs_hcnt = /bits/ 16 <0x37>;
  1266. fs_lcnt = /bits/ 16 <0x42>;
  1267. fp_hcnt = /bits/ 16 <0x14>;
  1268. fp_lcnt = /bits/ 16 <0x1a>;
  1269. hs_hcnt = /bits/ 16 <0x2>;
  1270. hs_lcnt = /bits/ 16 <0x7>;
  1271. status = "disabled";
  1272. #address-cells = <1>;
  1273. #size-cells = <0>;
  1274. };
  1275. isp0: isp@ffe4100000 {
  1276. compatible = "thead,light-isp";
  1277. reg = <0xff 0xe4100000 0x0 0x10000>;
  1278. interrupt-parent = <&intc>;
  1279. interrupts = <117>,<118>;
  1280. status = "disabled";
  1281. };
  1282. isp1: isp@ffe4110000 {
  1283. compatible = "thead,light-isp";
  1284. reg = <0xff 0xe4110000 0x0 0x10000>;
  1285. interrupt-parent = <&intc>;
  1286. interrupts = <120>,<121>;
  1287. status = "disabled";
  1288. };
  1289. isp_ry0: isp_ry@ffe4120000 {
  1290. compatible = "thead,light-isp_ry";
  1291. reg = <0xff 0xe4120000 0x0 0x10000>;
  1292. interrupt-parent = <&intc>;
  1293. interrupts = <123>,<124>;
  1294. status = "disabled";
  1295. };
  1296. dewarp: dewarp@ffe4130000 {
  1297. compatible = "thead,light-dewarp";
  1298. reg = <0xff 0xe4130000 0x0 0x10000>;
  1299. interrupt-parent = <&intc>;
  1300. interrupts = <98>,<99>;
  1301. status = "disabled";
  1302. };
  1303. dec400_isp0: dec400@ffe4060000 {
  1304. compatible = "thead,dec400";
  1305. reg = <0xff 0xe4060000 0x0 0x8000>;
  1306. status = "disabled";
  1307. };
  1308. dec400_isp1: dec400@ffe4068000 {
  1309. compatible = "thead,dec400";
  1310. reg = <0xff 0xe4068000 0x0 0x8000>;
  1311. status = "disabled";
  1312. };
  1313. dec400_isp2: dec400@ffe4070000 {
  1314. compatible = "thead,dec400";
  1315. reg = <0xff 0xe4070000 0x0 0x8000>;
  1316. status = "disabled";
  1317. };
  1318. bm_visys: bm_visys@ffe4040000 {
  1319. compatible = "thead,light-bm-visys";
  1320. reg = <0xff 0xe4040000 0x0 0x1000>;
  1321. status = "disabled";
  1322. };
  1323. bm_csi0: csi@ffe4000000{ //CSI2
  1324. compatible = "thead,light-bm-csi";
  1325. reg = < 0xff 0xe4000000 0x0 0x10000>;
  1326. interrupt-parent = <&intc>;
  1327. interrupts = <128>;
  1328. dphyglueiftester = <0x180>;
  1329. sysreg_mipi_csi_ctrl = <0x140>;
  1330. status = "disabled";
  1331. };
  1332. bm_csi1: csi@ffe4010000{ //CSI2X2_B
  1333. compatible = "thead,light-bm-csi";
  1334. reg = < 0xff 0xe4010000 0x0 0x10000>;
  1335. interrupt-parent = <&intc>;
  1336. interrupts = <126>; // 110 + 16 int_mipi_csi2x2_int0
  1337. dphyglueiftester = <0x182>; // for FPGA PHY only. ASIC not needed.
  1338. sysreg_mipi_csi_ctrl = <0x148>;
  1339. status = "disabled";
  1340. };
  1341. bm_csi2: csi@ffe4020000{ //CSI2X2_A
  1342. compatible = "thead,light-bm-csi";
  1343. reg = < 0xff 0xe4020000 0x0 0x10000>;
  1344. interrupt-parent = <&intc>;
  1345. interrupts = <127>;
  1346. dphyglueiftester = <0x184>;
  1347. sysreg_mipi_csi_ctrl = <0x144>;
  1348. status = "disabled";
  1349. };
  1350. bm_isp0: bm_isp@ffe4100000 {
  1351. compatible = "thead,light-bm-isp";
  1352. reg = <0xff 0xe4100000 0x0 0x10000>;
  1353. status = "disabled";
  1354. };
  1355. bm_isp1: bm_isp@ffe4110000 {
  1356. compatible = "thead,light-bm-isp";
  1357. reg = <0xff 0xe4110000 0x0 0x10000>;
  1358. status = "disabled";
  1359. };
  1360. //isp-ry
  1361. bm_isp2: bm_isp@ffe4120000 {
  1362. compatible = "thead,light-bm-isp";
  1363. reg = <0xff 0xe4120000 0x0 0x10000>;
  1364. status = "disabled";
  1365. };
  1366. vi_pre: vi_pre@ffe4030000 {
  1367. compatible = "thead,vi_pre";
  1368. reg = <0xff 0xe4030000 0x0 0x1000>;
  1369. interrupt-parent = <&intc>;
  1370. interrupts = <134>;
  1371. status = "disabled";
  1372. };
  1373. video0: cam_dev@100 {
  1374. compatible = "thead,video";
  1375. status = "disabled";
  1376. };
  1377. video1: cam_dev@200 {
  1378. compatible = "thead,video";
  1379. status = "disabled";
  1380. };
  1381. video2: cam_dev@300 {
  1382. compatible = "thead,video";
  1383. status = "disabled";
  1384. };
  1385. vvcam_sensor0: vvcam_sensor@0 {
  1386. compatible = "thead,light-vvcam-sensor";
  1387. status = "disabled";
  1388. };
  1389. vvcam_sensor1: vvcam_sensor@1 {
  1390. compatible = "thead,light-vvcam-sensor";
  1391. status = "disabled";
  1392. };
  1393. vvcam_sensor2: vvcam_sensor@2 {
  1394. compatible = "thead,light-vvcam-sensor";
  1395. status = "disabled";
  1396. };
  1397. vvcam_sensor3: vvcam_sensor@3 {
  1398. compatible = "thead,light-vvcam-sensor";
  1399. status = "disabled";
  1400. };
  1401. vvcam_sensor4: vvcam_sensor@4 {
  1402. compatible = "thead,light-vvcam-sensor";
  1403. status = "disabled";
  1404. };
  1405. vvcam_sensor5: vvcam_sensor@5 {
  1406. compatible = "thead,light-vvcam-sensor";
  1407. status = "disabled";
  1408. };
  1409. vvcam_sensor6: vvcam_sensor@6 {
  1410. compatible = "thead,light-vvcam-sensor";
  1411. status = "disabled";
  1412. };
  1413. xtensa_dsp: dsp@01{
  1414. compatible = "thead,dsp-hw-common";
  1415. reg = <0xff 0xef040000 0x0 0x001000 >; /*DSP_SYSREG(0x0000-0xFFF) */
  1416. status = "disabled";
  1417. };
  1418. xtensa_dsp0: dsp@0 {
  1419. compatible = "cdns,xrp-hw-simple";
  1420. reg = <0xff 0xe4040190 0x0 0x000010 /* host irq DSP->CPU INT Register */
  1421. 0xff 0xe40401e0 0x0 0x000010 /* device irq CPU->DSP INT Register */
  1422. 0xff 0xef048000 0x0 0x008000 /*DSP_APB(0x0000-0xFFF) */
  1423. 0x00 0x90000000 0x0 0x00001000 /* DSP communication area */
  1424. 0x0 0x90001000 0x0 0x00fff000>; /* DSP shared memory */
  1425. dsp = <0>;
  1426. dspsys-rst-bit = <8>; /*bit# in DSP_SYSREG*/
  1427. dspsys-bus-offset = <0x90>; /*in DSP_SYSREG*/
  1428. device-irq = <0x4 1 24>; /*0xff 0xe40401e4 offset to clear DSP I]RQ, bit#, IRQ# */
  1429. device-irq-host-offset = <0x8>; /*0xff 0xe40401e8 offset to trigger DSP IRQ*/
  1430. device-irq-mode = <1>; /*level trigger*/
  1431. host-irq = <0x4 1>; /*0xff 0xe4040194 offset to clear, bit# */
  1432. host-irq-mode = <1>; /*level trigger */
  1433. host-irq-offset = <0x8>; /* 0xff 0xe4040198 offset to trigger ,device side*/
  1434. interrupt-parent = <&intc>;
  1435. interrupts = <156>;
  1436. firmware-name = "xrp0.elf";
  1437. status = "disabled";
  1438. #address-cells = <2>;
  1439. #size-cells = <1>;
  1440. ranges = <0x00 0x70000000 0x00 0x70000000 0x40000000
  1441. 0x00 0xfa000000 0xff 0xe0000000 0x00180000
  1442. 0x00 0xe0180000 0xff 0xe0180000 0x00040000
  1443. 0x00 0xffc00000 0xff 0xe4000000 0x00200000 >; /* VISYS_R */
  1444. dsp@0 {
  1445. ranges = <0x00 0x70000000 0x00 0x70000000 0x40000000
  1446. 0x00 0xfa000000 0xff 0xe0000000 0x00180000
  1447. 0x00 0xe0180000 0xff 0xe0180000 0x00040000
  1448. 0x00 0xffc00000 0xff 0xe4000000 0x00200000 >; /* VISYS_R */
  1449. };
  1450. };
  1451. xtensa_dsp1: dsp@1 {
  1452. compatible = "cdns,xrp-hw-simple";
  1453. reg = <0xff 0xe40401a0 0x0 0x000010 /* host irq DSP->CPU INT Register */
  1454. 0xff 0xe40401d0 0x0 0x000010 /* device irq CPU->DSP INT Register */
  1455. 0xff 0xef050000 0x0 0x008000 /*DSP_APB(0x0000-0xFFF) */
  1456. 0x00 0xa0000000 0x0 0x00001000 /* DSP communication area */
  1457. 0x0 0xa0001000 0x0 0x00fff000>; /* DSP shared memory */
  1458. dsp = <1>;
  1459. dspsys-rst-bit = <8>; /*bit# in DSP_SYSREG*/
  1460. dspsys-bus-offset = <0x90>; /*in DSP_SYSREG*/
  1461. device-irq = <0x4 1 24>; /*0xff 0xe40401e4 offset to clear DSP I]RQ, bit#, IRQ# */
  1462. device-irq-host-offset = <0x8>; /*0xff 0xe40401e8 offset to trigger DSP IRQ*/
  1463. device-irq-mode = <1>; /*level trigger*/
  1464. host-irq = <0x4 1>; /*0xff 0xe4040194 offset to clear, bit# */
  1465. host-irq-mode = <1>; /*level trigger */
  1466. host-irq-offset = <0x8>; /* 0xff 0xe4040198 offset to trigger ,device side*/
  1467. interrupt-parent = <&intc>;
  1468. interrupts = <157>;
  1469. firmware-name = "xrp1.elf";
  1470. status = "disabled";
  1471. #address-cells = <2>;
  1472. #size-cells = <1>;
  1473. ranges = <0x00 0x70000000 0x00 0x70000000 0x40000000
  1474. 0x00 0xfa000000 0xff 0xe0000000 0x00180000
  1475. 0x00 0xe0180000 0xff 0xe01C0000 0x00040000
  1476. 0x00 0xffc00000 0xff 0xe4000000 0x00200000 >; /* VISYS_R */
  1477. dsp@0 {
  1478. ranges = <0x00 0x70000000 0x00 0x70000000 0x40000000
  1479. 0x00 0xfa000000 0xff 0xe0000000 0x00180000
  1480. 0x00 0xe0180000 0xff 0xe01C0000 0x00040000
  1481. 0x00 0xffc00000 0xff 0xe4000000 0x00200000 >; /* VISYS_R */
  1482. };
  1483. };
  1484. pmp: pmp@ffdc020000 {
  1485. compatible = "pmp";
  1486. reg = <0xff 0xdc020000 0x0 0x1000>;
  1487. };
  1488. mrvbr: mrvbr@ffff018050 {
  1489. compatible = "mrvbr";
  1490. reg = <0xff 0xff019050 0x0 0x1000>;
  1491. };
  1492. mrmr: mrmr@ffff014004 {
  1493. compatible = "mrmr";
  1494. reg = <0xff 0xff015004 0x0 0x1000>;
  1495. };
  1496. bmu: ddr-pmu@ffff008000 {
  1497. compatible = "thead,light-ddr-pmu";
  1498. reg = <0xff 0xff008000 0x0 0x800
  1499. 0xff 0xff008800 0x0 0x800
  1500. 0xff 0xff009000 0x0 0x800
  1501. 0xff 0xff009800 0x0 0x800
  1502. 0xff 0xff00a000 0x0 0x800>;
  1503. interrupt-parent = <&intc>;
  1504. interrupts = <87>;
  1505. status = "okay";
  1506. };
  1507. mbox_910t: mbox@ffffc38000 {
  1508. compatible = "thead,light-mbox";
  1509. reg = <0xff 0xffc38000 0x0 0x4000>,
  1510. <0xff 0xffc44000 0x0 0x1000>,
  1511. <0xff 0xffc4c000 0x0 0x1000>,
  1512. <0xff 0xffc54000 0x0 0x1000>;
  1513. reg-names = "local_base", "remote_icu0", "remote_icu1", "remote_icu2";
  1514. interrupt-parent = <&intc>;
  1515. interrupts = <28>;
  1516. clocks = <&dummy_clock_apb>;
  1517. clock-names = "ipg";
  1518. icu_cpu_id = <0>;
  1519. #mbox-cells = <2>;
  1520. };
  1521. trng: rng@ffff300000 {
  1522. compatible = "inside-secure,safexcel-eip76";
  1523. reg = <0xff 0xff300000 0x0 0x7d>;
  1524. interrupt-parent = <&intc>;
  1525. interrupts = <149>;
  1526. clocks = <&dummy_clock_eip>;
  1527. status = "disabled";
  1528. };
  1529. eip_28: eip-28@ffff300000 {
  1530. compatible = "xlnx,sunrise-fpga-1.0", "safexcel-eip-28";
  1531. reg = <0xff 0xff300000 0x0 0x40000>;
  1532. interrupt-parent = <&intc>;
  1533. interrupts = <144>,<145>,<146>,<147>;
  1534. clocks = <&dummy_clock_eip>;
  1535. status = "disabled";
  1536. };
  1537. };
  1538. aon {
  1539. compatible = "thead,light-aon";
  1540. mbox-names = "aon";
  1541. mboxes = <&mbox_910t 1 0>;
  1542. status = "okay";
  1543. pd: light-aon-pd {
  1544. compatible = "thead,light-aon-pd";
  1545. #power-domain-cells = <1>;
  1546. };
  1547. soc_dovdd18_scan_reg: soc_dovdd18_scan {
  1548. compatible = "regulator-fixed";
  1549. regulator-name = "soc_dovdd18_scan";
  1550. regulator-min-microvolt = <1800000>;
  1551. regulator-max-microvolt = <1800000>;
  1552. gpio = <&gpio0_porta 10 1>;
  1553. enable-active-high;
  1554. regulator-always-on;
  1555. };
  1556. soc_vext_2v8_reg: soc_vext_2v8 {
  1557. compatible = "regulator-fixed";
  1558. regulator-name = "soc_vext_2v8";
  1559. regulator-min-microvolt = <2800000>;
  1560. regulator-max-microvolt = <2800000>;
  1561. gpio = <&gpio1_porta 7 1>;
  1562. enable-active-high;
  1563. regulator-always-on;
  1564. };
  1565. soc_dvdd12_scan_reg: soc_dvdd12_scan {
  1566. compatible = "regulator-fixed";
  1567. regulator-name = "soc_dvdd12_scan";
  1568. regulator-min-microvolt = <1200000>;
  1569. regulator-max-microvolt = <1200000>;
  1570. gpio = <&gpio0_porta 11 1>;
  1571. enable-active-high;
  1572. regulator-always-on;
  1573. };
  1574. soc_avdd28_scan_en_reg: soc_avdd28_scan_en {
  1575. compatible = "regulator-fixed";
  1576. regulator-name = "soc_avdd28_scan_en";
  1577. regulator-min-microvolt = <2800000>;
  1578. regulator-max-microvolt = <2800000>;
  1579. gpio = <&ao_gpio_porta 14 1>;
  1580. enable-active-high;
  1581. regulator-always-on;
  1582. };
  1583. soc_avdd28_rgb_reg: soc_avdd28_rgb {
  1584. compatible = "regulator-fixed";
  1585. regulator-name = "soc_avdd28_rgb";
  1586. regulator-min-microvolt = <2800000>;
  1587. regulator-max-microvolt = <2800000>;
  1588. gpio = <&gpio1_porta 24 1>;
  1589. enable-active-high;
  1590. regulator-always-on;
  1591. };
  1592. soc_dovdd18_rgb_reg: soc_dovdd18_rgb {
  1593. compatible = "regulator-fixed";
  1594. regulator-name = "soc_dovdd18_rgb";
  1595. regulator-min-microvolt = <2800000>;
  1596. regulator-max-microvolt = <2800000>;
  1597. gpio = <&gpio1_porta 22 1>;
  1598. enable-active-high;
  1599. regulator-always-on;
  1600. };
  1601. soc_dvdd12_rgb_reg: soc_dvdd12_rgb {
  1602. compatible = "regulator-fixed";
  1603. regulator-name = "soc_dvdd12_rgb";
  1604. regulator-min-microvolt = <2800000>;
  1605. regulator-max-microvolt = <2800000>;
  1606. gpio = <&gpio1_porta 23 1>;
  1607. enable-active-high;
  1608. regulator-always-on;
  1609. };
  1610. soc_avdd25_ir_reg: soc_avdd25_ir {
  1611. compatible = "regulator-fixed";
  1612. regulator-name = "soc_avdd25_ir";
  1613. regulator-min-microvolt = <2800000>;
  1614. regulator-max-microvolt = <2800000>;
  1615. gpio = <&gpio1_porta 7 1>;
  1616. enable-active-high;
  1617. regulator-always-on;
  1618. };
  1619. soc_dovdd18_ir_reg: soc_dovdd18_ir {
  1620. compatible = "regulator-fixed";
  1621. regulator-name = "soc_dovdd18_ir";
  1622. regulator-min-microvolt = <2800000>;
  1623. regulator-max-microvolt = <2800000>;
  1624. gpio = <&gpio1_porta 7 1>;
  1625. enable-active-high;
  1626. regulator-always-on;
  1627. };
  1628. soc_dvdd12_ir_reg: soc_dvdd12_ir {
  1629. compatible = "regulator-fixed";
  1630. regulator-name = "soc_dvdd12_ir";
  1631. regulator-min-microvolt = <2800000>;
  1632. regulator-max-microvolt = <2800000>;
  1633. gpio = <&gpio1_porta 7 1>;
  1634. enable-active-high;
  1635. regulator-always-on;
  1636. };
  1637. aon_reg_ricoh: light-ricoh-reg {
  1638. compatible = "thead,light-ricoh-pmic";
  1639. status = "okay";
  1640. dvdd_cpu_reg: appcpu_dvdd {
  1641. regulator-name = "appcpu_dvdd";
  1642. regulator-min-microvolt = <600000>;
  1643. regulator-max-microvolt = <1500000>;
  1644. regulator-boot-on;
  1645. regulator-always-on;
  1646. };
  1647. dvddm_cpu_reg: appcpu_dvddm {
  1648. regulator-name = "appcpu_dvddm";
  1649. regulator-min-microvolt = <600000>;
  1650. regulator-max-microvolt = <1500000>;
  1651. regulator-boot-on;
  1652. regulator-always-on;
  1653. };
  1654. soc_dvdd18_aon_reg: soc_dvdd18_aon {
  1655. regulator-name = "soc_dvdd18_aon";
  1656. regulator-boot-on;
  1657. regulator-always-on;
  1658. };
  1659. soc_avdd33_usb3_reg: soc_avdd33_usb3 {
  1660. regulator-name = "soc_avdd33_usb3";
  1661. regulator-boot-on;
  1662. regulator-always-on;
  1663. };
  1664. soc_dvdd08_aon_reg: soc_dvdd08_aon {
  1665. regulator-name = "soc_dvdd08_aon";
  1666. regulator-boot-on;
  1667. regulator-always-on;
  1668. };
  1669. soc_dvdd08_ddr_reg: soc_dvdd08_ddr {
  1670. regulator-name = "soc_dvdd08_ddr";
  1671. regulator-boot-on;
  1672. regulator-always-on;
  1673. };
  1674. soc_vdd_ddr_1v8_reg: soc_vdd_ddr_1v8 {
  1675. regulator-name = "soc_vdd_ddr_1v8";
  1676. regulator-boot-on;
  1677. regulator-always-on;
  1678. };
  1679. soc_vdd_ddr_1v1_reg: soc_vdd_ddr_1v1 {
  1680. regulator-name = "soc_vdd_ddr_1v1";
  1681. regulator-boot-on;
  1682. regulator-always-on;
  1683. };
  1684. soc_vdd_ddr_0v6_reg: soc_vdd_ddr_0v6 {
  1685. regulator-name = "soc_vdd_ddr_0v6";
  1686. regulator-boot-on;
  1687. regulator-always-on;
  1688. };
  1689. soc_dvdd18_ap_reg: soc_dvdd18_ap {
  1690. regulator-name = "soc_dvdd18_ap";
  1691. regulator-boot-on;
  1692. regulator-always-on;
  1693. };
  1694. soc_dvdd08_ap_reg: soc_dvdd08_ap {
  1695. regulator-name = "soc_dvdd08_ap";
  1696. regulator-boot-on;
  1697. regulator-always-on;
  1698. };
  1699. soc_avdd08_mipi_hdmi_reg: soc_avdd08_mipi_hdmi {
  1700. regulator-name = "soc_avdd08_mipi_hdmi";
  1701. regulator-boot-on;
  1702. regulator-always-on;
  1703. };
  1704. soc_avdd18_mipi_hdmi_reg: soc_avdd18_mipi_hdmi {
  1705. regulator-name = "soc_avdd18_mipi_hdmi";
  1706. regulator-boot-on;
  1707. regulator-always-on;
  1708. };
  1709. soc_vdd33_emmc_reg: soc_vdd33_emmc {
  1710. regulator-name = "soc_vdd33_emmc";
  1711. regulator-boot-on;
  1712. regulator-always-on;
  1713. };
  1714. soc_vdd18_emmc_reg: soc_vdd18_emmc {
  1715. regulator-name = "soc_vdd18_emmc";
  1716. regulator-boot-on;
  1717. regulator-always-on;
  1718. };
  1719. };
  1720. c910_cpufreq {
  1721. compatible = "thead,light-mpw-cpufreq";
  1722. status = "okay";
  1723. };
  1724. test: light-aon-test {
  1725. compatible = "thead,light-aon-test";
  1726. };
  1727. };
  1728. };