/* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (C) 2021 Alibaba Group Holding Limited. */ #include #include #include #include #include / { compatible = "thead,light"; #address-cells = <2>; #size-cells = <2>; aliases { ethernet0 = &gmac0; ethernet1 = &gmac1; gpio0 = &gpio0; gpio1 = &gpio1; gpio2 = &gpio2; gpio3 = &gpio3; i2c0 = &i2c0; i2c2 = &i2c2; i2c3 = &i2c3; i2c4 = &i2c4; mmc0 = &emmc; mmc1 = &sdhci0; serial0 = &uart0; serial1 = &uart1; serial2 = &uart2; serial3 = &uart3; serial4 = &uart4; serial5 = &uart5; spi0 = &spi0; spi1 = &qspi0; spi2 = &qspi1; vivcam0 = &vvcam_sensor0; vivcam1 = &vvcam_sensor1; vivcam2= &vvcam_sensor2; vivcam3= &vvcam_sensor3; vivcam4= &vvcam_sensor4; vivcam5= &vvcam_sensor5; vivcam6= &vvcam_sensor6; }; memory@0 { device_type = "memory"; reg = <0x0 0x00000000 0x1 0x00000000>; }; resmem: reserved-memory { #address-cells = <2>; #size-cells = <2>; ranges; /* global autoconfigured region for contiguous allocations */ linux,cma { compatible = "shared-dma-pool"; reusable; size = <0 0x14000000>; alloc-ranges = <0 0x20000000 0 0x40000000>; linux,cma-default; }; }; cpus: cpus { #address-cells = <1>; #size-cells = <0>; timebase-frequency = <3000000>; c910_0: cpu@0 { device_type = "cpu"; reg = <0>; status = "okay"; compatible = "riscv"; riscv,isa = "rv64imafdcvsu"; mmu-type = "riscv,sv39"; cpu-freq = "1.848Ghz"; cpu-icache = "64KB"; cpu-dcache = "64KB"; cpu-l2cache = "1MB"; cpu-tlb = "1024 4-ways"; cpu-cacheline = "64Bytes"; cpu-vector = "0.7.1"; operating-points = < /* kHz uV */ 300000 600000 800000 700000 1500000 800000 1848000 1000000 >; light,dvddm-operating-points = < /* kHz uV */ 300000 750000 800000 800000 1500000 800000 1848000 1000000 >; clock-latency = <61036>; clocks = <&clk C910_CCLK>, <&clk C910_CCLK_I0>, <&clk CPU_PLL1_FOUTPOSTDIV>, <&clk CPU_PLL0_FOUTPOSTDIV>; clock-names = "c910_cclk", "c910_cclk_i0", "cpu_pll1_foutpostdiv", "cpu_pll0_foutpostdiv"; dvdd-supply = <&dvdd_cpu_reg>; dvddm-supply = <&dvddm_cpu_reg>; cpu0_intc: interrupt-controller { #interrupt-cells = <1>; compatible = "riscv,cpu-intc"; interrupt-controller; }; }; c910_1: cpu@1 { device_type = "cpu"; reg = <1>; status = "okay"; compatible = "riscv"; riscv,isa = "rv64imafdcvsu"; mmu-type = "riscv,sv39"; cpu-freq = "1.848Ghz"; cpu-icache = "64KB"; cpu-dcache = "64KB"; cpu-l2cache = "1MB"; cpu-tlb = "1024 4-ways"; cpu-cacheline = "64Bytes"; cpu-vector = "0.7.1"; operating-points = < /* kHz uV */ 300000 600000 800000 700000 1500000 800000 1848000 1000000 >; light,dvddm-operating-points = < /* kHz uV */ 300000 750000 800000 800000 1500000 800000 1848000 1000000 >; clock-latency = <61036>; clocks = <&clk C910_CCLK>, <&clk C910_CCLK_I0>, <&clk CPU_PLL1_FOUTPOSTDIV>, <&clk CPU_PLL0_FOUTPOSTDIV>; clock-names = "c910_cclk", "c910_cclk_i0", "cpu_pll1_foutpostdiv", "cpu_pll0_foutpostdiv"; dvdd-supply = <&dvdd_cpu_reg>; dvddm-supply = <&dvddm_cpu_reg>; cpu1_intc: interrupt-controller { #interrupt-cells = <1>; compatible = "riscv,cpu-intc"; interrupt-controller; }; }; c910_2: cpu@2 { device_type = "cpu"; reg = <2>; status = "okay"; compatible = "riscv"; riscv,isa = "rv64imafdcvsu"; mmu-type = "riscv,sv39"; cpu-freq = "1.848Ghz"; cpu-icache = "64KB"; cpu-dcache = "64KB"; cpu-l2cache = "1MB"; cpu-tlb = "1024 4-ways"; cpu-cacheline = "64Bytes"; cpu-vector = "0.7.1"; operating-points = < /* kHz uV */ 300000 600000 800000 700000 1500000 800000 1848000 1000000 >; light,dvddm-operating-points = < /* kHz uV */ 300000 750000 800000 800000 1500000 800000 1848000 1000000 >; clock-latency = <61036>; clocks = <&clk C910_CCLK>, <&clk C910_CCLK_I0>, <&clk CPU_PLL1_FOUTPOSTDIV>, <&clk CPU_PLL0_FOUTPOSTDIV>; clock-names = "c910_cclk", "c910_cclk_i0", "cpu_pll1_foutpostdiv", "cpu_pll0_foutpostdiv"; dvdd-supply = <&dvdd_cpu_reg>; dvddm-supply = <&dvddm_cpu_reg>; cpu2_intc: interrupt-controller { #interrupt-cells = <1>; compatible = "riscv,cpu-intc"; interrupt-controller; }; }; c910_3: cpu@3 { device_type = "cpu"; reg = <3>; status = "okay"; compatible = "riscv"; riscv,isa = "rv64imafdcvsu"; mmu-type = "riscv,sv39"; cpu-freq = "1.848Ghz"; cpu-icache = "64KB"; cpu-dcache = "64KB"; cpu-l2cache = "1MB"; cpu-tlb = "1024 4-ways"; cpu-cacheline = "64Bytes"; cpu-vector = "0.7.1"; operating-points = < /* kHz uV */ 300000 600000 800000 700000 1500000 800000 1848000 1000000 >; light,dvddm-operating-points = < /* kHz uV */ 300000 750000 800000 800000 1500000 800000 1848000 1000000 >; clock-latency = <61036>; clocks = <&clk C910_CCLK>, <&clk C910_CCLK_I0>, <&clk CPU_PLL1_FOUTPOSTDIV>, <&clk CPU_PLL0_FOUTPOSTDIV>; clock-names = "c910_cclk", "c910_cclk_i0", "cpu_pll1_foutpostdiv", "cpu_pll0_foutpostdiv"; dvdd-supply = <&dvdd_cpu_reg>; dvddm-supply = <&dvddm_cpu_reg>; cpu3_intc: interrupt-controller { #interrupt-cells = <1>; compatible = "riscv,cpu-intc"; interrupt-controller; }; }; }; display-subsystem { compatible = "verisilicon,display-subsystem"; ports = <&dpu_disp0>, <&dpu_disp1>; status = "disabled"; }; dpu-encoders { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <0>; dpu_enc0: dpu-encoder@0 { /* default encoder is DSI */ compatible = "verisilicon,dsi-encoder"; reg = <0>; status = "disabled"; ports { #address-cells = <1>; #size-cells = <0>; /* input */ port@0 { reg = <0>; enc0_in: endpoint { remote-endpoint = <&disp0_out>; }; }; }; }; dpu_enc1: dpu-encoder@1 { /* default encoder is DSI */ compatible = "verisilicon,dsi-encoder"; reg = <1>; status = "disabled"; ports { #address-cells = <1>; #size-cells = <0>; /* input */ port@0 { reg = <0>; enc1_in: endpoint { remote-endpoint = <&disp1_out>; }; }; }; }; }; soc { compatible = "simple-bus"; #address-cells = <2>; #size-cells = <2>; ranges; reset: reset-sample { compatible = "thead,reset-sample"; plic-delegate = <0xff 0xd81ffffc>; entry-reg = <0xff 0xff019050>; entry-cnt = <4>; control-reg = <0xff 0xff015004>; control-val = <0x1c>; csr-copy = <0x7f3 0x7c0 0x7c1 0x7c2 0x7c3 0x7c5 0x7cc>; }; clint0: clint@ffdc000000 { compatible = "riscv,clint0"; interrupts-extended = < &cpu0_intc 3 &cpu0_intc 7 &cpu1_intc 3 &cpu1_intc 7 &cpu2_intc 3 &cpu2_intc 7 &cpu3_intc 3 &cpu3_intc 7 >; reg = <0xff 0xdc000000 0x0 0x04000000>; clint,has-no-64bit-mmio; }; intc: interrupt-controller@ffd8000000 { #interrupt-cells = <1>; compatible = "riscv,plic0"; interrupt-controller; interrupts-extended = < &cpu0_intc 0xffffffff &cpu0_intc 9 &cpu1_intc 0xffffffff &cpu1_intc 9 &cpu2_intc 0xffffffff &cpu2_intc 9 &cpu3_intc 0xffffffff &cpu3_intc 9 >; reg = <0xff 0xd8000000 0x0 0x04000000>; reg-names = "control"; riscv,max-priority = <7>; riscv,ndev = <240>; }; clocks { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <0>; dummy_clock_apb: apb-clock@0 { compatible = "fixed-clock"; reg = <0>; /* Not address, just for index */ clock-frequency = <62500000>; clock-output-names = "dummy_clock_apb"; #clock-cells = <0>; }; dummy_clock_ref: ref-clock@1 { compatible = "fixed-clock"; reg = <1>; /* Not address, just for index */ clock-frequency = <50000000>; clock-output-names = "dummy_clock_ref"; #clock-cells = <0>; }; dummy_clock_suspend: suspend-clock@2 { compatible = "fixed-clock"; reg = <2>; /* Not address, just for index */ clock-frequency = <50000000>; clock-output-names = "dummy_clock_suspend"; #clock-cells = <0>; }; dummy_clock_rtc: rtc-clock@3 { compatible = "fixed-clock"; reg = <3>; /* Not address, just for index */ clock-frequency = <32768>; clock-output-names = "dummy_clock_rtc"; #clock-cells = <0>; }; dummy_clock_ahb: ahb-clock@4 { compatible = "fixed-clock"; reg = <4>; /* Not address, just for index */ clock-frequency = <50000000>; clock-output-names = "dummy_clock_ahb"; #clock-cells = <0>; }; dummy_clock_npu: npu-clock@5 { compatible = "fixed-clock"; reg = <5>; /* Not address, just for index */ clock-frequency = <24000000>; clock-output-names = "dummy_clock_npu"; #clock-cells = <0>; }; dummy_clock_gpu: gpu-clock@6 { compatible = "fixed-clock"; reg = <6>; /* Not address, just for index */ clock-frequency = <18000000>; clock-output-names = "dummy_clock_gpu"; #clock-cells = <0>; }; dummy_clock_dphy_ref: dphy-ref-clock@7 { compatible = "fixed-clock"; reg = <7>; /* Not address, just for index */ clock-frequency = <24000000>; clock-output-names = "dummy_clock_dphy_ref"; #clock-cells = <0>; }; dummy_clock_dphy_cfg: dphy-cfg-clock@8 { compatible = "fixed-clock"; reg = <8>; /* Not address, just for index */ clock-frequency = <24000000>; clock-output-names = "dummy_clock_dphy_cfg"; #clock-cells = <0>; }; dummy_clock_dpu_pixel0: dpu-pixel-clock@9 { compatible = "fixed-clock"; reg = <9>; clock-frequency = <72000000>; clock-output-names = "dummy_clock_dpu_pixel0"; #clock-cells = <0>; }; dummy_clock_dpu_pixel1: dpu-pixel-clock@10 { compatible = "fixed-clock"; reg = <10>; clock-frequency = <74250000>; clock-output-names = "dummy_clock_dpu_pixel1"; #clock-cells = <0>; }; osc_32k: clock-osc-32k@11 { compatible = "fixed-clock"; reg = <11>; #clock-cells = <0>; clock-frequency = <32768>; clock-output-names = "osc_32k"; }; osc_24m: clock-osc-24m@12 { compatible = "fixed-clock"; reg = <12>; #clock-cells = <0>; clock-frequency = <24000000>; clock-output-names = "osc_24m"; }; rc_24m: clock-rc-24m@13 { compatible = "fixed-clock"; reg = <13>; #clock-cells = <0>; clock-frequency = <24000000>; clock-output-names = "rc_24m"; }; dummy_clock_eip: eip-clock@14 { compatible = "fixed-clock"; reg = <14>; /* Not address, just for index */ clock-frequency = <400000000>; clock-output-names = "dummy_clock_eip"; #clock-cells = <0>; }; dummy_clock_spi: spi-clock@15 { compatible = "fixed-clock"; reg = <15>; /* Not address, just for index */ clock-frequency = <396000000>; clock-output-names = "dummy_clock_spi"; #clock-cells = <0>; }; dummy_clock_qspi: spi-clock@16 { compatible = "fixed-clock"; reg = <15>; /* Not address, just for index */ clock-frequency = <792000000>; clock-output-names = "dummy_clock_qspi"; #clock-cells = <0>; }; dummy_gmac_ahb: gmac-ahb-clock@16 { compatible = "fixed-clock"; reg = <16>; clock-frequency = <250000000>; clock-output-names = "dummy_gmac_ahb"; #clock-cells = <0>; }; dummy_clock_gmac: gmac-clock@17 { compatible = "fixed-clock"; reg = <17>; clock-frequency = <500000000>; clock-output-names = "dummy_clock_gmac"; #clock-cells = <0>; }; dummy_clock_sdhci: sdhci-clock@18 { compatible = "fixed-clock"; reg = <18>; /* Not address, just for index */ clock-frequency = <198000000>; clock-output-names = "dummy_clock_sdhci"; #clock-cells = <0>; }; dummy_clock_aonsys_clk: aonsys-clk-clock@19 { compatible = "fixed-clock"; reg = <19>; /* Not address, just for index */ clock-frequency = <73728000>; clock-output-names = "dummy_clock_aonsys_clk"; #clock-cells = <0>; }; dummy_clock_uart_sclk: uart-sclk-clock@20 { compatible = "fixed-clock"; reg = <20>; /* Not address, just for index */ clock-frequency = <100000000>; clock-output-names = "dummy_clock_uart_sclk"; #clock-cells = <0>; }; }; iso7816: iso7816-card@fff7f30000 { compatible = "thead,light-iso7816-card"; reg = <0xff 0xf7f30000 0x0 0x4000>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_iso7816>; interrupts = <69>; interrupt-parent = <&intc>; status = "disabled"; }; teesys_syscon: teesys-reg@ffff200000 { compatible = "syscon"; reg = <0xff 0xff200000 0x0 0x10000>; }; nvmem_controller: efuse@ffff210000 { compatible = "thead,light-fm-efuse", "syscon"; reg = <0xff 0xff210000 0x0 0x10000>; thead,teesys = <&teesys_syscon>; #address-cells = <1>; #size-cells = <1>; gmac0_mac_address: mac-address@176 { reg = <0xb0 6>; }; gmac1_mac_address: mac-address@184 { reg = <0xb8 6>; }; }; gpio0: gpio@ffec005000 { compatible = "snps,dw-apb-gpio"; reg = <0xff 0xec005000 0x0 0x1000>; #address-cells = <1>; #size-cells = <0>; gpio0_porta: gpio0-controller@0 { compatible = "snps,dw-apb-gpio-port"; gpio-controller; #gpio-cells = <2>; nr-gpios-snps = <32>; reg = <0>; interrupt-controller; #interrupt-cells = <2>; interrupt-parent = <&intc>; interrupts = <56>; }; }; gpio1: gpio@ffec006000 { compatible = "snps,dw-apb-gpio"; reg = <0xff 0xec006000 0x0 0x1000>; #address-cells = <1>; #size-cells = <0>; gpio1_porta: gpio1-controller@0 { compatible = "snps,dw-apb-gpio-port"; gpio-controller; #gpio-cells = <2>; nr-gpios-snps = <32>; reg = <0>; interrupt-controller; #interrupt-cells = <2>; interrupt-parent = <&intc>; interrupts = <57>; }; }; gpio2: gpio@ffe7f34000 { compatible = "snps,dw-apb-gpio"; reg = <0xff 0xe7f34000 0x0 0x1000>; #address-cells = <1>; #size-cells = <0>; gpio2_porta: gpio2-controller@0 { compatible = "snps,dw-apb-gpio-port"; gpio-controller; #gpio-cells = <2>; nr-gpios-snps = <32>; reg = <0>; interrupt-controller; #interrupt-cells = <2>; interrupt-parent = <&intc>; interrupts = <58>; }; }; gpio3: gpio@ffe7f38000 { compatible = "snps,dw-apb-gpio"; reg = <0xff 0xe7f38000 0x0 0x1000>; #address-cells = <1>; #size-cells = <0>; gpio3_porta: gpio3-controller@0 { compatible = "snps,dw-apb-gpio-port"; gpio-controller; #gpio-cells = <2>; nr-gpios-snps = <32>; reg = <0>; interrupt-controller; #interrupt-cells = <2>; interrupt-parent = <&intc>; interrupts = <59>; }; }; ao_gpio4: gpio@fffff52000 { compatible = "snps,dw-apb-gpio"; reg = <0xff 0xfff52000 0x0 0x1000>; #address-cells = <1>; #size-cells = <0>; ao_gpio4_porta: ao_gpio4-controller@0 { compatible = "snps,dw-apb-gpio-port"; gpio-controller; #gpio-cells = <2>; nr-gpios-snps = <32>; reg = <0>; interrupt-controller; #interrupt-cells = <2>; interrupt-parent = <&intc>; interrupts = <55>; }; }; ao_gpio: gpio@fffff41000 { compatible = "snps,dw-apb-gpio"; reg = <0xff 0xfff41000 0x0 0x1000>; #address-cells = <1>; #size-cells = <0>; ao_gpio_porta: ao_gpio-controller@0 { compatible = "snps,dw-apb-gpio-port"; gpio-controller; #gpio-cells = <2>; nr-gpios-snps = <32>; reg = <0>; interrupt-controller; #interrupt-cells = <2>; interrupt-parent = <&intc>; interrupts = <76>; }; }; padctrl1_apsys: pinctrl1-apsys@ffe7f3c000 { compatible = "thead,light-fm-left-pinctrl"; reg = <0xff 0xe7f3c000 0x0 0x1000>; status = "okay"; }; padctrl0_apsys: padctrl0-apsys@ffec007000 { compatible = "thead,light-fm-right-pinctrl"; reg = <0xff 0xec007000 0x0 0x1000>; status = "okay"; }; pwm: pwm@ffec01c000 { compatible = "thead,pwm-light"; reg = <0xff 0xec01c000 0x0 0x4000>; #pwm-cells = <2>; clocks = <&clk CLKGEN_PWM_PCLK>, <&clk CLKGEN_PWM_CCLK>; clock-names = "pclk", "cclk"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm>; }; timer0: timer@ffefc32000 { compatible = "snps,dw-apb-timer"; reg = <0xff 0xefc32000 0x0 0x14>; clocks = <&dummy_clock_apb>; clock-names = "timer"; clock-frequency = <62500000>; interrupts = <16>; interrupt-parent = <&intc>; status = "okay"; }; timer1: timer@ffefc32014 { compatible = "snps,dw-apb-timer"; reg = <0xff 0xefc32014 0x0 0x14>; clocks = <&dummy_clock_apb>; clock-names = "timer"; clock-frequency = <62500000>; interrupts = <17>; interrupt-parent = <&intc>; status = "okay"; }; timer2: timer@ffefc32028 { compatible = "snps,dw-apb-timer"; reg = <0xff 0xefc32028 0x0 0x14>; clocks = <&dummy_clock_apb>; clock-names = "timer"; clock-frequency = <62500000>; interrupts = <18>; interrupt-parent = <&intc>; status = "disabled"; }; timer3: timer@ffefc3203c { compatible = "snps,dw-apb-timer"; reg = <0xff 0xefc3203c 0x0 0x14>; clocks = <&dummy_clock_apb>; clock-names = "timer"; clock-frequency = <62500000>; interrupts = <19>; interrupt-parent = <&intc>; status = "disabled"; }; padctrl_aosys: padctrl-aosys@fffff4a000 { compatible = "thead,light-fm-aon-pinctrl"; reg = <0xff 0xfff4a000 0x0 0x2000>; status = "okay"; }; timer4: timer@ffffc33000 { compatible = "snps,dw-apb-timer"; reg = <0xff 0xffc33000 0x0 0x14>; clocks = <&dummy_clock_apb>; clock-names = "timer"; clock-frequency = <62500000>; interrupts = <20>; interrupt-parent = <&intc>; status = "disabled"; }; timer5: timer@ffffc33014 { compatible = "snps,dw-apb-timer"; reg = <0xff 0xffc33014 0x0 0x14>; clocks = <&dummy_clock_apb>; clock-names = "timer"; clock-frequency = <62500000>; interrupts = <21>; interrupt-parent = <&intc>; status = "disabled"; }; timer6: timer@ffffc33028 { compatible = "snps,dw-apb-timer"; reg = <0xff 0xffc33028 0x0 0x14>; clocks = <&dummy_clock_apb>; clock-names = "timer"; clock-frequency = <62500000>; interrupts = <22>; interrupt-parent = <&intc>; status = "disabled"; }; timer7: timer@ffffc3303c { compatible = "snps,dw-apb-timer"; reg = <0xff 0xffc3303c 0x0 0x14>; clocks = <&dummy_clock_apb>; clock-names = "timer"; clock-frequency = <62500000>; interrupts = <23>; interrupt-parent = <&intc>; status = "disabled"; }; uart0: serial@ffe7014000 { /* Normal serial, for C910 log */ compatible = "snps,dw-apb-uart"; reg = <0xff 0xe7014000 0x0 0x4000>; interrupt-parent = <&intc>; interrupts = <36>; clocks = <&clk CLKGEN_UART0_SCLK>; clock-names = "baudclk"; reg-shift = <2>; reg-io-width = <4>; hw-flow-control = "unsupport"; status = "okay"; }; uart1: serial@ffe7f00000 { /* Normal serial, for C902 log */ compatible = "snps,dw-apb-uart"; reg = <0xff 0xe7f00000 0x0 0x4000>; interrupt-parent = <&intc>; interrupts = <37>; clocks = <&clk CLKGEN_UART1_SCLK>; clock-names = "baudclk"; reg-shift = <2>; reg-io-width = <4>; hw-flow-control = "unsupport"; status = "okay"; }; uart2: serial@ffec010000 { /* IRDA supported serial, not in 85P bit */ compatible = "snps,dw-apb-uart"; reg = <0xff 0xec010000 0x0 0x4000>; interrupt-parent = <&intc>; interrupts = <38>; clocks = <&clk CLKGEN_UART2_SCLK>; clock-names = "baudclk"; reg-shift = <2>; reg-io-width = <4>; hw-flow-control = "unsupport"; status = "disabled"; }; uart3: serial@ffe7f04000 { /* IRDA supported serial, not in 85P bit */ compatible = "snps,dw-apb-uart"; reg = <0xff 0xe7f04000 0x0 0x4000>; interrupt-parent = <&intc>; interrupts = <39>; clocks = <&clk CLKGEN_UART3_SCLK>; clock-names = "baudclk"; reg-shift = <2>; reg-io-width = <4>; hw-flow-control = "unsupport"; status = "disabled"; }; uart4: serial@fff7f08000 { /* High Speed with Flow Ctrol serial */ compatible = "snps,dw-apb-uart"; reg = <0xff 0xf7f08000 0x0 0x4000>; interrupt-parent = <&intc>; interrupts = <40>; clocks = <&clk CLKGEN_UART4_SCLK>; clock-names = "baudclk"; reg-shift = <2>; reg-io-width = <4>; hw-flow-control = "support"; status = "okay"; }; uart5: serial@fff7f0c000 { /* Normal serial, for external SE, not in 85P bit */ compatible = "snps,dw-apb-uart"; reg = <0xff 0xf7f0c000 0x0 0x4000>; interrupt-parent = <&intc>; interrupts = <41>; clocks = <&clk CLKGEN_UART5_SCLK>; clock-names = "baudclk"; reg-shift = <2>; reg-io-width = <4>; hw-flow-control = "unsupport"; status = "disabled"; }; adc: adc@ffec020000 { compatible = "thead,light-adc"; reg = <0xff 0xfff51000 0x0 0x2000>; interrupt-parent = <&intc>; interrupts = <61>; clocks = <&dummy_clock_aonsys_clk>; clock-names = "adc"; /* ADC pin is proprietary,no need to config pinctrl */ status = "disabled"; }; spi0: spi@ffe700c000 { compatible = "snps,dw-apb-ssi"; reg = <0xff 0xe700c000 0x0 0x1000>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi0>; interrupt-parent = <&intc>; interrupts = <54>; clocks = <&dummy_clock_spi>; num-cs = <2>; #address-cells = <1>; #size-cells = <0>; }; qspi0: spi@ffea000000 { compatible = "snps,dw-apb-ssi-quad"; reg = <0xff 0xea000000 0x0 0x1000>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_qspi0>; interrupt-parent = <&intc>; interrupts = <52>; clocks = <&dummy_clock_qspi>; #address-cells = <1>; #size-cells = <0>; }; qspi1: spi@fff8000000 { compatible = "snps,dw-apb-ssi-quad"; reg = <0xff 0xf8000000 0x0 0x1000>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_qspi1>; interrupt-parent = <&intc>; interrupts = <53>; clocks = <&dummy_clock_spi>; #address-cells = <1>; #size-cells = <0>; }; g2d: gc620@ffecc80000 { compatible = "thead,c910-gc620"; reg = <0xff 0xecc80000 0x0 0x40000>; interrupt-parent = <&intc>; interrupts = <101>; interrupt-names = "irq_2d"; status = "okay"; }; dsi0: dw-mipi-dsi@ffef500000 { compatible = "thead,light-mipi-dsi", "simple-bus", "syscon"; reg = <0xff 0xef500000 0x0 0x10000>; status = "disabled"; dphy_0: dsi0-dphy { compatible = "thead,light-mipi-dphy"; regmap = <&dsi0>; vosys-regmap = <&vosys_reg>; clocks = <&dummy_clock_dphy_ref>, <&dummy_clock_dphy_cfg>, <&dummy_clock_apb>; clock-names = "refclk", "cfgclk", "pclk"; #phy-cells = <0>; }; dhost_0: dsi0-host { compatible = "verisilicon,dw-mipi-dsi"; regmap = <&dsi0>; interrupt-parent = <&intc>; interrupts = <129>; clocks = <&dummy_clock_dphy_ref>, <&dummy_clock_apb>; clock-names = "ref", "pclk"; phys = <&dphy_0>; phy-names = "dphy"; #address-cells = <1>; #size-cells = <0>; }; }; dsi1: dw-mipi-dsi@ffef510000 { compatible = "thead,light-mipi-dsi", "simple-bus", "syscon"; reg = <0xff 0xef510000 0x0 0x10000>; status = "disabled"; dphy_1: dsi1-dphy { compatible = "thead,light-mipi-dphy"; regmap = <&dsi1>; vosys-regmap = <&vosys_reg>; clocks = <&dummy_clock_dphy_ref>, <&dummy_clock_dphy_cfg>, <&dummy_clock_apb>; clock-names = "refclk", "cfgclk", "pclk"; #phy-cells = <0>; }; dhost_1: dsi1-host { compatible = "verisilicon,dw-mipi-dsi"; regmap = <&dsi1>; interrupt-parent = <&intc>; interrupts = <129>; clocks = <&dummy_clock_dphy_ref>, <&dummy_clock_apb>; clock-names = "ref", "pclk"; phys = <&dphy_1>; phy-names = "dphy"; #address-cells = <1>; #size-cells = <0>; }; }; vosys_reg: vosys@ffef528000 { compatible = "thead,light-vo-subsys", "syscon"; reg = <0xff 0xef528000 0x0 0x1000>; status = "okay"; }; hdmi_tx: dw-hdmi-tx@ffef540000 { compatible = "thead,light-hdmi-tx"; reg = <0xff 0xef540000 0x0 0x40000>; interrupt-parent = <&intc>; interrupts = <111>; clocks = <&dummy_clock_apb>, <&dummy_clock_dphy_ref>; clock-names = "iahb", "isfr"; reg-io-width = <4>; phy_version = <301>; /* TODO: add phy property */ status = "disabled"; }; dpu: dc8200@ffef600000 { compatible = "verisilicon,dc8200"; #address-cells = <1>; #size-cells = <0>; reg = <0xff 0xef600000 0x0 0x100>, <0xff 0xef600800 0x0 0x2000>, <0xff 0xef630010 0x0 0x60>; interrupt-parent = <&intc>; interrupts = <93>; clocks = <&dummy_clock_apb>, <&clk DPU0_PLL_DIV_CLK>, <&clk DPU1_PLL_DIV_CLK>, <&dummy_clock_ahb>; clock-names = "core_clk", "pix_clk0", "pix_clk1", "axi_clk"; status = "disabled"; dpu_disp0: port@0 { reg = <0>; disp0_out: endpoint { remote-endpoint = <&enc0_in>; }; }; dpu_disp1: port@1 { reg = <1>; disp1_out: endpoint { remote-endpoint = <&enc1_in>; }; }; }; watchdog0: watchdog@ffefc30000 { compatible = "snps,dw-wdt"; reg = <0xff 0xefc30000 0x0 0x1000>; interrupt-parent = <&intc>; interrupts = <24>; clocks = <&dummy_clock_apb>; clock-names = "baudclk"; status = "okay"; }; watchdog1: watchdog@ffefc31000 { compatible = "snps,dw-wdt"; reg = <0xff 0xefc31000 0x0 0x1000>; interrupt-parent = <&intc>; interrupts = <25>; clocks = <&dummy_clock_apb>; clock-names = "baudclk"; status = "okay"; }; rtc: rtc@fffff40000 { compatible = "apm,xgene-rtc"; reg = <0xff 0xfff40000 0x0 0x1000>; interrupt-parent = <&intc>; interrupts = <74>; clocks = <&dummy_clock_rtc>; clock-names = "rtc"; status = "okay"; }; usb: dwc3@ffe7040000 { compatible = "snps,dwc3"; reg = <0xff 0xe7040000 0x0 0x10000>; interrupt-parent = <&intc>; interrupts = <68>; clocks = <&dummy_clock_ref>, <&dummy_clock_apb>, <&dummy_clock_suspend>; clock-names = "ref", "bus_early", "suspend"; reg-shift = <2>; reg-io-width = <4>; maximum-speed = "super-speed"; dr_mode = "host"; dma-mask = <0xf 0xffffffff>; snps,usb3_lpm_capable; snps,dis_u3_susphy_quirk; status = "okay"; }; pmu: pmu@0 { compatible = "riscv,c910_pmu"; reg = <0 0 0 0>; /* Not address, just for index */ }; clk: clock-controller@ffef010000 { compatible = "thead,light-fm-ree-clk"; reg = <0xff 0xef010000 0x0 0x1000>; #clock-cells = <1>; clocks = <&osc_32k>, <&osc_24m>, <&rc_24m>; clock-names = "osc_32k", "osc_24m", "rc_24m"; status = "okay"; }; sys_reg: sys_reg@ffef010100 { compatible = "thead,light_sys_reg"; reg = <0xff 0xef010100 0x0 0x100>; status = "okay"; }; dmac0: dmac@ffefc00000 { compatible = "snps,axi-dma-1.01a"; reg = <0xff 0xefc00000 0x0 0x1000>; interrupt-parent = <&intc>; interrupts = <27>; clocks = <&dummy_clock_apb>, <&dummy_clock_apb>; clock-names = "core-clk", "cfgr-clk"; #dma-cells = <1>; dma-channels = <4>; snps,block-size = <65536 65536 65536 65536>; snps,priority = <0 1 2 3>; snps,dma-masters = <1>; snps,data-width = <4>; snps,axi-max-burst-len = <16>; status = "okay"; }; dmac1: tee_dmac@ffff340000 { compatible = "snps,axi-dma-1.01a"; reg = <0xff 0xff340000 0x0 0x1000>; interrupt-parent = <&intc>; interrupts = <150>; clocks = <&dummy_clock_apb>, <&dummy_clock_apb>; clock-names = "core-clk", "cfgr-clk"; #dma-cells = <1>; dma-channels = <4>; snps,block-size = <65536 65536 65536 65536>; snps,priority = <0 1 2 3>; snps,dma-masters = <1>; snps,data-width = <4>; snps,axi-max-burst-len = <16>; status = "okay"; }; stmmac_axi_setup: stmmac-axi-config { snps,wr_osr_lmt = <3>; snps,rd_osr_lmt = <3>; snps,blen = <16 8 4 0 0 0 0>; }; gmac0: ethernet@ffe7070000 { compatible = "thead,light-dwmac"; reg = <0xff 0xe7070000 0x0 0x2000 0xff 0xec00301c 0x0 0x4 0xff 0xec003020 0x0 0x4 0xff 0xec003000 0x0 0x1c>; reg-names = "gmac", "phy_if_reg", "txclk_dir_reg", "clk_mgr_reg"; interrupt-parent = <&intc>; interrupts = <66>; interrupt-names = "macirq"; clocks = <&clk CLKGEN_GMAC0_HCLK>, <&clk CLKGEN_GMAC0_CCLK>; clock-names = "stmmaceth", "gmac_pll_clk"; snps,pbl = <32>; snps,fixed-burst; snps,axi-config = <&stmmac_axi_setup>; nvmem-cells = <&gmac0_mac_address>; nvmem-cell-names = "mac-address"; }; gmac1: ethernet@ffe7060000 { compatible = "thead,light-dwmac"; reg = <0xff 0xe7060000 0x0 0x2000 0xff 0xec00401c 0x0 0x4 0xff 0xec004020 0x0 0x4 0xff 0xec004000 0x0 0x1c>; reg-names = "gmac", "phy_if_reg", "txclk_dir_reg", "clk_mgr_reg"; interrupt-parent = <&intc>; interrupts = <67>; interrupt-names = "macirq"; clocks = <&clk CLKGEN_GMAC1_HCLK>, <&clk CLKGEN_GMAC1_CCLK>; clock-names = "stmmaceth", "gmac_pll_clk"; snps,pbl = <32>; snps,fixed-burst; snps,axi-config = <&stmmac_axi_setup>; nvmem-cells = <&gmac1_mac_address>; nvmem-cell-names = "mac-address"; }; emmc: sdhci@ffe7080000 { compatible = "snps,dwcmshc-sdhci"; reg = <0xff 0xe7080000 0x0 0x10000 0xff 0xef014060 0x0 0x4>; interrupt-parent = <&intc>; interrupts = <62>; interrupt-names = "sdhciirq"; clocks = <&dummy_clock_sdhci>; clock-names = "core"; }; sdhci0: sd@ffe7090000 { compatible = "snps,dwcmshc-sdhci"; reg = <0xff 0xe7090000 0x0 0x10000 0xff 0xef014064 0x0 0x4>; interrupt-parent = <&intc>; interrupts = <64>; interrupt-names = "sdhci0irq"; clocks = <&dummy_clock_sdhci>; clock-names = "core"; }; sdhci1: sd@ffe70a0000 { compatible = "snps,dwcmshc-sdhci"; reg = <0xff 0xe70a0000 0x0 0x10000 0xff 0xef014064 0x0 0x4>; interrupt-parent = <&intc>; interrupts = <71>; interrupt-names = "sdhci1irq"; clocks = <&dummy_clock_sdhci>; clock-names = "core"; }; hwspinlock: hwspinlock@ffefc10000 { compatible = "light,hwspinlock"; reg = <0xff 0xefc10000 0x0 0x10000>; status = "disabled"; }; npu: vha@fffc800000 { compatible = "img,ax3386-nna"; reg = <0xff 0xfc800000 0x0 0x100000>; interrupt-parent = <&intc>; interrupts = <113>; interrupt-names = "npuirq"; clocks = <&dummy_clock_npu>; clock-names = "dummy_clock_npu"; vha_clk_rate = <24000000>; ldo_vha-supply = <&npu>; dma-mask = <0xf 0xffffffff>; status = "disabled"; }; gpu: gpu@ffef400000 { compatible = "img,gpu"; reg = <0xff 0xef400000 0x0 0x100000>; interrupt-parent = <&intc>; interrupts = <102>; interrupt-names = "gpuirq"; clocks = <&dummy_clock_gpu>; clock-names = "dummy_clock_gpu"; gpu_clk_rate = <18000000>; dma-mask = <0xf 0xffffffff>; status = "disabled"; }; fce: fce@fffcc50000 { compatible = "thead,light-fce"; reg = <0xff 0xfcc50000 0x0 0x10000>; interrupt-parent = <&intc>; interrupts = <100>; interrupt-names = "fceirq"; dma-mask = <0xf 0xffffffff>; status = "disabled"; }; vdec: vdec@ffecc00000 { compatible = "thead,light-vc8000d"; reg = <0xff 0xecc00000 0x0 0x8000>; interrupt-parent = <&intc>; interrupts = <131>; status = "disabled"; }; venc: venc@ffecc10000 { compatible = "thead,light-vc8000e"; reg = <0xff 0xecc10000 0x0 0x8000>; interrupt-parent = <&intc>; interrupts = <133>; status = "disabled"; }; isp_venc_shake: shake@ffe4078000 { compatible = "thead,light-ivs"; reg = <0xff 0xe4078000 0x0 0x1000>; interrupt-parent = <&intc>; interrupts = <158>; status = "disabled"; }; vidmem: vidmem@ffecc08000 { compatible = "thead,light-vidmem"; reg = <0xff 0xecc08000 0x0 0x1000>; status = "disabled"; }; light_i2s: light_i2s@ffe7034000 { #sound-dai-cells = <1>; compatible = "light,light-i2s"; reg = <0xff 0xe7034000 0x0 0x4000>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_audio_i2s0>; light,mode = "i2s-master"; interrupt-parent = <&intc>; interrupts = <70>; dmas = <&dmac0 35>, <&dmac0 39>; dma-names = "tx", "rx"; light,dma_maxburst = <4>; #dma-cells = <1>; clocks = <&dummy_clock_apb>; clock-names = "pclk"; status = "disabled"; }; i2c0: i2c@ffe7f20000 { compatible = "snps,designware-i2c"; reg = <0xff 0xe7f20000 0x0 0x4000>; interrupt-parent = <&intc>; interrupts = <44>; clocks = <&dummy_clock_apb>; clock-frequency = <100000>; ss_hcnt = /bits/ 16 <0x104>; ss_lcnt = /bits/ 16 <0xec>; fs_hcnt = /bits/ 16 <0x37>; fs_lcnt = /bits/ 16 <0x42>; fp_hcnt = /bits/ 16 <0x14>; fp_lcnt = /bits/ 16 <0x1a>; hs_hcnt = /bits/ 16 <0x2>; hs_lcnt = /bits/ 16 <0x7>; #address-cells = <1>; #size-cells = <0>; }; i2c1: i2c@ffe7f24000 { compatible = "snps,designware-i2c"; reg = <0xff 0xe7f24000 0x0 0x4000>; interrupt-parent = <&intc>; interrupts = <45>; clocks = <&dummy_clock_apb>; clock-frequency = <100000>; ss_hcnt = /bits/ 16 <0x104>; ss_lcnt = /bits/ 16 <0xec>; fs_hcnt = /bits/ 16 <0x37>; fs_lcnt = /bits/ 16 <0x42>; fp_hcnt = /bits/ 16 <0x14>; fp_lcnt = /bits/ 16 <0x1a>; hs_hcnt = /bits/ 16 <0x2>; hs_lcnt = /bits/ 16 <0x6>; #address-cells = <1>; #size-cells = <0>; }; i2c2: i2c@ffec00c000{ compatible = "snps,designware-i2c"; reg = <0xff 0xec00c000 0x0 0x4000>; interrupt-parent = <&intc>; interrupts = <46>; clocks = <&dummy_clock_apb>; clock-frequency = <100000>; ss_hcnt = /bits/ 16 <0x104>; ss_lcnt = /bits/ 16 <0xec>; fs_hcnt = /bits/ 16 <0x37>; fs_lcnt = /bits/ 16 <0x42>; fp_hcnt = /bits/ 16 <0x14>; fp_lcnt = /bits/ 16 <0x1a>; hs_hcnt = /bits/ 16 <0x2>; hs_lcnt = /bits/ 16 <0x7>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; }; i2c3: i2c@ffec014000{ compatible = "snps,designware-i2c"; reg = <0xff 0xec014000 0x0 0x4000>; interrupt-parent = <&intc>; interrupts = <47>; clocks = <&dummy_clock_apb>; clock-frequency = <100000>; ss_hcnt = /bits/ 16 <0x104>; ss_lcnt = /bits/ 16 <0xec>; fs_hcnt = /bits/ 16 <0x37>; fs_lcnt = /bits/ 16 <0x42>; fp_hcnt = /bits/ 16 <0x14>; fp_lcnt = /bits/ 16 <0x1a>; hs_hcnt = /bits/ 16 <0x2>; hs_lcnt = /bits/ 16 <0x7>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; }; i2c4: i2c@ffe7f28000{ compatible = "snps,designware-i2c"; reg = <0xff 0xe7f28000 0x0 0x4000>; interrupt-parent = <&intc>; interrupts = <48>; clocks = <&dummy_clock_apb>; clock-frequency = <100000>; ss_hcnt = /bits/ 16 <0x104>; ss_lcnt = /bits/ 16 <0xec>; fs_hcnt = /bits/ 16 <0x37>; fs_lcnt = /bits/ 16 <0x42>; fp_hcnt = /bits/ 16 <0x14>; fp_lcnt = /bits/ 16 <0x1a>; hs_hcnt = /bits/ 16 <0x2>; hs_lcnt = /bits/ 16 <0x7>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; }; isp0: isp@ffe4100000 { compatible = "thead,light-isp"; reg = <0xff 0xe4100000 0x0 0x10000>; interrupt-parent = <&intc>; interrupts = <117>,<118>; status = "disabled"; }; isp1: isp@ffe4110000 { compatible = "thead,light-isp"; reg = <0xff 0xe4110000 0x0 0x10000>; interrupt-parent = <&intc>; interrupts = <120>,<121>; status = "disabled"; }; isp_ry0: isp_ry@ffe4120000 { compatible = "thead,light-isp_ry"; reg = <0xff 0xe4120000 0x0 0x10000>; interrupt-parent = <&intc>; interrupts = <123>,<124>; status = "disabled"; }; dewarp: dewarp@ffe4130000 { compatible = "thead,light-dewarp"; reg = <0xff 0xe4130000 0x0 0x10000>; interrupt-parent = <&intc>; interrupts = <98>,<99>; status = "disabled"; }; dec400_isp0: dec400@ffe4060000 { compatible = "thead,dec400"; reg = <0xff 0xe4060000 0x0 0x8000>; status = "disabled"; }; dec400_isp1: dec400@ffe4068000 { compatible = "thead,dec400"; reg = <0xff 0xe4068000 0x0 0x8000>; status = "disabled"; }; dec400_isp2: dec400@ffe4070000 { compatible = "thead,dec400"; reg = <0xff 0xe4070000 0x0 0x8000>; status = "disabled"; }; bm_visys: bm_visys@ffe4040000 { compatible = "thead,light-bm-visys"; reg = <0xff 0xe4040000 0x0 0x1000>; status = "disabled"; }; bm_csi0: csi@ffe4000000{ //CSI2 compatible = "thead,light-bm-csi"; reg = < 0xff 0xe4000000 0x0 0x10000>; interrupt-parent = <&intc>; interrupts = <128>; dphyglueiftester = <0x180>; sysreg_mipi_csi_ctrl = <0x140>; status = "disabled"; }; bm_csi1: csi@ffe4010000{ //CSI2X2_B compatible = "thead,light-bm-csi"; reg = < 0xff 0xe4010000 0x0 0x10000>; interrupt-parent = <&intc>; interrupts = <126>; // 110 + 16 int_mipi_csi2x2_int0 dphyglueiftester = <0x182>; // for FPGA PHY only. ASIC not needed. sysreg_mipi_csi_ctrl = <0x148>; status = "disabled"; }; bm_csi2: csi@ffe4020000{ //CSI2X2_A compatible = "thead,light-bm-csi"; reg = < 0xff 0xe4020000 0x0 0x10000>; interrupt-parent = <&intc>; interrupts = <127>; dphyglueiftester = <0x184>; sysreg_mipi_csi_ctrl = <0x144>; status = "disabled"; }; bm_isp0: bm_isp@ffe4100000 { compatible = "thead,light-bm-isp"; reg = <0xff 0xe4100000 0x0 0x10000>; status = "disabled"; }; bm_isp1: bm_isp@ffe4110000 { compatible = "thead,light-bm-isp"; reg = <0xff 0xe4110000 0x0 0x10000>; status = "disabled"; }; //isp-ry bm_isp2: bm_isp@ffe4120000 { compatible = "thead,light-bm-isp"; reg = <0xff 0xe4120000 0x0 0x10000>; status = "disabled"; }; vi_pre: vi_pre@ffe4030000 { compatible = "thead,vi_pre"; reg = <0xff 0xe4030000 0x0 0x1000>; interrupt-parent = <&intc>; interrupts = <134>; status = "disabled"; }; video0: cam_dev@100 { compatible = "thead,video"; status = "disabled"; }; video1: cam_dev@200 { compatible = "thead,video"; status = "disabled"; }; video2: cam_dev@300 { compatible = "thead,video"; status = "disabled"; }; vvcam_sensor0: vvcam_sensor@0 { compatible = "thead,light-vvcam-sensor"; status = "disabled"; }; vvcam_sensor1: vvcam_sensor@1 { compatible = "thead,light-vvcam-sensor"; status = "disabled"; }; vvcam_sensor2: vvcam_sensor@2 { compatible = "thead,light-vvcam-sensor"; status = "disabled"; }; vvcam_sensor3: vvcam_sensor@3 { compatible = "thead,light-vvcam-sensor"; status = "disabled"; }; vvcam_sensor4: vvcam_sensor@4 { compatible = "thead,light-vvcam-sensor"; status = "disabled"; }; vvcam_sensor5: vvcam_sensor@5 { compatible = "thead,light-vvcam-sensor"; status = "disabled"; }; vvcam_sensor6: vvcam_sensor@6 { compatible = "thead,light-vvcam-sensor"; status = "disabled"; }; xtensa_dsp: dsp@01{ compatible = "thead,dsp-hw-common"; reg = <0xff 0xef040000 0x0 0x001000 >; /*DSP_SYSREG(0x0000-0xFFF) */ status = "disabled"; }; xtensa_dsp0: dsp@0 { compatible = "cdns,xrp-hw-simple"; reg = <0xff 0xe4040190 0x0 0x000010 /* host irq DSP->CPU INT Register */ 0xff 0xe40401e0 0x0 0x000010 /* device irq CPU->DSP INT Register */ 0xff 0xef048000 0x0 0x008000 /*DSP_APB(0x0000-0xFFF) */ 0x00 0x90000000 0x0 0x00001000 /* DSP communication area */ 0x0 0x90001000 0x0 0x00fff000>; /* DSP shared memory */ dsp = <0>; dspsys-rst-bit = <8>; /*bit# in DSP_SYSREG*/ dspsys-bus-offset = <0x90>; /*in DSP_SYSREG*/ device-irq = <0x4 1 24>; /*0xff 0xe40401e4 offset to clear DSP I]RQ, bit#, IRQ# */ device-irq-host-offset = <0x8>; /*0xff 0xe40401e8 offset to trigger DSP IRQ*/ device-irq-mode = <1>; /*level trigger*/ host-irq = <0x4 1>; /*0xff 0xe4040194 offset to clear, bit# */ host-irq-mode = <1>; /*level trigger */ host-irq-offset = <0x8>; /* 0xff 0xe4040198 offset to trigger ,device side*/ interrupt-parent = <&intc>; interrupts = <156>; firmware-name = "xrp0.elf"; status = "disabled"; #address-cells = <2>; #size-cells = <1>; ranges = <0x00 0x70000000 0x00 0x70000000 0x40000000 0x00 0xfa000000 0xff 0xe0000000 0x00180000 0x00 0xe0180000 0xff 0xe0180000 0x00040000 0x00 0xffc00000 0xff 0xe4000000 0x00200000 >; /* VISYS_R */ dsp@0 { ranges = <0x00 0x70000000 0x00 0x70000000 0x40000000 0x00 0xfa000000 0xff 0xe0000000 0x00180000 0x00 0xe0180000 0xff 0xe0180000 0x00040000 0x00 0xffc00000 0xff 0xe4000000 0x00200000 >; /* VISYS_R */ }; }; xtensa_dsp1: dsp@1 { compatible = "cdns,xrp-hw-simple"; reg = <0xff 0xe40401a0 0x0 0x000010 /* host irq DSP->CPU INT Register */ 0xff 0xe40401d0 0x0 0x000010 /* device irq CPU->DSP INT Register */ 0xff 0xef050000 0x0 0x008000 /*DSP_APB(0x0000-0xFFF) */ 0x00 0xa0000000 0x0 0x00001000 /* DSP communication area */ 0x0 0xa0001000 0x0 0x00fff000>; /* DSP shared memory */ dsp = <1>; dspsys-rst-bit = <8>; /*bit# in DSP_SYSREG*/ dspsys-bus-offset = <0x90>; /*in DSP_SYSREG*/ device-irq = <0x4 1 24>; /*0xff 0xe40401e4 offset to clear DSP I]RQ, bit#, IRQ# */ device-irq-host-offset = <0x8>; /*0xff 0xe40401e8 offset to trigger DSP IRQ*/ device-irq-mode = <1>; /*level trigger*/ host-irq = <0x4 1>; /*0xff 0xe4040194 offset to clear, bit# */ host-irq-mode = <1>; /*level trigger */ host-irq-offset = <0x8>; /* 0xff 0xe4040198 offset to trigger ,device side*/ interrupt-parent = <&intc>; interrupts = <157>; firmware-name = "xrp1.elf"; status = "disabled"; #address-cells = <2>; #size-cells = <1>; ranges = <0x00 0x70000000 0x00 0x70000000 0x40000000 0x00 0xfa000000 0xff 0xe0000000 0x00180000 0x00 0xe0180000 0xff 0xe01C0000 0x00040000 0x00 0xffc00000 0xff 0xe4000000 0x00200000 >; /* VISYS_R */ dsp@0 { ranges = <0x00 0x70000000 0x00 0x70000000 0x40000000 0x00 0xfa000000 0xff 0xe0000000 0x00180000 0x00 0xe0180000 0xff 0xe01C0000 0x00040000 0x00 0xffc00000 0xff 0xe4000000 0x00200000 >; /* VISYS_R */ }; }; pmp: pmp@ffdc020000 { compatible = "pmp"; reg = <0xff 0xdc020000 0x0 0x1000>; }; mrvbr: mrvbr@ffff018050 { compatible = "mrvbr"; reg = <0xff 0xff019050 0x0 0x1000>; }; mrmr: mrmr@ffff014004 { compatible = "mrmr"; reg = <0xff 0xff015004 0x0 0x1000>; }; bmu: ddr-pmu@ffff008000 { compatible = "thead,light-ddr-pmu"; reg = <0xff 0xff008000 0x0 0x800 0xff 0xff008800 0x0 0x800 0xff 0xff009000 0x0 0x800 0xff 0xff009800 0x0 0x800 0xff 0xff00a000 0x0 0x800>; interrupt-parent = <&intc>; interrupts = <87>; status = "okay"; }; mbox_910t: mbox@ffffc38000 { compatible = "thead,light-mbox"; reg = <0xff 0xffc38000 0x0 0x4000>, <0xff 0xffc44000 0x0 0x1000>, <0xff 0xffc4c000 0x0 0x1000>, <0xff 0xffc54000 0x0 0x1000>; reg-names = "local_base", "remote_icu0", "remote_icu1", "remote_icu2"; interrupt-parent = <&intc>; interrupts = <28>; clocks = <&dummy_clock_apb>; clock-names = "ipg"; icu_cpu_id = <0>; #mbox-cells = <2>; }; trng: rng@ffff300000 { compatible = "inside-secure,safexcel-eip76"; reg = <0xff 0xff300000 0x0 0x7d>; interrupt-parent = <&intc>; interrupts = <149>; clocks = <&dummy_clock_eip>; status = "disabled"; }; eip_28: eip-28@ffff300000 { compatible = "xlnx,sunrise-fpga-1.0", "safexcel-eip-28"; reg = <0xff 0xff300000 0x0 0x40000>; interrupt-parent = <&intc>; interrupts = <144>,<145>,<146>,<147>; clocks = <&dummy_clock_eip>; status = "disabled"; }; }; aon { compatible = "thead,light-aon"; mbox-names = "aon"; mboxes = <&mbox_910t 1 0>; status = "okay"; pd: light-aon-pd { compatible = "thead,light-aon-pd"; #power-domain-cells = <1>; }; soc_dovdd18_scan_reg: soc_dovdd18_scan { compatible = "regulator-fixed"; regulator-name = "soc_dovdd18_scan"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; gpio = <&gpio0_porta 10 1>; enable-active-high; regulator-always-on; }; soc_vext_2v8_reg: soc_vext_2v8 { compatible = "regulator-fixed"; regulator-name = "soc_vext_2v8"; regulator-min-microvolt = <2800000>; regulator-max-microvolt = <2800000>; gpio = <&gpio1_porta 7 1>; enable-active-high; regulator-always-on; }; soc_dvdd12_scan_reg: soc_dvdd12_scan { compatible = "regulator-fixed"; regulator-name = "soc_dvdd12_scan"; regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1200000>; gpio = <&gpio0_porta 11 1>; enable-active-high; regulator-always-on; }; soc_avdd28_scan_en_reg: soc_avdd28_scan_en { compatible = "regulator-fixed"; regulator-name = "soc_avdd28_scan_en"; regulator-min-microvolt = <2800000>; regulator-max-microvolt = <2800000>; gpio = <&ao_gpio_porta 14 1>; enable-active-high; regulator-always-on; }; soc_avdd28_rgb_reg: soc_avdd28_rgb { compatible = "regulator-fixed"; regulator-name = "soc_avdd28_rgb"; regulator-min-microvolt = <2800000>; regulator-max-microvolt = <2800000>; gpio = <&gpio1_porta 24 1>; enable-active-high; regulator-always-on; }; soc_dovdd18_rgb_reg: soc_dovdd18_rgb { compatible = "regulator-fixed"; regulator-name = "soc_dovdd18_rgb"; regulator-min-microvolt = <2800000>; regulator-max-microvolt = <2800000>; gpio = <&gpio1_porta 22 1>; enable-active-high; regulator-always-on; }; soc_dvdd12_rgb_reg: soc_dvdd12_rgb { compatible = "regulator-fixed"; regulator-name = "soc_dvdd12_rgb"; regulator-min-microvolt = <2800000>; regulator-max-microvolt = <2800000>; gpio = <&gpio1_porta 23 1>; enable-active-high; regulator-always-on; }; soc_avdd25_ir_reg: soc_avdd25_ir { compatible = "regulator-fixed"; regulator-name = "soc_avdd25_ir"; regulator-min-microvolt = <2800000>; regulator-max-microvolt = <2800000>; gpio = <&gpio1_porta 7 1>; enable-active-high; regulator-always-on; }; soc_dovdd18_ir_reg: soc_dovdd18_ir { compatible = "regulator-fixed"; regulator-name = "soc_dovdd18_ir"; regulator-min-microvolt = <2800000>; regulator-max-microvolt = <2800000>; gpio = <&gpio1_porta 7 1>; enable-active-high; regulator-always-on; }; soc_dvdd12_ir_reg: soc_dvdd12_ir { compatible = "regulator-fixed"; regulator-name = "soc_dvdd12_ir"; regulator-min-microvolt = <2800000>; regulator-max-microvolt = <2800000>; gpio = <&gpio1_porta 7 1>; enable-active-high; regulator-always-on; }; aon_reg_ricoh: light-ricoh-reg { compatible = "thead,light-ricoh-pmic"; status = "okay"; dvdd_cpu_reg: appcpu_dvdd { regulator-name = "appcpu_dvdd"; regulator-min-microvolt = <600000>; regulator-max-microvolt = <1500000>; regulator-boot-on; regulator-always-on; }; dvddm_cpu_reg: appcpu_dvddm { regulator-name = "appcpu_dvddm"; regulator-min-microvolt = <600000>; regulator-max-microvolt = <1500000>; regulator-boot-on; regulator-always-on; }; soc_dvdd18_aon_reg: soc_dvdd18_aon { regulator-name = "soc_dvdd18_aon"; regulator-boot-on; regulator-always-on; }; soc_avdd33_usb3_reg: soc_avdd33_usb3 { regulator-name = "soc_avdd33_usb3"; regulator-boot-on; regulator-always-on; }; soc_dvdd08_aon_reg: soc_dvdd08_aon { regulator-name = "soc_dvdd08_aon"; regulator-boot-on; regulator-always-on; }; soc_dvdd08_ddr_reg: soc_dvdd08_ddr { regulator-name = "soc_dvdd08_ddr"; regulator-boot-on; regulator-always-on; }; soc_vdd_ddr_1v8_reg: soc_vdd_ddr_1v8 { regulator-name = "soc_vdd_ddr_1v8"; regulator-boot-on; regulator-always-on; }; soc_vdd_ddr_1v1_reg: soc_vdd_ddr_1v1 { regulator-name = "soc_vdd_ddr_1v1"; regulator-boot-on; regulator-always-on; }; soc_vdd_ddr_0v6_reg: soc_vdd_ddr_0v6 { regulator-name = "soc_vdd_ddr_0v6"; regulator-boot-on; regulator-always-on; }; soc_dvdd18_ap_reg: soc_dvdd18_ap { regulator-name = "soc_dvdd18_ap"; regulator-boot-on; regulator-always-on; }; soc_dvdd08_ap_reg: soc_dvdd08_ap { regulator-name = "soc_dvdd08_ap"; regulator-boot-on; regulator-always-on; }; soc_avdd08_mipi_hdmi_reg: soc_avdd08_mipi_hdmi { regulator-name = "soc_avdd08_mipi_hdmi"; regulator-boot-on; regulator-always-on; }; soc_avdd18_mipi_hdmi_reg: soc_avdd18_mipi_hdmi { regulator-name = "soc_avdd18_mipi_hdmi"; regulator-boot-on; regulator-always-on; }; soc_vdd33_emmc_reg: soc_vdd33_emmc { regulator-name = "soc_vdd33_emmc"; regulator-boot-on; regulator-always-on; }; soc_vdd18_emmc_reg: soc_vdd18_emmc { regulator-name = "soc_vdd18_emmc"; regulator-boot-on; regulator-always-on; }; }; c910_cpufreq { compatible = "thead,light-mpw-cpufreq"; status = "okay"; }; test: light-aon-test { compatible = "thead,light-aon-test"; }; }; };