ehci-mx6.c 16 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
  4. * Copyright (C) 2010 Freescale Semiconductor, Inc.
  5. */
  6. #include <common.h>
  7. #include <log.h>
  8. #include <usb.h>
  9. #include <errno.h>
  10. #include <wait_bit.h>
  11. #include <linux/compiler.h>
  12. #include <linux/delay.h>
  13. #include <usb/ehci-ci.h>
  14. #include <asm/io.h>
  15. #include <asm/arch/imx-regs.h>
  16. #include <asm/arch/clock.h>
  17. #include <asm/mach-imx/iomux-v3.h>
  18. #include <asm/mach-imx/sys_proto.h>
  19. #include <dm.h>
  20. #include <asm/mach-types.h>
  21. #include <power/regulator.h>
  22. #include <linux/usb/otg.h>
  23. #include "ehci.h"
  24. DECLARE_GLOBAL_DATA_PTR;
  25. #define USB_OTGREGS_OFFSET 0x000
  26. #define USB_H1REGS_OFFSET 0x200
  27. #define USB_H2REGS_OFFSET 0x400
  28. #define USB_H3REGS_OFFSET 0x600
  29. #define USB_OTHERREGS_OFFSET 0x800
  30. #define USB_H1_CTRL_OFFSET 0x04
  31. #define USBPHY_CTRL 0x00000030
  32. #define USBPHY_CTRL_SET 0x00000034
  33. #define USBPHY_CTRL_CLR 0x00000038
  34. #define USBPHY_CTRL_TOG 0x0000003c
  35. #define USBPHY_PWD 0x00000000
  36. #define USBPHY_CTRL_SFTRST 0x80000000
  37. #define USBPHY_CTRL_CLKGATE 0x40000000
  38. #define USBPHY_CTRL_ENUTMILEVEL3 0x00008000
  39. #define USBPHY_CTRL_ENUTMILEVEL2 0x00004000
  40. #define USBPHY_CTRL_OTG_ID 0x08000000
  41. #define ANADIG_USB2_CHRG_DETECT_EN_B 0x00100000
  42. #define ANADIG_USB2_CHRG_DETECT_CHK_CHRG_B 0x00080000
  43. #define ANADIG_USB2_PLL_480_CTRL_BYPASS 0x00010000
  44. #define ANADIG_USB2_PLL_480_CTRL_ENABLE 0x00002000
  45. #define ANADIG_USB2_PLL_480_CTRL_POWER 0x00001000
  46. #define ANADIG_USB2_PLL_480_CTRL_EN_USB_CLKS 0x00000040
  47. #define USBNC_OFFSET 0x200
  48. #define USBNC_PHY_STATUS_OFFSET 0x23C
  49. #define USBNC_PHYSTATUS_ID_DIG (1 << 4) /* otg_id status */
  50. #define USBNC_PHYCFG2_ACAENB (1 << 4) /* otg_id detection enable */
  51. #define UCTRL_PWR_POL (1 << 9) /* OTG Polarity of Power Pin */
  52. #define UCTRL_OVER_CUR_POL (1 << 8) /* OTG Polarity of Overcurrent */
  53. #define UCTRL_OVER_CUR_DIS (1 << 7) /* Disable OTG Overcurrent Detection */
  54. /* USBCMD */
  55. #define UCMD_RUN_STOP (1 << 0) /* controller run/stop */
  56. #define UCMD_RESET (1 << 1) /* controller reset */
  57. #if defined(CONFIG_MX6) || defined(CONFIG_MX7ULP)
  58. static const unsigned phy_bases[] = {
  59. USB_PHY0_BASE_ADDR,
  60. #if defined(USB_PHY1_BASE_ADDR)
  61. USB_PHY1_BASE_ADDR,
  62. #endif
  63. };
  64. static void usb_internal_phy_clock_gate(int index, int on)
  65. {
  66. void __iomem *phy_reg;
  67. if (index >= ARRAY_SIZE(phy_bases))
  68. return;
  69. phy_reg = (void __iomem *)phy_bases[index];
  70. phy_reg += on ? USBPHY_CTRL_CLR : USBPHY_CTRL_SET;
  71. writel(USBPHY_CTRL_CLKGATE, phy_reg);
  72. }
  73. static void usb_power_config(int index)
  74. {
  75. #if defined(CONFIG_MX7ULP)
  76. struct usbphy_regs __iomem *usbphy =
  77. (struct usbphy_regs __iomem *)USB_PHY0_BASE_ADDR;
  78. if (index > 0)
  79. return;
  80. writel(ANADIG_USB2_CHRG_DETECT_EN_B |
  81. ANADIG_USB2_CHRG_DETECT_CHK_CHRG_B,
  82. &usbphy->usb1_chrg_detect);
  83. scg_enable_usb_pll(true);
  84. #else
  85. struct anatop_regs __iomem *anatop =
  86. (struct anatop_regs __iomem *)ANATOP_BASE_ADDR;
  87. void __iomem *chrg_detect;
  88. void __iomem *pll_480_ctrl_clr;
  89. void __iomem *pll_480_ctrl_set;
  90. switch (index) {
  91. case 0:
  92. chrg_detect = &anatop->usb1_chrg_detect;
  93. pll_480_ctrl_clr = &anatop->usb1_pll_480_ctrl_clr;
  94. pll_480_ctrl_set = &anatop->usb1_pll_480_ctrl_set;
  95. break;
  96. case 1:
  97. chrg_detect = &anatop->usb2_chrg_detect;
  98. pll_480_ctrl_clr = &anatop->usb2_pll_480_ctrl_clr;
  99. pll_480_ctrl_set = &anatop->usb2_pll_480_ctrl_set;
  100. break;
  101. default:
  102. return;
  103. }
  104. /*
  105. * Some phy and power's special controls
  106. * 1. The external charger detector needs to be disabled
  107. * or the signal at DP will be poor
  108. * 2. The PLL's power and output to usb
  109. * is totally controlled by IC, so the Software only needs
  110. * to enable them at initializtion.
  111. */
  112. writel(ANADIG_USB2_CHRG_DETECT_EN_B |
  113. ANADIG_USB2_CHRG_DETECT_CHK_CHRG_B,
  114. chrg_detect);
  115. writel(ANADIG_USB2_PLL_480_CTRL_BYPASS,
  116. pll_480_ctrl_clr);
  117. writel(ANADIG_USB2_PLL_480_CTRL_ENABLE |
  118. ANADIG_USB2_PLL_480_CTRL_POWER |
  119. ANADIG_USB2_PLL_480_CTRL_EN_USB_CLKS,
  120. pll_480_ctrl_set);
  121. #endif
  122. }
  123. /* Return 0 : host node, <>0 : device mode */
  124. static int usb_phy_enable(int index, struct usb_ehci *ehci)
  125. {
  126. void __iomem *phy_reg;
  127. void __iomem *phy_ctrl;
  128. void __iomem *usb_cmd;
  129. int ret;
  130. if (index >= ARRAY_SIZE(phy_bases))
  131. return 0;
  132. phy_reg = (void __iomem *)phy_bases[index];
  133. phy_ctrl = (void __iomem *)(phy_reg + USBPHY_CTRL);
  134. usb_cmd = (void __iomem *)&ehci->usbcmd;
  135. /* Stop then Reset */
  136. clrbits_le32(usb_cmd, UCMD_RUN_STOP);
  137. ret = wait_for_bit_le32(usb_cmd, UCMD_RUN_STOP, false, 10000, false);
  138. if (ret)
  139. return ret;
  140. setbits_le32(usb_cmd, UCMD_RESET);
  141. ret = wait_for_bit_le32(usb_cmd, UCMD_RESET, false, 10000, false);
  142. if (ret)
  143. return ret;
  144. /* Reset USBPHY module */
  145. setbits_le32(phy_ctrl, USBPHY_CTRL_SFTRST);
  146. udelay(10);
  147. /* Remove CLKGATE and SFTRST */
  148. clrbits_le32(phy_ctrl, USBPHY_CTRL_CLKGATE | USBPHY_CTRL_SFTRST);
  149. udelay(10);
  150. /* Power up the PHY */
  151. writel(0, phy_reg + USBPHY_PWD);
  152. /* enable FS/LS device */
  153. setbits_le32(phy_ctrl, USBPHY_CTRL_ENUTMILEVEL2 |
  154. USBPHY_CTRL_ENUTMILEVEL3);
  155. return 0;
  156. }
  157. int usb_phy_mode(int port)
  158. {
  159. void __iomem *phy_reg;
  160. void __iomem *phy_ctrl;
  161. u32 val;
  162. phy_reg = (void __iomem *)phy_bases[port];
  163. phy_ctrl = (void __iomem *)(phy_reg + USBPHY_CTRL);
  164. val = readl(phy_ctrl);
  165. if (val & USBPHY_CTRL_OTG_ID)
  166. return USB_INIT_DEVICE;
  167. else
  168. return USB_INIT_HOST;
  169. }
  170. #if defined(CONFIG_MX7ULP)
  171. struct usbnc_regs {
  172. u32 ctrl1;
  173. u32 ctrl2;
  174. u32 reserve0[2];
  175. u32 hsic_ctrl;
  176. };
  177. #else
  178. /* Base address for this IP block is 0x02184800 */
  179. struct usbnc_regs {
  180. u32 ctrl[4]; /* otg/host1-3 */
  181. u32 uh2_hsic_ctrl;
  182. u32 uh3_hsic_ctrl;
  183. u32 otg_phy_ctrl_0;
  184. u32 uh1_phy_ctrl_0;
  185. };
  186. #endif
  187. #elif defined(CONFIG_MX7)
  188. struct usbnc_regs {
  189. u32 ctrl1;
  190. u32 ctrl2;
  191. u32 reserve1[10];
  192. u32 phy_cfg1;
  193. u32 phy_cfg2;
  194. u32 reserve2;
  195. u32 phy_status;
  196. u32 reserve3[4];
  197. u32 adp_cfg1;
  198. u32 adp_cfg2;
  199. u32 adp_status;
  200. };
  201. static void usb_power_config(int index)
  202. {
  203. struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR +
  204. (0x10000 * index) + USBNC_OFFSET);
  205. void __iomem *phy_cfg2 = (void __iomem *)(&usbnc->phy_cfg2);
  206. /*
  207. * Clear the ACAENB to enable usb_otg_id detection,
  208. * otherwise it is the ACA detection enabled.
  209. */
  210. clrbits_le32(phy_cfg2, USBNC_PHYCFG2_ACAENB);
  211. }
  212. int usb_phy_mode(int port)
  213. {
  214. struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR +
  215. (0x10000 * port) + USBNC_OFFSET);
  216. void __iomem *status = (void __iomem *)(&usbnc->phy_status);
  217. u32 val;
  218. val = readl(status);
  219. if (val & USBNC_PHYSTATUS_ID_DIG)
  220. return USB_INIT_DEVICE;
  221. else
  222. return USB_INIT_HOST;
  223. }
  224. #endif
  225. static void usb_oc_config(int index)
  226. {
  227. #if defined(CONFIG_MX6)
  228. struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR +
  229. USB_OTHERREGS_OFFSET);
  230. void __iomem *ctrl = (void __iomem *)(&usbnc->ctrl[index]);
  231. #elif defined(CONFIG_MX7) || defined(CONFIG_MX7ULP)
  232. struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR +
  233. (0x10000 * index) + USBNC_OFFSET);
  234. void __iomem *ctrl = (void __iomem *)(&usbnc->ctrl1);
  235. #endif
  236. #if CONFIG_MACH_TYPE == MACH_TYPE_MX6Q_ARM2
  237. /* mx6qarm2 seems to required a different setting*/
  238. clrbits_le32(ctrl, UCTRL_OVER_CUR_POL);
  239. #else
  240. setbits_le32(ctrl, UCTRL_OVER_CUR_POL);
  241. #endif
  242. setbits_le32(ctrl, UCTRL_OVER_CUR_DIS);
  243. /* Set power polarity to high active */
  244. #ifdef CONFIG_MXC_USB_OTG_HACTIVE
  245. setbits_le32(ctrl, UCTRL_PWR_POL);
  246. #else
  247. clrbits_le32(ctrl, UCTRL_PWR_POL);
  248. #endif
  249. }
  250. /**
  251. * board_usb_phy_mode - override usb phy mode
  252. * @port: usb host/otg port
  253. *
  254. * Target board specific, override usb_phy_mode.
  255. * When usb-otg is used as usb host port, iomux pad usb_otg_id can be
  256. * left disconnected in this case usb_phy_mode will not be able to identify
  257. * the phy mode that usb port is used.
  258. * Machine file overrides board_usb_phy_mode.
  259. *
  260. * Return: USB_INIT_DEVICE or USB_INIT_HOST
  261. */
  262. int __weak board_usb_phy_mode(int port)
  263. {
  264. return usb_phy_mode(port);
  265. }
  266. /**
  267. * board_ehci_hcd_init - set usb vbus voltage
  268. * @port: usb otg port
  269. *
  270. * Target board specific, setup iomux pad to setup supply vbus voltage
  271. * for usb otg port. Machine board file overrides board_ehci_hcd_init
  272. *
  273. * Return: 0 Success
  274. */
  275. int __weak board_ehci_hcd_init(int port)
  276. {
  277. return 0;
  278. }
  279. /**
  280. * board_ehci_power - enables/disables usb vbus voltage
  281. * @port: usb otg port
  282. * @on: on/off vbus voltage
  283. *
  284. * Enables/disables supply vbus voltage for usb otg port.
  285. * Machine board file overrides board_ehci_power
  286. *
  287. * Return: 0 Success
  288. */
  289. int __weak board_ehci_power(int port, int on)
  290. {
  291. return 0;
  292. }
  293. int ehci_mx6_common_init(struct usb_ehci *ehci, int index)
  294. {
  295. int ret;
  296. enable_usboh3_clk(1);
  297. mdelay(1);
  298. /* Do board specific initialization */
  299. ret = board_ehci_hcd_init(index);
  300. if (ret)
  301. return ret;
  302. usb_power_config(index);
  303. usb_oc_config(index);
  304. #if defined(CONFIG_MX6) || defined(CONFIG_MX7ULP)
  305. usb_internal_phy_clock_gate(index, 1);
  306. usb_phy_enable(index, ehci);
  307. #endif
  308. return 0;
  309. }
  310. #if !CONFIG_IS_ENABLED(DM_USB)
  311. int ehci_hcd_init(int index, enum usb_init_type init,
  312. struct ehci_hccr **hccr, struct ehci_hcor **hcor)
  313. {
  314. enum usb_init_type type;
  315. #if defined(CONFIG_MX6)
  316. u32 controller_spacing = 0x200;
  317. #elif defined(CONFIG_MX7) || defined(CONFIG_MX7ULP)
  318. u32 controller_spacing = 0x10000;
  319. #endif
  320. struct usb_ehci *ehci = (struct usb_ehci *)(USB_BASE_ADDR +
  321. (controller_spacing * index));
  322. int ret;
  323. if (index > 3)
  324. return -EINVAL;
  325. if (CONFIG_IS_ENABLED(IMX_MODULE_FUSE)) {
  326. if (usb_fused((ulong)ehci)) {
  327. printf("SoC fuse indicates USB@0x%lx is unavailable.\n",
  328. (ulong)ehci);
  329. return -ENODEV;
  330. }
  331. }
  332. ret = ehci_mx6_common_init(ehci, index);
  333. if (ret)
  334. return ret;
  335. type = board_usb_phy_mode(index);
  336. if (hccr && hcor) {
  337. *hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
  338. *hcor = (struct ehci_hcor *)((uint32_t)*hccr +
  339. HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
  340. }
  341. if ((type == init) || (type == USB_INIT_DEVICE))
  342. board_ehci_power(index, (type == USB_INIT_DEVICE) ? 0 : 1);
  343. if (type != init)
  344. return -ENODEV;
  345. if (type == USB_INIT_DEVICE)
  346. return 0;
  347. setbits_le32(&ehci->usbmode, CM_HOST);
  348. writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc);
  349. setbits_le32(&ehci->portsc, USB_EN);
  350. mdelay(10);
  351. return 0;
  352. }
  353. int ehci_hcd_stop(int index)
  354. {
  355. return 0;
  356. }
  357. #else
  358. struct ehci_mx6_priv_data {
  359. struct ehci_ctrl ctrl;
  360. struct usb_ehci *ehci;
  361. struct udevice *vbus_supply;
  362. enum usb_init_type init_type;
  363. int portnr;
  364. };
  365. static int mx6_init_after_reset(struct ehci_ctrl *dev)
  366. {
  367. struct ehci_mx6_priv_data *priv = dev->priv;
  368. enum usb_init_type type = priv->init_type;
  369. struct usb_ehci *ehci = priv->ehci;
  370. int ret;
  371. ret = ehci_mx6_common_init(priv->ehci, priv->portnr);
  372. if (ret)
  373. return ret;
  374. #if CONFIG_IS_ENABLED(DM_REGULATOR)
  375. if (priv->vbus_supply) {
  376. ret = regulator_set_enable(priv->vbus_supply,
  377. (type == USB_INIT_DEVICE) ?
  378. false : true);
  379. if (ret && ret != -ENOSYS) {
  380. printf("Error enabling VBUS supply (ret=%i)\n", ret);
  381. return ret;
  382. }
  383. }
  384. #endif
  385. if (type == USB_INIT_DEVICE)
  386. return 0;
  387. setbits_le32(&ehci->usbmode, CM_HOST);
  388. writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc);
  389. setbits_le32(&ehci->portsc, USB_EN);
  390. mdelay(10);
  391. return 0;
  392. }
  393. static const struct ehci_ops mx6_ehci_ops = {
  394. .init_after_reset = mx6_init_after_reset
  395. };
  396. static int ehci_usb_phy_mode(struct udevice *dev)
  397. {
  398. struct usb_plat *plat = dev_get_plat(dev);
  399. void *__iomem addr = dev_read_addr_ptr(dev);
  400. void *__iomem phy_ctrl, *__iomem phy_status;
  401. const void *blob = gd->fdt_blob;
  402. int offset = dev_of_offset(dev), phy_off;
  403. u32 val;
  404. /*
  405. * About fsl,usbphy, Refer to
  406. * Documentation/devicetree/bindings/usb/ci-hdrc-usb2.txt.
  407. */
  408. if (is_mx6() || is_mx7ulp()) {
  409. phy_off = fdtdec_lookup_phandle(blob,
  410. offset,
  411. "fsl,usbphy");
  412. if (phy_off < 0)
  413. return -EINVAL;
  414. addr = (void __iomem *)fdtdec_get_addr(blob, phy_off,
  415. "reg");
  416. if ((fdt_addr_t)addr == FDT_ADDR_T_NONE)
  417. return -EINVAL;
  418. phy_ctrl = (void __iomem *)(addr + USBPHY_CTRL);
  419. val = readl(phy_ctrl);
  420. if (val & USBPHY_CTRL_OTG_ID)
  421. plat->init_type = USB_INIT_DEVICE;
  422. else
  423. plat->init_type = USB_INIT_HOST;
  424. } else if (is_mx7()) {
  425. phy_status = (void __iomem *)(addr +
  426. USBNC_PHY_STATUS_OFFSET);
  427. val = readl(phy_status);
  428. if (val & USBNC_PHYSTATUS_ID_DIG)
  429. plat->init_type = USB_INIT_DEVICE;
  430. else
  431. plat->init_type = USB_INIT_HOST;
  432. } else {
  433. return -EINVAL;
  434. }
  435. return 0;
  436. }
  437. static int ehci_usb_of_to_plat(struct udevice *dev)
  438. {
  439. struct usb_plat *plat = dev_get_plat(dev);
  440. enum usb_dr_mode dr_mode;
  441. dr_mode = usb_get_dr_mode(dev_ofnode(dev));
  442. switch (dr_mode) {
  443. case USB_DR_MODE_HOST:
  444. plat->init_type = USB_INIT_HOST;
  445. break;
  446. case USB_DR_MODE_PERIPHERAL:
  447. plat->init_type = USB_INIT_DEVICE;
  448. break;
  449. case USB_DR_MODE_OTG:
  450. case USB_DR_MODE_UNKNOWN:
  451. return ehci_usb_phy_mode(dev);
  452. };
  453. return 0;
  454. }
  455. static int ehci_usb_bind(struct udevice *dev)
  456. {
  457. /*
  458. * TODO:
  459. * This driver is only partly converted to DT probing and still uses
  460. * a tremendous amount of hard-coded addresses. To make things worse,
  461. * the driver depends on specific sequential indexing of controllers,
  462. * from which it derives offsets in the PHY and ANATOP register sets.
  463. *
  464. * Here we attempt to calculate these indexes from DT information as
  465. * well as we can. The USB controllers on all existing iMX6 SoCs
  466. * are placed next to each other, at addresses incremented by 0x200,
  467. * and iMX7 their addresses are shifted by 0x10000.
  468. * Thus, the index is derived from the multiple of 0x200 (0x10000 for
  469. * iMX7) offset from the first controller address.
  470. *
  471. * However, to complete conversion of this driver to DT probing, the
  472. * following has to be done:
  473. * - DM clock framework support for iMX must be implemented
  474. * - usb_power_config() has to be converted to clock framework
  475. * -> Thus, the ad-hoc "index" variable goes away.
  476. * - USB PHY handling has to be factored out into separate driver
  477. * -> Thus, the ad-hoc "index" variable goes away from the PHY
  478. * code, the PHY driver must parse it's address from DT. This
  479. * USB driver must find the PHY driver via DT phandle.
  480. * -> usb_power_config() shall be moved to PHY driver
  481. * With these changes in place, the ad-hoc indexing goes away and
  482. * the driver is fully converted to DT probing.
  483. */
  484. /*
  485. * FIXME: This cannot work with the new sequence numbers.
  486. * Please complete the DM conversion.
  487. *
  488. * u32 controller_spacing = is_mx7() ? 0x10000 : 0x200;
  489. * fdt_addr_t addr = devfdt_get_addr_index(dev, 0);
  490. *
  491. * dev->req_seq = (addr - USB_BASE_ADDR) / controller_spacing;
  492. */
  493. return 0;
  494. }
  495. static int ehci_usb_probe(struct udevice *dev)
  496. {
  497. struct usb_plat *plat = dev_get_plat(dev);
  498. struct usb_ehci *ehci = dev_read_addr_ptr(dev);
  499. struct ehci_mx6_priv_data *priv = dev_get_priv(dev);
  500. enum usb_init_type type = plat->init_type;
  501. struct ehci_hccr *hccr;
  502. struct ehci_hcor *hcor;
  503. int ret;
  504. if (CONFIG_IS_ENABLED(IMX_MODULE_FUSE)) {
  505. if (usb_fused((ulong)ehci)) {
  506. printf("SoC fuse indicates USB@0x%lx is unavailable.\n",
  507. (ulong)ehci);
  508. return -ENODEV;
  509. }
  510. }
  511. priv->ehci = ehci;
  512. priv->portnr = dev_seq(dev);
  513. priv->init_type = type;
  514. #if CONFIG_IS_ENABLED(DM_REGULATOR)
  515. ret = device_get_supply_regulator(dev, "vbus-supply",
  516. &priv->vbus_supply);
  517. if (ret)
  518. debug("%s: No vbus supply\n", dev->name);
  519. #endif
  520. ret = ehci_mx6_common_init(ehci, priv->portnr);
  521. if (ret)
  522. return ret;
  523. #if CONFIG_IS_ENABLED(DM_REGULATOR)
  524. if (priv->vbus_supply) {
  525. ret = regulator_set_enable(priv->vbus_supply,
  526. (type == USB_INIT_DEVICE) ?
  527. false : true);
  528. if (ret && ret != -ENOSYS) {
  529. printf("Error enabling VBUS supply (ret=%i)\n", ret);
  530. return ret;
  531. }
  532. }
  533. #endif
  534. if (priv->init_type == USB_INIT_HOST) {
  535. setbits_le32(&ehci->usbmode, CM_HOST);
  536. writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc);
  537. setbits_le32(&ehci->portsc, USB_EN);
  538. }
  539. mdelay(10);
  540. hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
  541. hcor = (struct ehci_hcor *)((uint32_t)hccr +
  542. HC_LENGTH(ehci_readl(&(hccr)->cr_capbase)));
  543. return ehci_register(dev, hccr, hcor, &mx6_ehci_ops, 0, priv->init_type);
  544. }
  545. static const struct udevice_id mx6_usb_ids[] = {
  546. { .compatible = "fsl,imx27-usb" },
  547. { }
  548. };
  549. U_BOOT_DRIVER(usb_mx6) = {
  550. .name = "ehci_mx6",
  551. .id = UCLASS_USB,
  552. .of_match = mx6_usb_ids,
  553. .of_to_plat = ehci_usb_of_to_plat,
  554. .bind = ehci_usb_bind,
  555. .probe = ehci_usb_probe,
  556. .remove = ehci_deregister,
  557. .ops = &ehci_usb_ops,
  558. .plat_auto = sizeof(struct usb_plat),
  559. .priv_auto = sizeof(struct ehci_mx6_priv_data),
  560. .flags = DM_FLAG_ALLOC_PRIV_DMA,
  561. };
  562. #endif