starfive_evb.c 8.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2022-2023 StarFive Technology Co., Ltd.
  4. * Author: yanhong <yanhong.wang@starfivetech.com>
  5. *
  6. */
  7. #include <common.h>
  8. #include <asm/io.h>
  9. #include <asm/arch/jh7110-regs.h>
  10. #include <cpu_func.h>
  11. #include <dm/uclass.h>
  12. #include <dm/device.h>
  13. #include <env.h>
  14. #include <inttypes.h>
  15. #include <misc.h>
  16. #include <linux/bitops.h>
  17. #include <asm/arch/gpio.h>
  18. #include <bmp_logo.h>
  19. #include <video.h>
  20. #include <splash.h>
  21. enum chip_type_t {
  22. CHIP_A = 0,
  23. CHIP_B,
  24. CHIP_MAX,
  25. };
  26. enum cpu_voltage_type_t {
  27. CPU_VOL_1020 = 0xef0,
  28. CPU_VOL_1040 = 0xfff,
  29. CPU_VOL_1060 = 0xff0,
  30. CPU_VOL_1000 = 0x8f0,
  31. };
  32. #define CPU_VOL_MASK 0xfff
  33. #define SYS_CLOCK_ENABLE(clk) \
  34. setbits_le32(SYS_CRG_BASE + clk, CLK_ENABLE_MASK)
  35. #define CPU_VOL_BINNING_OFFSET 0x7fc
  36. static void sys_reset_clear(ulong assert, ulong status, u32 rst)
  37. {
  38. u32 value;
  39. clrbits_le32(SYS_CRG_BASE + assert, BIT(rst));
  40. do {
  41. value = in_le32(SYS_CRG_BASE + status);
  42. } while ((value & BIT(rst)) != BIT(rst));
  43. }
  44. static void jh7110_timer_init(void)
  45. {
  46. SYS_CLOCK_ENABLE(TIMER_CLK_APB_SHIFT);
  47. SYS_CLOCK_ENABLE(TIMER_CLK_TIMER0_SHIFT);
  48. SYS_CLOCK_ENABLE(TIMER_CLK_TIMER1_SHIFT);
  49. SYS_CLOCK_ENABLE(TIMER_CLK_TIMER2_SHIFT);
  50. SYS_CLOCK_ENABLE(TIMER_CLK_TIMER3_SHIFT);
  51. sys_reset_clear(SYS_CRG_RESET_ASSERT3_SHIFT,
  52. SYS_CRG_RESET_STATUS3_SHIFT, TIMER_RSTN_APB_SHIFT);
  53. sys_reset_clear(SYS_CRG_RESET_ASSERT3_SHIFT,
  54. SYS_CRG_RESET_STATUS3_SHIFT, TIMER_RSTN_TIMER0_SHIFT);
  55. sys_reset_clear(SYS_CRG_RESET_ASSERT3_SHIFT,
  56. SYS_CRG_RESET_STATUS3_SHIFT, TIMER_RSTN_TIMER1_SHIFT);
  57. sys_reset_clear(SYS_CRG_RESET_ASSERT3_SHIFT,
  58. SYS_CRG_RESET_STATUS3_SHIFT, TIMER_RSTN_TIMER2_SHIFT);
  59. sys_reset_clear(SYS_CRG_RESET_ASSERT3_SHIFT,
  60. SYS_CRG_RESET_STATUS3_SHIFT, TIMER_RSTN_TIMER3_SHIFT);
  61. }
  62. static void jh7110_gmac_sel_tx_to_rgmii(int id)
  63. {
  64. switch (id) {
  65. case 0:
  66. clrsetbits_le32(AON_CRG_BASE + GMAC5_0_CLK_TX_SHIFT,
  67. GMAC5_0_CLK_TX_MASK,
  68. BIT(GMAC5_0_CLK_TX_BIT) & GMAC5_0_CLK_TX_MASK);
  69. break;
  70. case 1:
  71. clrsetbits_le32(SYS_CRG_BASE + GMAC5_1_CLK_TX_SHIFT,
  72. GMAC5_1_CLK_TX_MASK,
  73. BIT(GMAC5_1_CLK_TX_BIT) & GMAC5_1_CLK_TX_MASK);
  74. break;
  75. default:
  76. break;
  77. }
  78. }
  79. static void jh7110_gmac_io_pad(int id)
  80. {
  81. u32 cap = BIT(0); /* 2.5V */
  82. switch (id) {
  83. case 0:
  84. /* Improved GMAC0 TX I/O PAD capability */
  85. clrsetbits_le32(AON_IOMUX_BASE + 0x78, 0x3, cap & 0x3);
  86. clrsetbits_le32(AON_IOMUX_BASE + 0x7c, 0x3, cap & 0x3);
  87. clrsetbits_le32(AON_IOMUX_BASE + 0x80, 0x3, cap & 0x3);
  88. clrsetbits_le32(AON_IOMUX_BASE + 0x84, 0x3, cap & 0x3);
  89. clrsetbits_le32(AON_IOMUX_BASE + 0x88, 0x3, cap & 0x3);
  90. break;
  91. case 1:
  92. /* Improved GMAC1 TX I/O PAD capability */
  93. clrsetbits_le32(SYS_IOMUX_BASE + 0x26c, 0x3, cap & 0x3);
  94. clrsetbits_le32(SYS_IOMUX_BASE + 0x270, 0x3, cap & 0x3);
  95. clrsetbits_le32(SYS_IOMUX_BASE + 0x274, 0x3, cap & 0x3);
  96. clrsetbits_le32(SYS_IOMUX_BASE + 0x278, 0x3, cap & 0x3);
  97. clrsetbits_le32(SYS_IOMUX_BASE + 0x27c, 0x3, cap & 0x3);
  98. break;
  99. }
  100. }
  101. static void jh7110_gmac_init(int id, u32 chip)
  102. {
  103. switch (chip) {
  104. case CHIP_B:
  105. jh7110_gmac_sel_tx_to_rgmii(id);
  106. jh7110_gmac_io_pad(id);
  107. break;
  108. case CHIP_A:
  109. default:
  110. break;
  111. }
  112. }
  113. static void jh7110_usb_init(bool usb2_enable)
  114. {
  115. if (usb2_enable) {
  116. /*usb 2.0 utmi phy init*/
  117. clrsetbits_le32(STG_SYSCON_BASE + STG_SYSCON_4,
  118. USB_MODE_STRAP_MASK,
  119. (2<<USB_MODE_STRAP_SHIFT) &
  120. USB_MODE_STRAP_MASK);/*2:host mode, 4:device mode*/
  121. clrsetbits_le32(STG_SYSCON_BASE + STG_SYSCON_4,
  122. USB_OTG_SUSPENDM_BYPS_MASK,
  123. BIT(USB_OTG_SUSPENDM_BYPS_SHIFT)
  124. & USB_OTG_SUSPENDM_BYPS_MASK);
  125. clrsetbits_le32(STG_SYSCON_BASE + STG_SYSCON_4,
  126. USB_OTG_SUSPENDM_MASK,
  127. BIT(USB_OTG_SUSPENDM_SHIFT) &
  128. USB_OTG_SUSPENDM_MASK);/*HOST = 1. DEVICE = 0;*/
  129. clrsetbits_le32(STG_SYSCON_BASE + STG_SYSCON_4,
  130. USB_PLL_EN_MASK,
  131. BIT(USB_PLL_EN_SHIFT) & USB_PLL_EN_MASK);
  132. clrsetbits_le32(STG_SYSCON_BASE + STG_SYSCON_4,
  133. USB_REFCLK_MODE_MASK,
  134. BIT(USB_REFCLK_MODE_SHIFT) & USB_REFCLK_MODE_MASK);
  135. /* usb 2.0 phy mode,REPLACE USB3.0 PHY module = 1;else = 0*/
  136. clrsetbits_le32(SYS_SYSCON_BASE + SYS_SYSCON_24,
  137. PDRSTN_SPLIT_MASK,
  138. BIT(PDRSTN_SPLIT_SHIFT) &
  139. PDRSTN_SPLIT_MASK);
  140. } else {
  141. /*usb 3.0 pipe phy config*/
  142. clrsetbits_le32(STG_SYSCON_BASE + STG_SYSCON_196,
  143. PCIE_CKREF_SRC_MASK,
  144. (0<<PCIE_CKREF_SRC_SHIFT) & PCIE_CKREF_SRC_MASK);
  145. clrsetbits_le32(STG_SYSCON_BASE + STG_SYSCON_196,
  146. PCIE_CLK_SEL_MASK,
  147. (0<<PCIE_CLK_SEL_SHIFT) & PCIE_CLK_SEL_MASK);
  148. clrsetbits_le32(STG_SYSCON_BASE + STG_SYSCON_328,
  149. PCIE_PHY_MODE_MASK,
  150. BIT(PCIE_PHY_MODE_SHIFT) & PCIE_PHY_MODE_MASK);
  151. clrsetbits_le32(STG_SYSCON_BASE + STG_SYSCON_500,
  152. PCIE_USB3_BUS_WIDTH_MASK,
  153. (0 << PCIE_USB3_BUS_WIDTH_SHIFT) &
  154. PCIE_USB3_BUS_WIDTH_MASK);
  155. clrsetbits_le32(STG_SYSCON_BASE + STG_SYSCON_500,
  156. PCIE_USB3_RATE_MASK,
  157. (0 << PCIE_USB3_RATE_SHIFT) & PCIE_USB3_RATE_MASK);
  158. clrsetbits_le32(STG_SYSCON_BASE + STG_SYSCON_500,
  159. PCIE_USB3_RX_STANDBY_MASK,
  160. (0 << PCIE_USB3_RX_STANDBY_SHIFT)
  161. & PCIE_USB3_RX_STANDBY_MASK);
  162. clrsetbits_le32(STG_SYSCON_BASE + STG_SYSCON_500,
  163. PCIE_USB3_PHY_ENABLE_MASK,
  164. BIT(PCIE_USB3_PHY_ENABLE_SHIFT)
  165. & PCIE_USB3_PHY_ENABLE_MASK);
  166. /* usb 3.0 phy mode,REPLACE USB3.0 PHY module = 1;else = 0*/
  167. clrsetbits_le32(SYS_SYSCON_BASE + SYS_SYSCON_24,
  168. PDRSTN_SPLIT_MASK,
  169. (0 << PDRSTN_SPLIT_SHIFT) & PDRSTN_SPLIT_MASK);
  170. }
  171. }
  172. static u32 get_chip_type(void)
  173. {
  174. u32 value;
  175. value = in_le32(AON_IOMUX_BASE + AON_GPIO_DIN_REG);
  176. value = (value & BIT(3)) >> 3;
  177. switch (value) {
  178. case CHIP_B:
  179. env_set("chip_vision", "B");
  180. break;
  181. case CHIP_A:
  182. default:
  183. env_set("chip_vision", "A");
  184. break;
  185. }
  186. return value;
  187. }
  188. static void get_boot_mode(void)
  189. {
  190. /* evb only support flash boot */
  191. env_set("bootmode", "flash");
  192. }
  193. #if CONFIG_IS_ENABLED(STARFIVE_OTP)
  194. static void get_cpu_voltage_type(struct udevice *dev)
  195. {
  196. int ret;
  197. u32 buf = CPU_VOL_1040;
  198. ret = misc_read(dev, CPU_VOL_BINNING_OFFSET, &buf, sizeof(buf));
  199. if (ret != sizeof(buf))
  200. printf("%s: error reading CPU vol from OTP\n", __func__);
  201. else {
  202. switch ((buf & CPU_VOL_MASK)) {
  203. case CPU_VOL_1000:
  204. env_set("cpu_max_vol", "1000000");
  205. break;
  206. case CPU_VOL_1060:
  207. env_set("cpu_max_vol", "1060000");
  208. break;
  209. case CPU_VOL_1020:
  210. env_set("cpu_max_vol", "1020000");
  211. break;
  212. default:
  213. break;
  214. }
  215. }
  216. }
  217. #endif
  218. int board_init(void)
  219. {
  220. enable_caches();
  221. jh7110_timer_init();
  222. jh7110_usb_init(true);
  223. return 0;
  224. }
  225. #ifdef CONFIG_MISC_INIT_R
  226. int misc_init_r(void)
  227. {
  228. char mac0[6] = {0x66, 0x34, 0xb0, 0x6c, 0xde, 0xad};
  229. char mac1[6] = {0x66, 0x34, 0xb0, 0x7c, 0xae, 0x5d};
  230. u32 chip;
  231. #if CONFIG_IS_ENABLED(STARFIVE_OTP)
  232. struct udevice *dev;
  233. char buf[16];
  234. int ret;
  235. #define MACADDR_OFFSET 0x8
  236. ret = uclass_get_device_by_driver(UCLASS_MISC,
  237. DM_DRIVER_GET(starfive_otp), &dev);
  238. if (ret) {
  239. debug("%s: could not find otp device\n", __func__);
  240. goto err;
  241. }
  242. ret = misc_read(dev, MACADDR_OFFSET, buf, sizeof(buf));
  243. if (ret != sizeof(buf))
  244. printf("%s: error reading mac from OTP\n", __func__);
  245. else
  246. if (buf[0] != 0xff) {
  247. memcpy(mac0, buf, 6);
  248. memcpy(mac1, &buf[8], 6);
  249. }
  250. err:
  251. #endif
  252. eth_env_set_enetaddr("eth0addr", mac0);
  253. eth_env_set_enetaddr("eth1addr", mac1);
  254. chip = get_chip_type();
  255. /* Set the default cpu max voltage. */
  256. env_set("cpu_max_vol", "1040000");
  257. #if CONFIG_IS_ENABLED(STARFIVE_OTP)
  258. get_cpu_voltage_type(dev);
  259. #endif
  260. jh7110_gmac_init(0, chip);
  261. jh7110_gmac_init(1, chip);
  262. return 0;
  263. }
  264. #endif
  265. int board_late_init(void)
  266. {
  267. struct udevice *dev;
  268. int ret;
  269. get_boot_mode();
  270. /*
  271. * save the memory info by environment variable in u-boot,
  272. * It will used to update the memory configuration in dts,
  273. * which passed to kernel lately.
  274. */
  275. env_set_hex("memory_addr", gd->ram_base);
  276. env_set_hex("memory_size", gd->ram_size);
  277. ret = uclass_get_device(UCLASS_VIDEO, 0, &dev);
  278. if (ret)
  279. return ret;
  280. ret = video_bmp_display(dev, (ulong)&bmp_logo_bitmap[0], BMP_ALIGN_CENTER, BMP_ALIGN_CENTER, true);
  281. if (ret)
  282. goto err;
  283. err:
  284. return 0;
  285. }
  286. #ifdef CONFIG_ID_EEPROM
  287. #include <asm/arch/eeprom.h>
  288. #define STARFIVE_JH7110_EEPROM_DDRINFO_OFFSET 91
  289. static bool check_eeprom_dram_info(ulong size)
  290. {
  291. switch (size) {
  292. case 1:
  293. case 2:
  294. case 4:
  295. case 8:
  296. case 16:
  297. return true;
  298. default:
  299. return false;
  300. }
  301. }
  302. static int resize_ddr_from_eeprom(void)
  303. {
  304. ulong size;
  305. u32 len = 1;
  306. u8 data = 0;
  307. int ret;
  308. /* read memory size info */
  309. ret = get_data_from_eeprom(STARFIVE_JH7110_EEPROM_DDRINFO_OFFSET, len, &data);
  310. if (ret == len) {
  311. size = hextoul(&data, NULL);
  312. if (check_eeprom_dram_info(size))
  313. return size;
  314. }
  315. return 0;
  316. }
  317. #else
  318. static int resize_ddr_from_eeprom(void)
  319. {
  320. return 0;
  321. }
  322. #endif /* CONFIG_ID_EEPROM */
  323. int board_ddr_size(void)
  324. {
  325. return resize_ddr_from_eeprom();
  326. }