cpu.c 3.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
  4. */
  5. #include <common.h>
  6. #include <cpu.h>
  7. #include <dm.h>
  8. #include <dm/lists.h>
  9. #include <init.h>
  10. #include <log.h>
  11. #include <asm/encoding.h>
  12. #include <dm/uclass-internal.h>
  13. #include <linux/bitops.h>
  14. /*
  15. * The variables here must be stored in the data section since they are used
  16. * before the bss section is available.
  17. */
  18. #ifdef CONFIG_OF_PRIOR_STAGE
  19. phys_addr_t prior_stage_fdt_address __section(".data");
  20. #endif
  21. #ifndef CONFIG_XIP
  22. u32 hart_lottery __section(".data") = 0;
  23. /*
  24. * The main hart running U-Boot has acquired available_harts_lock until it has
  25. * finished initialization of global data.
  26. */
  27. u32 available_harts_lock = 1;
  28. #endif
  29. static inline bool supports_extension(char ext)
  30. {
  31. #ifdef CONFIG_CPU
  32. struct udevice *dev;
  33. char desc[32];
  34. uclass_find_first_device(UCLASS_CPU, &dev);
  35. if (!dev) {
  36. debug("unable to find the RISC-V cpu device\n");
  37. return false;
  38. }
  39. if (!cpu_get_desc(dev, desc, sizeof(desc))) {
  40. /* skip the first 4 characters (rv32|rv64) */
  41. if (strchr(desc + 4, ext))
  42. return true;
  43. }
  44. return false;
  45. #else /* !CONFIG_CPU */
  46. #if CONFIG_IS_ENABLED(RISCV_MMODE)
  47. return csr_read(CSR_MISA) & (1 << (ext - 'a'));
  48. #else /* !CONFIG_IS_ENABLED(RISCV_MMODE) */
  49. #warning "There is no way to determine the available extensions in S-mode."
  50. #warning "Please convert your board to use the RISC-V CPU driver."
  51. return false;
  52. #endif /* CONFIG_IS_ENABLED(RISCV_MMODE) */
  53. #endif /* CONFIG_CPU */
  54. }
  55. static int riscv_cpu_probe(void)
  56. {
  57. #ifdef CONFIG_CPU
  58. int ret;
  59. /* probe cpus so that RISC-V timer can be bound */
  60. ret = cpu_probe_all();
  61. if (ret)
  62. return log_msg_ret("RISC-V cpus probe failed\n", ret);
  63. #endif
  64. return 0;
  65. }
  66. /*
  67. * This is called on secondary harts just after the IPI is init'd. Currently
  68. * there's nothing to do, since we just need to clear any existing IPIs, and
  69. * that is handled by the sending of an ipi itself.
  70. */
  71. #if CONFIG_IS_ENABLED(SMP)
  72. static void dummy_pending_ipi_clear(ulong hart, ulong arg0, ulong arg1)
  73. {
  74. }
  75. #endif
  76. int arch_cpu_init_dm(void)
  77. {
  78. int ret;
  79. ret = riscv_cpu_probe();
  80. if (ret)
  81. return ret;
  82. /* Enable FPU */
  83. if (supports_extension('d') || supports_extension('f')) {
  84. csr_set(MODE_PREFIX(status), MSTATUS_FS);
  85. csr_write(CSR_FCSR, 0);
  86. }
  87. if (CONFIG_IS_ENABLED(RISCV_MMODE)) {
  88. /*
  89. * Enable perf counters for cycle, time,
  90. * and instret counters only
  91. */
  92. #ifdef CONFIG_RISCV_PRIV_1_9
  93. csr_write(CSR_MSCOUNTEREN, GENMASK(2, 0));
  94. csr_write(CSR_MUCOUNTEREN, GENMASK(2, 0));
  95. #else
  96. csr_write(CSR_MCOUNTEREN, GENMASK(2, 0));
  97. #endif
  98. /* Disable paging */
  99. if (supports_extension('s'))
  100. #ifdef CONFIG_RISCV_PRIV_1_9
  101. csr_read_clear(CSR_MSTATUS, SR_VM);
  102. #else
  103. csr_write(CSR_SATP, 0);
  104. #endif
  105. }
  106. #if CONFIG_IS_ENABLED(SMP)
  107. ret = riscv_init_ipi();
  108. if (ret)
  109. return ret;
  110. /*
  111. * Clear all pending IPIs on secondary harts. We don't do anything on
  112. * the boot hart, since we never send an IPI to ourselves, and no
  113. * interrupts are enabled
  114. */
  115. ret = smp_call_function((ulong)dummy_pending_ipi_clear, 0, 0, 0);
  116. if (ret)
  117. return ret;
  118. #endif
  119. return 0;
  120. }
  121. int arch_early_init_r(void)
  122. {
  123. int ret;
  124. ret = riscv_cpu_probe();
  125. if (ret)
  126. return ret;
  127. if (IS_ENABLED(CONFIG_SYSRESET_SBI))
  128. device_bind_driver(gd->dm_root, "sbi-sysreset",
  129. "sbi-sysreset", NULL);
  130. return 0;
  131. }
  132. /**
  133. * harts_early_init() - A callback function called by start.S to configure
  134. * feature settings of each hart.
  135. *
  136. * In a multi-core system, memory access shall be careful here, it shall
  137. * take care of race conditions.
  138. */
  139. __weak void harts_early_init(void)
  140. {
  141. }