i2c.c 12 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2013 Google, Inc
  4. *
  5. * Note: Test coverage does not include 10-bit addressing
  6. */
  7. #include <common.h>
  8. #include <dm.h>
  9. #include <fdtdec.h>
  10. #include <i2c.h>
  11. #include <asm/state.h>
  12. #include <asm/test.h>
  13. #include <dm/device-internal.h>
  14. #include <dm/test.h>
  15. #include <dm/uclass-internal.h>
  16. #include <dm/util.h>
  17. #include <hexdump.h>
  18. #include <test/test.h>
  19. #include <test/ut.h>
  20. static const int busnum;
  21. static const int chip = 0x2c;
  22. /* Test that we can find buses and chips */
  23. static int dm_test_i2c_find(struct unit_test_state *uts)
  24. {
  25. struct udevice *bus, *dev;
  26. const int no_chip = 0x10;
  27. /*
  28. * The post_bind() method will bind devices to chip selects. Check
  29. * this then remove the emulation and the slave device.
  30. */
  31. ut_assertok(uclass_get_device_by_seq(UCLASS_I2C, busnum, &bus));
  32. ut_assertok(dm_i2c_probe(bus, chip, 0, &dev));
  33. ut_asserteq(-ENOENT, dm_i2c_probe(bus, no_chip, 0, &dev));
  34. ut_asserteq(-ENODEV, uclass_get_device_by_seq(UCLASS_I2C, 1, &bus));
  35. return 0;
  36. }
  37. DM_TEST(dm_test_i2c_find, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
  38. static int dm_test_i2c_read_write(struct unit_test_state *uts)
  39. {
  40. struct udevice *bus, *dev;
  41. uint8_t buf[5];
  42. ut_assertok(uclass_get_device_by_seq(UCLASS_I2C, busnum, &bus));
  43. ut_assertok(i2c_get_chip(bus, chip, 1, &dev));
  44. ut_assertok(dm_i2c_read(dev, 0, buf, 5));
  45. ut_asserteq_mem(buf, "\0\0\0\0\0", sizeof(buf));
  46. ut_assertok(dm_i2c_write(dev, 2, (uint8_t *)"AB", 2));
  47. ut_assertok(dm_i2c_read(dev, 0, buf, 5));
  48. ut_asserteq_mem(buf, "\0\0AB\0", sizeof(buf));
  49. return 0;
  50. }
  51. DM_TEST(dm_test_i2c_read_write, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
  52. static int dm_test_i2c_speed(struct unit_test_state *uts)
  53. {
  54. struct udevice *bus, *dev;
  55. uint8_t buf[5];
  56. ut_assertok(uclass_get_device_by_seq(UCLASS_I2C, busnum, &bus));
  57. /* Use test mode so we create the required errors for invalid speeds */
  58. sandbox_i2c_set_test_mode(bus, true);
  59. ut_assertok(i2c_get_chip(bus, chip, 1, &dev));
  60. ut_assertok(dm_i2c_set_bus_speed(bus, 100000));
  61. ut_assertok(dm_i2c_read(dev, 0, buf, 5));
  62. ut_assertok(dm_i2c_set_bus_speed(bus, 400000));
  63. ut_asserteq(400000, dm_i2c_get_bus_speed(bus));
  64. ut_assertok(dm_i2c_read(dev, 0, buf, 5));
  65. ut_asserteq(-EINVAL, dm_i2c_write(dev, 0, buf, 5));
  66. sandbox_i2c_set_test_mode(bus, false);
  67. return 0;
  68. }
  69. DM_TEST(dm_test_i2c_speed, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
  70. static int dm_test_i2c_offset_len(struct unit_test_state *uts)
  71. {
  72. struct udevice *bus, *dev;
  73. uint8_t buf[5];
  74. ut_assertok(uclass_get_device_by_seq(UCLASS_I2C, busnum, &bus));
  75. ut_assertok(i2c_get_chip(bus, chip, 1, &dev));
  76. ut_assertok(i2c_set_chip_offset_len(dev, 1));
  77. ut_assertok(dm_i2c_read(dev, 0, buf, 5));
  78. /* This is not supported by the uclass */
  79. ut_asserteq(-EINVAL, i2c_set_chip_offset_len(dev, 5));
  80. return 0;
  81. }
  82. DM_TEST(dm_test_i2c_offset_len, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
  83. static int dm_test_i2c_probe_empty(struct unit_test_state *uts)
  84. {
  85. struct udevice *bus, *dev;
  86. ut_assertok(uclass_get_device_by_seq(UCLASS_I2C, busnum, &bus));
  87. /* Use test mode so that this chip address will always probe */
  88. sandbox_i2c_set_test_mode(bus, true);
  89. ut_assertok(dm_i2c_probe(bus, SANDBOX_I2C_TEST_ADDR, 0, &dev));
  90. sandbox_i2c_set_test_mode(bus, false);
  91. return 0;
  92. }
  93. DM_TEST(dm_test_i2c_probe_empty, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
  94. static int dm_test_i2c_bytewise(struct unit_test_state *uts)
  95. {
  96. struct udevice *bus, *dev;
  97. struct udevice *eeprom;
  98. uint8_t buf[5];
  99. ut_assertok(uclass_get_device_by_seq(UCLASS_I2C, busnum, &bus));
  100. ut_assertok(i2c_get_chip(bus, chip, 1, &dev));
  101. ut_assertok(dm_i2c_read(dev, 0, buf, 5));
  102. ut_asserteq_mem(buf, "\0\0\0\0\0", sizeof(buf));
  103. /* Tell the EEPROM to only read/write one register at a time */
  104. ut_assertok(uclass_first_device(UCLASS_I2C_EMUL, &eeprom));
  105. ut_assertnonnull(eeprom);
  106. sandbox_i2c_eeprom_set_test_mode(eeprom, SIE_TEST_MODE_SINGLE_BYTE);
  107. /* Now we only get the first byte - the rest will be 0xff */
  108. ut_assertok(dm_i2c_read(dev, 0, buf, 5));
  109. ut_asserteq_mem(buf, "\0\xff\xff\xff\xff", sizeof(buf));
  110. /* If we do a separate transaction for each byte, it works */
  111. ut_assertok(i2c_set_chip_flags(dev, DM_I2C_CHIP_RD_ADDRESS));
  112. ut_assertok(dm_i2c_read(dev, 0, buf, 5));
  113. ut_asserteq_mem(buf, "\0\0\0\0\0", sizeof(buf));
  114. /* This will only write A */
  115. ut_assertok(i2c_set_chip_flags(dev, 0));
  116. ut_assertok(dm_i2c_write(dev, 2, (uint8_t *)"AB", 2));
  117. ut_assertok(dm_i2c_read(dev, 0, buf, 5));
  118. ut_asserteq_mem(buf, "\0\xff\xff\xff\xff", sizeof(buf));
  119. /* Check that the B was ignored */
  120. ut_assertok(i2c_set_chip_flags(dev, DM_I2C_CHIP_RD_ADDRESS));
  121. ut_assertok(dm_i2c_read(dev, 0, buf, 5));
  122. ut_asserteq_mem(buf, "\0\0A\0\0\0", sizeof(buf));
  123. /* Now write it again with the new flags, it should work */
  124. ut_assertok(i2c_set_chip_flags(dev, DM_I2C_CHIP_WR_ADDRESS));
  125. ut_assertok(dm_i2c_write(dev, 2, (uint8_t *)"AB", 2));
  126. ut_assertok(dm_i2c_read(dev, 0, buf, 5));
  127. ut_asserteq_mem(buf, "\0\xff\xff\xff\xff", sizeof(buf));
  128. ut_assertok(i2c_set_chip_flags(dev, DM_I2C_CHIP_WR_ADDRESS |
  129. DM_I2C_CHIP_RD_ADDRESS));
  130. ut_assertok(dm_i2c_read(dev, 0, buf, 5));
  131. ut_asserteq_mem(buf, "\0\0AB\0\0", sizeof(buf));
  132. /* Restore defaults */
  133. sandbox_i2c_eeprom_set_test_mode(eeprom, SIE_TEST_MODE_NONE);
  134. ut_assertok(i2c_set_chip_flags(dev, 0));
  135. return 0;
  136. }
  137. DM_TEST(dm_test_i2c_bytewise, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
  138. static int dm_test_i2c_offset(struct unit_test_state *uts)
  139. {
  140. struct udevice *eeprom;
  141. struct udevice *dev;
  142. uint8_t buf[5];
  143. ut_assertok(i2c_get_chip_for_busnum(busnum, chip, 1, &dev));
  144. /* Do a transfer so we can find the emulator */
  145. ut_assertok(dm_i2c_read(dev, 0, buf, 5));
  146. ut_assertok(uclass_first_device(UCLASS_I2C_EMUL, &eeprom));
  147. /* Offset length 0 */
  148. sandbox_i2c_eeprom_set_offset_len(eeprom, 0);
  149. ut_assertok(i2c_set_chip_offset_len(dev, 0));
  150. ut_assertok(dm_i2c_write(dev, 10 /* ignored */, (uint8_t *)"AB", 2));
  151. ut_assertok(dm_i2c_read(dev, 0, buf, 5));
  152. ut_asserteq_mem("AB\0\0\0\0", buf, sizeof(buf));
  153. ut_asserteq(0, sanbox_i2c_eeprom_get_prev_offset(eeprom));
  154. /* Offset length 1 */
  155. sandbox_i2c_eeprom_set_offset_len(eeprom, 1);
  156. ut_assertok(i2c_set_chip_offset_len(dev, 1));
  157. ut_assertok(dm_i2c_write(dev, 2, (uint8_t *)"AB", 2));
  158. ut_asserteq(2, sanbox_i2c_eeprom_get_prev_offset(eeprom));
  159. ut_assertok(dm_i2c_read(dev, 0, buf, 5));
  160. ut_asserteq_mem("ABAB\0", buf, sizeof(buf));
  161. ut_asserteq(0, sanbox_i2c_eeprom_get_prev_offset(eeprom));
  162. /* Offset length 2 boundary - check model wrapping */
  163. sandbox_i2c_eeprom_set_offset_len(eeprom, 2);
  164. ut_assertok(i2c_set_chip_offset_len(dev, 2));
  165. ut_assertok(dm_i2c_write(dev, 0xFF, (uint8_t *)"A", 1));
  166. ut_asserteq(0xFF, sanbox_i2c_eeprom_get_prev_offset(eeprom));
  167. ut_assertok(dm_i2c_write(dev, 0x100, (uint8_t *)"B", 1));
  168. ut_asserteq(0x100, sanbox_i2c_eeprom_get_prev_offset(eeprom));
  169. ut_assertok(dm_i2c_write(dev, 0x101, (uint8_t *)"C", 1));
  170. ut_asserteq(0x101, sanbox_i2c_eeprom_get_prev_offset(eeprom));
  171. ut_assertok(dm_i2c_read(dev, 0xFF, buf, 5));
  172. ut_asserteq_mem("ABCAB", buf, sizeof(buf));
  173. ut_asserteq(0xFF, sanbox_i2c_eeprom_get_prev_offset(eeprom));
  174. /* Offset length 2 */
  175. sandbox_i2c_eeprom_set_offset_len(eeprom, 2);
  176. ut_assertok(i2c_set_chip_offset_len(dev, 2));
  177. ut_assertok(dm_i2c_write(dev, 0x2020, (uint8_t *)"AB", 2));
  178. ut_assertok(dm_i2c_read(dev, 0x2020, buf, 5));
  179. ut_asserteq_mem("AB\0\0\0", buf, sizeof(buf));
  180. ut_asserteq(0x2020, sanbox_i2c_eeprom_get_prev_offset(eeprom));
  181. /* Offset length 3 */
  182. sandbox_i2c_eeprom_set_offset_len(eeprom, 3);
  183. ut_assertok(i2c_set_chip_offset_len(dev, 3));
  184. ut_assertok(dm_i2c_write(dev, 0x303030, (uint8_t *)"AB", 2));
  185. ut_assertok(dm_i2c_read(dev, 0x303030, buf, 5));
  186. ut_asserteq_mem("AB\0\0\0", buf, sizeof(buf));
  187. ut_asserteq(0x303030, sanbox_i2c_eeprom_get_prev_offset(eeprom));
  188. /* Offset length 4 */
  189. sandbox_i2c_eeprom_set_offset_len(eeprom, 4);
  190. ut_assertok(i2c_set_chip_offset_len(dev, 4));
  191. ut_assertok(dm_i2c_write(dev, 0x40404040, (uint8_t *)"AB", 2));
  192. ut_assertok(dm_i2c_read(dev, 0x40404040, buf, 5));
  193. ut_asserteq_mem("AB\0\0\0", buf, sizeof(buf));
  194. ut_asserteq(0x40404040, sanbox_i2c_eeprom_get_prev_offset(eeprom));
  195. /* Restore defaults */
  196. sandbox_i2c_eeprom_set_offset_len(eeprom, 1);
  197. return 0;
  198. }
  199. DM_TEST(dm_test_i2c_offset, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
  200. static int dm_test_i2c_addr_offset(struct unit_test_state *uts)
  201. {
  202. struct udevice *eeprom;
  203. struct udevice *dev;
  204. u8 buf[5];
  205. ut_assertok(i2c_get_chip_for_busnum(busnum, chip, 1, &dev));
  206. /* Do a transfer so we can find the emulator */
  207. ut_assertok(dm_i2c_read(dev, 0, buf, 5));
  208. ut_assertok(uclass_first_device(UCLASS_I2C_EMUL, &eeprom));
  209. /* Offset length 0 */
  210. sandbox_i2c_eeprom_set_offset_len(eeprom, 0);
  211. sandbox_i2c_eeprom_set_chip_addr_offset_mask(eeprom, 0x3);
  212. ut_assertok(i2c_set_chip_offset_len(dev, 0));
  213. ut_assertok(i2c_set_chip_addr_offset_mask(dev, 0x3));
  214. ut_assertok(dm_i2c_write(dev, 0x3, (uint8_t *)"AB", 2));
  215. ut_assertok(dm_i2c_read(dev, 0x3, buf, 5));
  216. ut_asserteq_mem("AB\0\0\0\0", buf, sizeof(buf));
  217. ut_asserteq(0x3, sanbox_i2c_eeprom_get_prev_offset(eeprom));
  218. ut_asserteq(chip | 0x3, sanbox_i2c_eeprom_get_prev_addr(eeprom));
  219. /* Offset length 1 */
  220. sandbox_i2c_eeprom_set_offset_len(eeprom, 1);
  221. sandbox_i2c_eeprom_set_chip_addr_offset_mask(eeprom, 0x3);
  222. ut_assertok(i2c_set_chip_offset_len(dev, 1));
  223. ut_assertok(i2c_set_chip_addr_offset_mask(dev, 0x3));
  224. ut_assertok(dm_i2c_write(dev, 0x310, (uint8_t *)"AB", 2));
  225. ut_assertok(dm_i2c_read(dev, 0x310, buf, 5));
  226. ut_asserteq_mem("AB\0\0\0\0", buf, sizeof(buf));
  227. ut_asserteq(0x310, sanbox_i2c_eeprom_get_prev_offset(eeprom));
  228. ut_asserteq(chip | 0x3, sanbox_i2c_eeprom_get_prev_addr(eeprom));
  229. /* Offset length 2 */
  230. sandbox_i2c_eeprom_set_offset_len(eeprom, 2);
  231. sandbox_i2c_eeprom_set_chip_addr_offset_mask(eeprom, 0x3);
  232. ut_assertok(i2c_set_chip_offset_len(dev, 2));
  233. ut_assertok(i2c_set_chip_addr_offset_mask(dev, 0x3));
  234. ut_assertok(dm_i2c_write(dev, 0x32020, (uint8_t *)"AB", 2));
  235. ut_assertok(dm_i2c_read(dev, 0x32020, buf, 5));
  236. ut_asserteq_mem("AB\0\0\0\0", buf, sizeof(buf));
  237. ut_asserteq(0x32020, sanbox_i2c_eeprom_get_prev_offset(eeprom));
  238. ut_asserteq(chip | 0x3, sanbox_i2c_eeprom_get_prev_addr(eeprom));
  239. /* Offset length 3 */
  240. sandbox_i2c_eeprom_set_offset_len(eeprom, 3);
  241. sandbox_i2c_eeprom_set_chip_addr_offset_mask(eeprom, 0x3);
  242. ut_assertok(i2c_set_chip_offset_len(dev, 3));
  243. ut_assertok(i2c_set_chip_addr_offset_mask(dev, 0x3));
  244. ut_assertok(dm_i2c_write(dev, 0x3303030, (uint8_t *)"AB", 2));
  245. ut_assertok(dm_i2c_read(dev, 0x3303030, buf, 5));
  246. ut_asserteq_mem("AB\0\0\0\0", buf, sizeof(buf));
  247. ut_asserteq(0x3303030, sanbox_i2c_eeprom_get_prev_offset(eeprom));
  248. ut_asserteq(chip | 0x3, sanbox_i2c_eeprom_get_prev_addr(eeprom));
  249. /* Restore defaults */
  250. sandbox_i2c_eeprom_set_offset_len(eeprom, 1);
  251. sandbox_i2c_eeprom_set_chip_addr_offset_mask(eeprom, 0);
  252. return 0;
  253. }
  254. DM_TEST(dm_test_i2c_addr_offset, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
  255. static int dm_test_i2c_reg_clrset(struct unit_test_state *uts)
  256. {
  257. struct udevice *eeprom;
  258. struct udevice *dev;
  259. u8 buf[5];
  260. ut_assertok(i2c_get_chip_for_busnum(busnum, chip, 1, &dev));
  261. /* Do a transfer so we can find the emulator */
  262. ut_assertok(dm_i2c_read(dev, 0, buf, 5));
  263. ut_assertok(uclass_first_device(UCLASS_I2C_EMUL, &eeprom));
  264. /* Dummy data for the test */
  265. ut_assertok(dm_i2c_write(dev, 0, "\xff\x00\xff\x00\x10", 5));
  266. /* Do some clrset tests */
  267. ut_assertok(dm_i2c_reg_clrset(dev, 0, 0xff, 0x10));
  268. ut_assertok(dm_i2c_reg_clrset(dev, 1, 0x00, 0x11));
  269. ut_assertok(dm_i2c_reg_clrset(dev, 2, 0xed, 0x00));
  270. ut_assertok(dm_i2c_reg_clrset(dev, 3, 0xff, 0x13));
  271. ut_assertok(dm_i2c_reg_clrset(dev, 4, 0x00, 0x14));
  272. ut_assertok(dm_i2c_read(dev, 0, buf, 5));
  273. ut_asserteq_mem("\x10\x11\x12\x13\x14", buf, sizeof(buf));
  274. return 0;
  275. }
  276. DM_TEST(dm_test_i2c_reg_clrset, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);