spl.c 4.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright 2019 Google LLC
  4. */
  5. #include <common.h>
  6. #include <binman_sym.h>
  7. #include <bootstage.h>
  8. #include <dm.h>
  9. #include <image.h>
  10. #include <log.h>
  11. #include <malloc.h>
  12. #include <spi.h>
  13. #include <spl.h>
  14. #include <spi_flash.h>
  15. #include <asm/fast_spi.h>
  16. #include <asm/spl.h>
  17. #include <asm/arch/cpu.h>
  18. #include <asm/arch/iomap.h>
  19. #include <dm/device-internal.h>
  20. #include <dm/uclass-internal.h>
  21. /* This reads the next phase from mapped SPI flash */
  22. static int rom_load_image(struct spl_image_info *spl_image,
  23. struct spl_boot_device *bootdev)
  24. {
  25. ulong spl_pos = spl_get_image_pos();
  26. ulong spl_size = spl_get_image_size();
  27. struct udevice *dev;
  28. ulong map_base;
  29. size_t map_size;
  30. uint offset;
  31. int ret;
  32. spl_image->size = CONFIG_SYS_MONITOR_LEN; /* We don't know SPL size */
  33. spl_image->entry_point = spl_phase() == PHASE_TPL ?
  34. CONFIG_SPL_TEXT_BASE : CONFIG_SYS_TEXT_BASE;
  35. spl_image->load_addr = spl_image->entry_point;
  36. spl_image->os = IH_OS_U_BOOT;
  37. spl_image->name = "U-Boot";
  38. debug("Reading from mapped SPI %lx, size %lx", spl_pos, spl_size);
  39. if (CONFIG_IS_ENABLED(SPI_FLASH_SUPPORT)) {
  40. ret = uclass_find_first_device(UCLASS_SPI_FLASH, &dev);
  41. if (ret)
  42. return log_msg_ret("spi_flash", ret);
  43. if (!dev)
  44. return log_msg_ret("spi_flash dev", -ENODEV);
  45. ret = dm_spi_get_mmap(dev, &map_base, &map_size, &offset);
  46. if (ret)
  47. return log_msg_ret("mmap", ret);
  48. } else {
  49. ret = fast_spi_get_bios_mmap(PCH_DEV_SPI, &map_base, &map_size,
  50. &offset);
  51. if (ret)
  52. return ret;
  53. }
  54. spl_pos += map_base & ~0xff000000;
  55. debug(", base %lx, pos %lx\n", map_base, spl_pos);
  56. bootstage_start(BOOTSTAGE_ID_ACCUM_MMAP_SPI, "mmap_spi");
  57. memcpy((void *)spl_image->load_addr, (void *)spl_pos, spl_size);
  58. cpu_flush_l1d_to_l2();
  59. bootstage_accum(BOOTSTAGE_ID_ACCUM_MMAP_SPI);
  60. return 0;
  61. }
  62. SPL_LOAD_IMAGE_METHOD("Mapped SPI", 2, BOOT_DEVICE_SPI_MMAP, rom_load_image);
  63. #if CONFIG_IS_ENABLED(SPI_FLASH_SUPPORT)
  64. static int apl_flash_std_read(struct udevice *dev, u32 offset, size_t len,
  65. void *buf)
  66. {
  67. struct spi_flash *flash = dev_get_uclass_priv(dev);
  68. struct mtd_info *mtd = &flash->mtd;
  69. size_t retlen;
  70. return log_ret(mtd->_read(mtd, offset, len, &retlen, buf));
  71. }
  72. static int apl_flash_probe(struct udevice *dev)
  73. {
  74. return spi_flash_std_probe(dev);
  75. }
  76. /*
  77. * Manually set the parent of the SPI flash to SPI, since dtoc doesn't. We also
  78. * need to allocate the parent_plat since by the time this function is
  79. * called device_bind() has already gone past that step.
  80. */
  81. static int apl_flash_bind(struct udevice *dev)
  82. {
  83. if (CONFIG_IS_ENABLED(OF_PLATDATA) &&
  84. !CONFIG_IS_ENABLED(OF_PLATDATA_PARENT)) {
  85. struct dm_spi_slave_plat *plat;
  86. struct udevice *spi;
  87. int ret;
  88. ret = uclass_first_device_err(UCLASS_SPI, &spi);
  89. if (ret)
  90. return ret;
  91. dev->parent = spi;
  92. plat = calloc(sizeof(*plat), 1);
  93. if (!plat)
  94. return -ENOMEM;
  95. dev->parent_plat = plat;
  96. }
  97. return 0;
  98. }
  99. static const struct dm_spi_flash_ops apl_flash_ops = {
  100. .read = apl_flash_std_read,
  101. };
  102. static const struct udevice_id apl_flash_ids[] = {
  103. { .compatible = "jedec,spi-nor" },
  104. { }
  105. };
  106. U_BOOT_DRIVER(winbond_w25q128fw) = {
  107. .name = "winbond_w25q128fw",
  108. .id = UCLASS_SPI_FLASH,
  109. .of_match = apl_flash_ids,
  110. .bind = apl_flash_bind,
  111. .probe = apl_flash_probe,
  112. .priv_auto = sizeof(struct spi_flash),
  113. .ops = &apl_flash_ops,
  114. };
  115. /* This uses a SPI flash device to read the next phase */
  116. static int spl_fast_spi_load_image(struct spl_image_info *spl_image,
  117. struct spl_boot_device *bootdev)
  118. {
  119. ulong spl_pos = spl_get_image_pos();
  120. ulong spl_size = spl_get_image_size();
  121. struct udevice *dev;
  122. int ret;
  123. ret = uclass_first_device_err(UCLASS_SPI_FLASH, &dev);
  124. if (ret)
  125. return ret;
  126. spl_image->size = CONFIG_SYS_MONITOR_LEN; /* We don't know SPL size */
  127. spl_image->entry_point = spl_phase() == PHASE_TPL ?
  128. CONFIG_SPL_TEXT_BASE : CONFIG_SYS_TEXT_BASE;
  129. spl_image->load_addr = spl_image->entry_point;
  130. spl_image->os = IH_OS_U_BOOT;
  131. spl_image->name = "U-Boot";
  132. spl_pos &= ~0xff000000;
  133. debug("Reading from flash %lx, size %lx\n", spl_pos, spl_size);
  134. ret = spi_flash_read_dm(dev, spl_pos, spl_size,
  135. (void *)spl_image->load_addr);
  136. cpu_flush_l1d_to_l2();
  137. if (ret)
  138. return ret;
  139. return 0;
  140. }
  141. SPL_LOAD_IMAGE_METHOD("Fast SPI", 1, BOOT_DEVICE_FAST_SPI,
  142. spl_fast_spi_load_image);
  143. void board_boot_order(u32 *spl_boot_list)
  144. {
  145. bool use_spi_flash = IS_ENABLED(CONFIG_APL_BOOT_FROM_FAST_SPI_FLASH);
  146. if (use_spi_flash) {
  147. spl_boot_list[0] = BOOT_DEVICE_FAST_SPI;
  148. spl_boot_list[1] = BOOT_DEVICE_SPI_MMAP;
  149. } else {
  150. spl_boot_list[0] = BOOT_DEVICE_SPI_MMAP;
  151. spl_boot_list[1] = BOOT_DEVICE_FAST_SPI;
  152. }
  153. }
  154. #else
  155. void board_boot_order(u32 *spl_boot_list)
  156. {
  157. spl_boot_list[0] = BOOT_DEVICE_SPI_MMAP;
  158. }
  159. #endif