handoff_soc64.h 3.1 KB

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  1. /* SPDX-License-Identifier: GPL-2.0
  2. *
  3. * Copyright (C) 2016-2021 Intel Corporation <www.intel.com>
  4. *
  5. */
  6. #ifndef _HANDOFF_SOC64_H_
  7. #define _HANDOFF_SOC64_H_
  8. /*
  9. * Offset for HW handoff from Quartus tools
  10. */
  11. /* HPS handoff */
  12. #define SOC64_HANDOFF_MAGIC_BOOT 0x424F4F54
  13. #define SOC64_HANDOFF_MAGIC_MUX 0x504D5558
  14. #define SOC64_HANDOFF_MAGIC_IOCTL 0x494F4354
  15. #define SOC64_HANDOFF_MAGIC_FPGA 0x46504741
  16. #define SOC64_HANDOFF_MAGIC_DELAY 0x444C4159
  17. #define SOC64_HANDOFF_MAGIC_CLOCK 0x434C4B53
  18. #define SOC64_HANDOFF_MAGIC_MISC 0x4D495343
  19. #define SOC64_HANDOFF_OFFSET_LENGTH 0x4
  20. #define SOC64_HANDOFF_OFFSET_DATA 0x10
  21. #define SOC64_HANDOFF_SIZE 4096
  22. #if IS_ENABLED(CONFIG_TARGET_SOCFPGA_STRATIX10) || \
  23. IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX)
  24. #define SOC64_HANDOFF_BASE 0xFFE3F000
  25. #define SOC64_HANDOFF_MISC (SOC64_HANDOFF_BASE + 0x610)
  26. #elif IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X)
  27. #define SOC64_HANDOFF_BASE 0xFFE5F000
  28. #define SOC64_HANDOFF_MISC (SOC64_HANDOFF_BASE + 0x630)
  29. /* DDR handoff */
  30. #define SOC64_HANDOFF_DDR_BASE 0xFFE5C000
  31. #define SOC64_HANDOFF_DDR_MAGIC 0x48524444
  32. #define SOC64_HANDOFF_DDR_UMCTL2_MAGIC 0x4C54434D
  33. #define SOC64_HANDOFF_DDR_UMCTL2_DDR4_TYPE 0x34524444
  34. #define SOC64_HANDOFF_DDR_UMCTL2_LPDDR4_0_TYPE 0x3044504C
  35. #define SOC64_HANDOFF_DDR_UMCTL2_LPDDR4_1_TYPE 0x3144504C
  36. #define SOC64_HANDOFF_DDR_MEMRESET_BASE (SOC64_HANDOFF_DDR_BASE + 0xC)
  37. #define SOC64_HANDOFF_DDR_UMCTL2_SECTION (SOC64_HANDOFF_DDR_BASE + 0x10)
  38. #define SOC64_HANDOFF_DDR_PHY_MAGIC 0x43594850
  39. #define SOC64_HANDOFF_DDR_PHY_INIT_ENGINE_MAGIC 0x45594850
  40. #define SOC64_HANDOFF_DDR_PHY_BASE_OFFSET 0x8
  41. #define SOC64_HANDOFF_DDR_UMCTL2_TYPE_OFFSET 0x8
  42. #define SOC64_HANDOFF_DDR_UMCTL2_BASE_ADDR_OFFSET 0xC
  43. #define SOC64_HANDOFF_DDR_TRAIN_IMEM_1D_SECTION 0xFFE50000
  44. #define SOC64_HANDOFF_DDR_TRAIN_DMEM_1D_SECTION 0xFFE58000
  45. #define SOC64_HANDOFF_DDR_TRAIN_IMEM_2D_SECTION 0xFFE44000
  46. #define SOC64_HANDOFF_DDR_TRAIN_DMEM_2D_SECTION 0xFFE4C000
  47. #define SOC64_HANDOFF_DDR_TRAIN_IMEM_LENGTH SZ_32K
  48. #define SOC64_HANDOFF_DDR_TRAIN_DMEM_LENGTH SZ_16K
  49. #endif
  50. #define SOC64_HANDOFF_MUX (SOC64_HANDOFF_BASE + 0x10)
  51. #define SOC64_HANDOFF_IOCTL (SOC64_HANDOFF_BASE + 0x1A0)
  52. #define SOC64_HANDOFF_FPGA (SOC64_HANDOFF_BASE + 0x330)
  53. #define SOC64_HANDOFF_DELAY (SOC64_HANDOFF_BASE + 0x3F0)
  54. #define SOC64_HANDOFF_CLOCK (SOC64_HANDOFF_BASE + 0x580)
  55. #if IS_ENABLED(CONFIG_TARGET_SOCFPGA_STRATIX10)
  56. #define SOC64_HANDOFF_CLOCK_OSC (SOC64_HANDOFF_BASE + 0x608)
  57. #define SOC64_HANDOFF_CLOCK_FPGA (SOC64_HANDOFF_BASE + 0x60C)
  58. #else
  59. #define SOC64_HANDOFF_CLOCK_OSC (SOC64_HANDOFF_BASE + 0x5fc)
  60. #define SOC64_HANDOFF_CLOCK_FPGA (SOC64_HANDOFF_BASE + 0x600)
  61. #endif
  62. #define SOC64_HANDOFF_MUX_LEN 96
  63. #define SOC64_HANDOFF_IOCTL_LEN 96
  64. #if IS_ENABLED(CONFIG_TARGET_SOCFPGA_STRATIX10)
  65. #define SOC64_HANDOFF_FPGA_LEN 42
  66. #else
  67. #define SOC64_HANDOFF_FPGA_LEN 40
  68. #endif
  69. #define SOC64_HANDOFF_DELAY_LEN 96
  70. #ifndef __ASSEMBLY__
  71. #include <asm/types.h>
  72. enum endianness {
  73. LITTLE_ENDIAN = 0,
  74. BIG_ENDIAN,
  75. UNKNOWN_ENDIANNESS
  76. };
  77. int socfpga_get_handoff_size(void *handoff_address);
  78. int socfpga_handoff_read(void *handoff_address, void *table, u32 table_len);
  79. #endif
  80. #endif /* _HANDOFF_SOC64_H_ */