clock_manager_s10.h 5.3 KB

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  1. /* SPDX-License-Identifier: GPL-2.0
  2. *
  3. * Copyright (C) 2016-2019 Intel Corporation <www.intel.com>
  4. *
  5. */
  6. #ifndef _CLOCK_MANAGER_S10_
  7. #define _CLOCK_MANAGER_S10_
  8. #include <asm/arch/clock_manager_soc64.h>
  9. #include <linux/bitops.h>
  10. /* Clock speed accessors */
  11. unsigned long cm_get_sdram_clk_hz(void);
  12. unsigned int cm_get_l4_sp_clk_hz(void);
  13. unsigned int cm_get_mmc_controller_clk_hz(void);
  14. unsigned int cm_get_spi_controller_clk_hz(void);
  15. struct cm_config {
  16. /* main group */
  17. u32 main_pll_mpuclk;
  18. u32 main_pll_nocclk;
  19. u32 main_pll_cntr2clk;
  20. u32 main_pll_cntr3clk;
  21. u32 main_pll_cntr4clk;
  22. u32 main_pll_cntr5clk;
  23. u32 main_pll_cntr6clk;
  24. u32 main_pll_cntr7clk;
  25. u32 main_pll_cntr8clk;
  26. u32 main_pll_cntr9clk;
  27. u32 main_pll_nocdiv;
  28. u32 main_pll_pllglob;
  29. u32 main_pll_fdbck;
  30. u32 main_pll_pllc0;
  31. u32 main_pll_pllc1;
  32. u32 spare;
  33. /* peripheral group */
  34. u32 per_pll_cntr2clk;
  35. u32 per_pll_cntr3clk;
  36. u32 per_pll_cntr4clk;
  37. u32 per_pll_cntr5clk;
  38. u32 per_pll_cntr6clk;
  39. u32 per_pll_cntr7clk;
  40. u32 per_pll_cntr8clk;
  41. u32 per_pll_cntr9clk;
  42. u32 per_pll_emacctl;
  43. u32 per_pll_gpiodiv;
  44. u32 per_pll_pllglob;
  45. u32 per_pll_fdbck;
  46. u32 per_pll_pllc0;
  47. u32 per_pll_pllc1;
  48. /* incoming clock */
  49. u32 hps_osc_clk_hz;
  50. u32 fpga_clk_hz;
  51. };
  52. void cm_basic_init(const struct cm_config * const cfg);
  53. /* Control status */
  54. #define CLKMGR_S10_CTRL 0x00
  55. #define CLKMGR_S10_STAT 0x04
  56. #define CLKMGR_S10_INTRCLR 0x14
  57. /* Mainpll group */
  58. #define CLKMGR_S10_MAINPLL_EN 0x30
  59. #define CLKMGR_S10_MAINPLL_BYPASS 0x3c
  60. #define CLKMGR_S10_MAINPLL_MPUCLK 0x48
  61. #define CLKMGR_S10_MAINPLL_NOCCLK 0x4c
  62. #define CLKMGR_S10_MAINPLL_CNTR2CLK 0x50
  63. #define CLKMGR_S10_MAINPLL_CNTR3CLK 0x54
  64. #define CLKMGR_S10_MAINPLL_CNTR4CLK 0x58
  65. #define CLKMGR_S10_MAINPLL_CNTR5CLK 0x5c
  66. #define CLKMGR_S10_MAINPLL_CNTR6CLK 0x60
  67. #define CLKMGR_S10_MAINPLL_CNTR7CLK 0x64
  68. #define CLKMGR_S10_MAINPLL_CNTR8CLK 0x68
  69. #define CLKMGR_S10_MAINPLL_CNTR9CLK 0x6c
  70. #define CLKMGR_S10_MAINPLL_NOCDIV 0x70
  71. #define CLKMGR_S10_MAINPLL_PLLGLOB 0x74
  72. #define CLKMGR_S10_MAINPLL_FDBCK 0x78
  73. #define CLKMGR_S10_MAINPLL_MEMSTAT 0x80
  74. #define CLKMGR_S10_MAINPLL_PLLC0 0x84
  75. #define CLKMGR_S10_MAINPLL_PLLC1 0x88
  76. #define CLKMGR_S10_MAINPLL_VCOCALIB 0x8c
  77. /* Periphpll group */
  78. #define CLKMGR_S10_PERPLL_EN 0xa4
  79. #define CLKMGR_S10_PERPLL_BYPASS 0xb0
  80. #define CLKMGR_S10_PERPLL_CNTR2CLK 0xbc
  81. #define CLKMGR_S10_PERPLL_CNTR3CLK 0xc0
  82. #define CLKMGR_S10_PERPLL_CNTR4CLK 0xc4
  83. #define CLKMGR_S10_PERPLL_CNTR5CLK 0xc8
  84. #define CLKMGR_S10_PERPLL_CNTR6CLK 0xcc
  85. #define CLKMGR_S10_PERPLL_CNTR7CLK 0xd0
  86. #define CLKMGR_S10_PERPLL_CNTR8CLK 0xd4
  87. #define CLKMGR_S10_PERPLL_CNTR9CLK 0xd8
  88. #define CLKMGR_S10_PERPLL_EMACCTL 0xdc
  89. #define CLKMGR_S10_PERPLL_GPIODIV 0xe0
  90. #define CLKMGR_S10_PERPLL_PLLGLOB 0xe4
  91. #define CLKMGR_S10_PERPLL_FDBCK 0xe8
  92. #define CLKMGR_S10_PERPLL_MEMSTAT 0xf0
  93. #define CLKMGR_S10_PERPLL_PLLC0 0xf4
  94. #define CLKMGR_S10_PERPLL_PLLC1 0xf8
  95. #define CLKMGR_S10_PERPLL_VCOCALIB 0xfc
  96. #define CLKMGR_STAT CLKMGR_S10_STAT
  97. #define CLKMGR_INTER CLKMGR_S10_INTER
  98. #define CLKMGR_PERPLL_EN CLKMGR_S10_PERPLL_EN
  99. #define CLKMGR_CTRL_SAFEMODE BIT(0)
  100. #define CLKMGR_BYPASS_MAINPLL_ALL 0x00000007
  101. #define CLKMGR_BYPASS_PERPLL_ALL 0x0000007f
  102. #define CLKMGR_INTER_MAINPLLLOCKED_MASK 0x00000001
  103. #define CLKMGR_INTER_PERPLLLOCKED_MASK 0x00000002
  104. #define CLKMGR_INTER_MAINPLLLOST_MASK 0x00000004
  105. #define CLKMGR_INTER_PERPLLLOST_MASK 0x00000008
  106. #define CLKMGR_STAT_BUSY BIT(0)
  107. #define CLKMGR_STAT_MAINPLL_LOCKED BIT(8)
  108. #define CLKMGR_STAT_PERPLL_LOCKED BIT(9)
  109. #define CLKMGR_PLLGLOB_PD_MASK 0x00000001
  110. #define CLKMGR_PLLGLOB_RST_MASK 0x00000002
  111. #define CLKMGR_PLLGLOB_VCO_PSRC_MASK 0X3
  112. #define CLKMGR_PLLGLOB_VCO_PSRC_OFFSET 16
  113. #define CLKMGR_VCO_PSRC_EOSC1 0
  114. #define CLKMGR_VCO_PSRC_INTOSC 1
  115. #define CLKMGR_VCO_PSRC_F2S 2
  116. #define CLKMGR_PLLGLOB_REFCLKDIV_MASK 0X3f
  117. #define CLKMGR_PLLGLOB_REFCLKDIV_OFFSET 8
  118. #define CLKMGR_CLKSRC_MASK 0x7
  119. #define CLKMGR_CLKSRC_OFFSET 16
  120. #define CLKMGR_CLKSRC_MAIN 0
  121. #define CLKMGR_CLKSRC_PER 1
  122. #define CLKMGR_CLKSRC_OSC1 2
  123. #define CLKMGR_CLKSRC_INTOSC 3
  124. #define CLKMGR_CLKSRC_FPGA 4
  125. #define CLKMGR_CLKCNT_MSK 0x7ff
  126. #define CLKMGR_FDBCK_MDIV_MASK 0xff
  127. #define CLKMGR_FDBCK_MDIV_OFFSET 24
  128. #define CLKMGR_PLLC0_DIV_MASK 0xff
  129. #define CLKMGR_PLLC1_DIV_MASK 0xff
  130. #define CLKMGR_PLLC0_EN_OFFSET 27
  131. #define CLKMGR_PLLC1_EN_OFFSET 24
  132. #define CLKMGR_NOCDIV_L4MAIN_OFFSET 0
  133. #define CLKMGR_NOCDIV_L4MPCLK_OFFSET 8
  134. #define CLKMGR_NOCDIV_L4SPCLK_OFFSET 16
  135. #define CLKMGR_NOCDIV_CSATCLK_OFFSET 24
  136. #define CLKMGR_NOCDIV_CSTRACECLK_OFFSET 26
  137. #define CLKMGR_NOCDIV_CSPDBGCLK_OFFSET 28
  138. #define CLKMGR_NOCDIV_L4SPCLK_MASK 0X3
  139. #define CLKMGR_NOCDIV_DIV1 0
  140. #define CLKMGR_NOCDIV_DIV2 1
  141. #define CLKMGR_NOCDIV_DIV4 2
  142. #define CLKMGR_NOCDIV_DIV8 3
  143. #define CLKMGR_CSPDBGCLK_DIV1 0
  144. #define CLKMGR_CSPDBGCLK_DIV4 1
  145. #define CLKMGR_MSCNT_CONST 200
  146. #define CLKMGR_MDIV_CONST 6
  147. #define CLKMGR_HSCNT_CONST 9
  148. #define CLKMGR_VCOCALIB_MSCNT_MASK 0xff
  149. #define CLKMGR_VCOCALIB_MSCNT_OFFSET 9
  150. #define CLKMGR_VCOCALIB_HSCNT_MASK 0xff
  151. #define CLKMGR_EMACCTL_EMAC0SEL_OFFSET 26
  152. #define CLKMGR_EMACCTL_EMAC1SEL_OFFSET 27
  153. #define CLKMGR_EMACCTL_EMAC2SEL_OFFSET 28
  154. #define CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK 0x00000020
  155. #endif /* _CLOCK_MANAGER_S10_ */