imx7d-smegw01.dts 4.6 KB

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  1. // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  2. //
  3. // Copyright (C) 2020 PHYTEC Messtechnik GmbH
  4. // Author: Jens Lang <J.Lang@phytec.de>
  5. // Copyright (C) 2021 Fabio Estevam <festevam@denx.de>
  6. /dts-v1/;
  7. #include "imx7d.dtsi"
  8. / {
  9. model = "Storopack SMEGW01 board";
  10. compatible = "storopack,imx7d-smegw01", "fsl,imx7d";
  11. aliases {
  12. mmc0 = &usdhc1;
  13. mmc1 = &usdhc3;
  14. };
  15. chosen {
  16. stdout-path = &uart1;
  17. };
  18. memory@80000000 {
  19. device_type = "memory";
  20. reg = <0x80000000 0x20000000>;
  21. };
  22. };
  23. &fec1 {
  24. pinctrl-names = "default";
  25. pinctrl-0 = <&pinctrl_enet1>;
  26. assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
  27. <&clks IMX7D_ENET1_TIME_ROOT_CLK>;
  28. assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
  29. assigned-clock-rates = <0>, <100000000>;
  30. phy-mode = "rgmii-id";
  31. phy-handle = <&ethphy0>;
  32. fsl,magic-packet;
  33. status = "okay";
  34. mdio: mdio {
  35. #address-cells = <1>;
  36. #size-cells = <0>;
  37. ethphy0: ethernet-phy@1 {
  38. compatible = "ethernet-phy-ieee802.3-c22";
  39. reg = <1>;
  40. };
  41. };
  42. };
  43. &uart1 {
  44. pinctrl-names = "default";
  45. pinctrl-0 = <&pinctrl_uart1>;
  46. status = "okay";
  47. };
  48. &usdhc1 {
  49. pinctrl-names = "default";
  50. pinctrl-0 = <&pinctrl_usdhc1>;
  51. cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
  52. no-1-8-v;
  53. enable-sdio-wakeup;
  54. keep-power-in-suspend;
  55. status = "okay";
  56. };
  57. &usdhc3 {
  58. pinctrl-names = "default", "state_100mhz", "state_200mhz";
  59. pinctrl-0 = <&pinctrl_usdhc3>;
  60. pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
  61. pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
  62. assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>;
  63. assigned-clock-rates = <400000000>;
  64. max-frequency = <200000000>;
  65. bus-width = <8>;
  66. fsl,tuning-step = <1>;
  67. non-removable;
  68. cap-sd-highspeed;
  69. cap-mmc-highspeed;
  70. cap-mmc-hw-reset;
  71. mmc-hs200-1_8v;
  72. mmc-ddr-1_8v;
  73. sd-uhs-ddr50;
  74. sd-uhs-sdr104;
  75. status = "okay";
  76. };
  77. &wdog1 {
  78. pinctrl-names = "default";
  79. pinctrl-0 = <&pinctrl_wdog>;
  80. fsl,ext-reset-output;
  81. status = "okay";
  82. };
  83. &iomuxc {
  84. pinctrl_enet1: enet1grp {
  85. fsl,pins = <
  86. MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x5
  87. MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x5
  88. MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x5
  89. MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x5
  90. MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x5
  91. MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x5
  92. MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x5
  93. MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x5
  94. MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x5
  95. MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x5
  96. MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x5
  97. MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x5
  98. MX7D_PAD_GPIO1_IO10__ENET1_MDIO 0x7
  99. MX7D_PAD_GPIO1_IO11__ENET1_MDC 0x7
  100. >;
  101. };
  102. pinctrl_uart1: uart1grp {
  103. fsl,pins = <
  104. MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX 0x74
  105. MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX 0x7c
  106. >;
  107. };
  108. pinctrl_usdhc1: usdhc1 {
  109. fsl,pins = <
  110. MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x59
  111. MX7D_PAD_SD1_CMD__SD1_CMD 0x59
  112. MX7D_PAD_SD1_CLK__SD1_CLK 0x19
  113. MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59
  114. MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59
  115. MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59
  116. MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59
  117. >;
  118. };
  119. pinctrl_usdhc3: usdhc3 {
  120. fsl,pins = <
  121. MX7D_PAD_SD3_CMD__SD3_CMD 0x5d
  122. MX7D_PAD_SD3_CLK__SD3_CLK 0x1d
  123. MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5d
  124. MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5d
  125. MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5d
  126. MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5d
  127. MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5d
  128. MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5d
  129. MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5d
  130. MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5d
  131. MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1d
  132. >;
  133. };
  134. pinctrl_usdhc3_100mhz: usdhc3_100mhz {
  135. fsl,pins = <
  136. MX7D_PAD_SD3_CMD__SD3_CMD 0x5e
  137. MX7D_PAD_SD3_CLK__SD3_CLK 0x1e
  138. MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5e
  139. MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5e
  140. MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5e
  141. MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5e
  142. MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5e
  143. MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5e
  144. MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5e
  145. MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5e
  146. MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1e
  147. >;
  148. };
  149. pinctrl_usdhc3_200mhz: usdhc3_200mhz {
  150. fsl,pins = <
  151. MX7D_PAD_SD3_CMD__SD3_CMD 0x5f
  152. MX7D_PAD_SD3_CLK__SD3_CLK 0x0f
  153. MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5f
  154. MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5f
  155. MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5f
  156. MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5f
  157. MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5f
  158. MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5f
  159. MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5f
  160. MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5f
  161. MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1f
  162. >;
  163. };
  164. };
  165. &iomuxc_lpsr {
  166. pinctrl_wdog: wdoggrp {
  167. fsl,pins = <
  168. MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x74
  169. >;
  170. };
  171. };