k3-j721e-common-proc-board-u-boot.dtsi 3.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
  4. */
  5. #include <dt-bindings/net/ti-dp83867.h>
  6. / {
  7. chosen {
  8. stdout-path = "serial2:115200n8";
  9. tick-timer = &timer1;
  10. };
  11. aliases {
  12. ethernet0 = &cpsw_port1;
  13. };
  14. };
  15. &cbass_main{
  16. u-boot,dm-spl;
  17. };
  18. &cbass_mcu_wakeup {
  19. u-boot,dm-spl;
  20. timer1: timer@40400000 {
  21. compatible = "ti,omap5430-timer";
  22. reg = <0x0 0x40400000 0x0 0x80>;
  23. ti,timer-alwon;
  24. clock-frequency = <25000000>;
  25. u-boot,dm-spl;
  26. };
  27. mcu_navss {
  28. u-boot,dm-spl;
  29. ringacc@2b800000 {
  30. u-boot,dm-spl;
  31. };
  32. dma-controller@285c0000 {
  33. u-boot,dm-spl;
  34. };
  35. };
  36. };
  37. &secure_proxy_main {
  38. u-boot,dm-spl;
  39. };
  40. &dmsc {
  41. u-boot,dm-spl;
  42. k3_sysreset: sysreset-controller {
  43. compatible = "ti,sci-sysreset";
  44. u-boot,dm-spl;
  45. };
  46. };
  47. &k3_pds {
  48. u-boot,dm-spl;
  49. };
  50. &k3_clks {
  51. u-boot,dm-spl;
  52. };
  53. &k3_reset {
  54. u-boot,dm-spl;
  55. };
  56. &wkup_pmx0 {
  57. u-boot,dm-spl;
  58. mcu_cpsw_pins_default: mcu_cpsw_pins_default {
  59. pinctrl-single,pins = <
  60. J721E_WKUP_IOPAD(0x0058, PIN_OUTPUT, 0) /* (N4) MCU_RGMII1_TX_CTL */
  61. J721E_WKUP_IOPAD(0x005c, PIN_INPUT, 0) /* (N5) MCU_RGMII1_RX_CTL */
  62. J721E_WKUP_IOPAD(0x0060, PIN_OUTPUT, 0) /* (M2) MCU_RGMII1_TD3 */
  63. J721E_WKUP_IOPAD(0x0064, PIN_OUTPUT, 0) /* (M3) MCU_RGMII1_TD2 */
  64. J721E_WKUP_IOPAD(0x0068, PIN_OUTPUT, 0) /* (M4) MCU_RGMII1_TD1 */
  65. J721E_WKUP_IOPAD(0x006c, PIN_OUTPUT, 0) /* (M5) MCU_RGMII1_TD0 */
  66. J721E_WKUP_IOPAD(0x0078, PIN_INPUT, 0) /* (L2) MCU_RGMII1_RD3 */
  67. J721E_WKUP_IOPAD(0x007c, PIN_INPUT, 0) /* (L5) MCU_RGMII1_RD2 */
  68. J721E_WKUP_IOPAD(0x0080, PIN_INPUT, 0) /* (M6) MCU_RGMII1_RD1 */
  69. J721E_WKUP_IOPAD(0x0084, PIN_INPUT, 0) /* (L6) MCU_RGMII1_RD0 */
  70. J721E_WKUP_IOPAD(0x0070, PIN_INPUT, 0) /* (N1) MCU_RGMII1_TXC */
  71. J721E_WKUP_IOPAD(0x0074, PIN_INPUT, 0) /* (M1) MCU_RGMII1_RXC */
  72. >;
  73. };
  74. mcu_mdio_pins_default: mcu_mdio1_pins_default {
  75. pinctrl-single,pins = <
  76. J721E_WKUP_IOPAD(0x008c, PIN_OUTPUT, 0) /* (L1) MCU_MDIO0_MDC */
  77. J721E_WKUP_IOPAD(0x0088, PIN_INPUT, 0) /* (L4) MCU_MDIO0_MDIO */
  78. >;
  79. };
  80. };
  81. &main_pmx0 {
  82. u-boot,dm-spl;
  83. };
  84. &main_uart0 {
  85. u-boot,dm-spl;
  86. };
  87. &mcu_uart0 {
  88. u-boot,dm-spl;
  89. };
  90. &main_sdhci0 {
  91. u-boot,dm-spl;
  92. };
  93. &main_sdhci1 {
  94. u-boot,dm-spl;
  95. };
  96. &main_usbss0_pins_default {
  97. u-boot,dm-spl;
  98. };
  99. &usbss0 {
  100. u-boot,dm-spl;
  101. ti,usb2-only;
  102. };
  103. &usb0 {
  104. dr_mode = "peripheral";
  105. u-boot,dm-spl;
  106. };
  107. &mcu_cpsw {
  108. pinctrl-names = "default";
  109. pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>;
  110. };
  111. &davinci_mdio {
  112. phy0: ethernet-phy@0 {
  113. reg = <0>;
  114. ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
  115. ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
  116. };
  117. };
  118. &cpsw_port1 {
  119. phy-mode = "rgmii-rxid";
  120. phy-handle = <&phy0>;
  121. };
  122. &mcu_cpsw {
  123. reg = <0x0 0x46000000 0x0 0x200000>,
  124. <0x0 0x40f00200 0x0 0x2>;
  125. reg-names = "cpsw_nuss", "mac_efuse";
  126. /delete-property/ ranges;
  127. cpsw-phy-sel@40f04040 {
  128. compatible = "ti,am654-cpsw-phy-sel";
  129. reg= <0x0 0x40f04040 0x0 0x4>;
  130. reg-names = "gmii-sel";
  131. };
  132. };
  133. &main_mmc1_pins_default {
  134. u-boot,dm-spl;
  135. };
  136. &wkup_i2c0_pins_default {
  137. u-boot,dm-spl;
  138. };
  139. &wkup_i2c0 {
  140. u-boot,dm-spl;
  141. };
  142. &main_i2c0 {
  143. u-boot,dm-spl;
  144. };
  145. &main_i2c0_pins_default {
  146. u-boot,dm-spl;
  147. };
  148. &exp2 {
  149. u-boot,dm-spl;
  150. };
  151. &mcu_fss0_ospi0_pins_default {
  152. u-boot,dm-spl;
  153. };
  154. &fss {
  155. u-boot,dm-spl;
  156. };
  157. &ospi0 {
  158. u-boot,dm-spl;
  159. flash@0 {
  160. u-boot,dm-spl;
  161. };
  162. };
  163. &ospi1 {
  164. u-boot,dm-spl;
  165. flash@0 {
  166. u-boot,dm-spl;
  167. };
  168. };
  169. &mcu_fss0_ospi1_pins_default {
  170. u-boot,dm-spl;
  171. };