// SPDX-License-Identifier: GPL-2.0 /* * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ */ #include / { chosen { stdout-path = "serial2:115200n8"; tick-timer = &timer1; }; aliases { ethernet0 = &cpsw_port1; }; }; &cbass_main{ u-boot,dm-spl; }; &cbass_mcu_wakeup { u-boot,dm-spl; timer1: timer@40400000 { compatible = "ti,omap5430-timer"; reg = <0x0 0x40400000 0x0 0x80>; ti,timer-alwon; clock-frequency = <25000000>; u-boot,dm-spl; }; mcu_navss { u-boot,dm-spl; ringacc@2b800000 { u-boot,dm-spl; }; dma-controller@285c0000 { u-boot,dm-spl; }; }; }; &secure_proxy_main { u-boot,dm-spl; }; &dmsc { u-boot,dm-spl; k3_sysreset: sysreset-controller { compatible = "ti,sci-sysreset"; u-boot,dm-spl; }; }; &k3_pds { u-boot,dm-spl; }; &k3_clks { u-boot,dm-spl; }; &k3_reset { u-boot,dm-spl; }; &wkup_pmx0 { u-boot,dm-spl; mcu_cpsw_pins_default: mcu_cpsw_pins_default { pinctrl-single,pins = < J721E_WKUP_IOPAD(0x0058, PIN_OUTPUT, 0) /* (N4) MCU_RGMII1_TX_CTL */ J721E_WKUP_IOPAD(0x005c, PIN_INPUT, 0) /* (N5) MCU_RGMII1_RX_CTL */ J721E_WKUP_IOPAD(0x0060, PIN_OUTPUT, 0) /* (M2) MCU_RGMII1_TD3 */ J721E_WKUP_IOPAD(0x0064, PIN_OUTPUT, 0) /* (M3) MCU_RGMII1_TD2 */ J721E_WKUP_IOPAD(0x0068, PIN_OUTPUT, 0) /* (M4) MCU_RGMII1_TD1 */ J721E_WKUP_IOPAD(0x006c, PIN_OUTPUT, 0) /* (M5) MCU_RGMII1_TD0 */ J721E_WKUP_IOPAD(0x0078, PIN_INPUT, 0) /* (L2) MCU_RGMII1_RD3 */ J721E_WKUP_IOPAD(0x007c, PIN_INPUT, 0) /* (L5) MCU_RGMII1_RD2 */ J721E_WKUP_IOPAD(0x0080, PIN_INPUT, 0) /* (M6) MCU_RGMII1_RD1 */ J721E_WKUP_IOPAD(0x0084, PIN_INPUT, 0) /* (L6) MCU_RGMII1_RD0 */ J721E_WKUP_IOPAD(0x0070, PIN_INPUT, 0) /* (N1) MCU_RGMII1_TXC */ J721E_WKUP_IOPAD(0x0074, PIN_INPUT, 0) /* (M1) MCU_RGMII1_RXC */ >; }; mcu_mdio_pins_default: mcu_mdio1_pins_default { pinctrl-single,pins = < J721E_WKUP_IOPAD(0x008c, PIN_OUTPUT, 0) /* (L1) MCU_MDIO0_MDC */ J721E_WKUP_IOPAD(0x0088, PIN_INPUT, 0) /* (L4) MCU_MDIO0_MDIO */ >; }; }; &main_pmx0 { u-boot,dm-spl; }; &main_uart0 { u-boot,dm-spl; }; &mcu_uart0 { u-boot,dm-spl; }; &main_sdhci0 { u-boot,dm-spl; }; &main_sdhci1 { u-boot,dm-spl; }; &main_usbss0_pins_default { u-boot,dm-spl; }; &usbss0 { u-boot,dm-spl; ti,usb2-only; }; &usb0 { dr_mode = "peripheral"; u-boot,dm-spl; }; &mcu_cpsw { pinctrl-names = "default"; pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>; }; &davinci_mdio { phy0: ethernet-phy@0 { reg = <0>; ti,rx-internal-delay = ; ti,fifo-depth = ; }; }; &cpsw_port1 { phy-mode = "rgmii-rxid"; phy-handle = <&phy0>; }; &mcu_cpsw { reg = <0x0 0x46000000 0x0 0x200000>, <0x0 0x40f00200 0x0 0x2>; reg-names = "cpsw_nuss", "mac_efuse"; /delete-property/ ranges; cpsw-phy-sel@40f04040 { compatible = "ti,am654-cpsw-phy-sel"; reg= <0x0 0x40f04040 0x0 0x4>; reg-names = "gmii-sel"; }; }; &main_mmc1_pins_default { u-boot,dm-spl; }; &wkup_i2c0_pins_default { u-boot,dm-spl; }; &wkup_i2c0 { u-boot,dm-spl; }; &main_i2c0 { u-boot,dm-spl; }; &main_i2c0_pins_default { u-boot,dm-spl; }; &exp2 { u-boot,dm-spl; }; &mcu_fss0_ospi0_pins_default { u-boot,dm-spl; }; &fss { u-boot,dm-spl; }; &ospi0 { u-boot,dm-spl; flash@0 { u-boot,dm-spl; }; }; &ospi1 { u-boot,dm-spl; flash@0 { u-boot,dm-spl; }; }; &mcu_fss0_ospi1_pins_default { u-boot,dm-spl; };