bsec.c 13 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
  4. */
  5. #define LOG_CATEGORY UCLASS_MISC
  6. #include <common.h>
  7. #include <clk.h>
  8. #include <dm.h>
  9. #include <log.h>
  10. #include <misc.h>
  11. #include <asm/io.h>
  12. #include <asm/arch/bsec.h>
  13. #include <asm/arch/stm32mp1_smc.h>
  14. #include <dm/device_compat.h>
  15. #include <linux/arm-smccc.h>
  16. #include <linux/iopoll.h>
  17. #define BSEC_OTP_MAX_VALUE 95
  18. #define BSEC_TIMEOUT_US 10000
  19. /* BSEC REGISTER OFFSET (base relative) */
  20. #define BSEC_OTP_CONF_OFF 0x000
  21. #define BSEC_OTP_CTRL_OFF 0x004
  22. #define BSEC_OTP_WRDATA_OFF 0x008
  23. #define BSEC_OTP_STATUS_OFF 0x00C
  24. #define BSEC_OTP_LOCK_OFF 0x010
  25. #define BSEC_DENABLE_OFF 0x014
  26. #define BSEC_DISTURBED_OFF 0x01C
  27. #define BSEC_ERROR_OFF 0x034
  28. #define BSEC_WRLOCK_OFF 0x04C /* OTP write permananet lock */
  29. #define BSEC_SPLOCK_OFF 0x064 /* OTP write sticky lock */
  30. #define BSEC_SWLOCK_OFF 0x07C /* shadow write sticky lock */
  31. #define BSEC_SRLOCK_OFF 0x094 /* shadow read sticky lock */
  32. #define BSEC_OTP_DATA_OFF 0x200
  33. /* BSEC_CONFIGURATION Register MASK */
  34. #define BSEC_CONF_POWER_UP 0x001
  35. /* BSEC_CONTROL Register */
  36. #define BSEC_READ 0x000
  37. #define BSEC_WRITE 0x100
  38. /* LOCK Register */
  39. #define OTP_LOCK_MASK 0x1F
  40. #define OTP_LOCK_BANK_SHIFT 0x05
  41. #define OTP_LOCK_BIT_MASK 0x01
  42. /* STATUS Register */
  43. #define BSEC_MODE_BUSY_MASK 0x08
  44. #define BSEC_MODE_PROGFAIL_MASK 0x10
  45. #define BSEC_MODE_PWR_MASK 0x20
  46. /* DENABLE Register */
  47. #define BSEC_DENABLE_DBGSWENABLE BIT(10)
  48. /*
  49. * OTP Lock services definition
  50. * Value must corresponding to the bit number in the register
  51. */
  52. #define BSEC_LOCK_PROGRAM 0x04
  53. /**
  54. * bsec_lock() - manage lock for each type SR/SP/SW
  55. * @address: address of bsec IP register
  56. * @otp: otp number (0 - BSEC_OTP_MAX_VALUE)
  57. * Return: true if locked else false
  58. */
  59. static bool bsec_read_lock(u32 address, u32 otp)
  60. {
  61. u32 bit;
  62. u32 bank;
  63. bit = 1 << (otp & OTP_LOCK_MASK);
  64. bank = ((otp >> OTP_LOCK_BANK_SHIFT) & OTP_LOCK_MASK) * sizeof(u32);
  65. return !!(readl(address + bank) & bit);
  66. }
  67. /**
  68. * bsec_check_error() - Check status of one otp
  69. * @base: base address of bsec IP
  70. * @otp: otp number (0 - BSEC_OTP_MAX_VALUE)
  71. * Return: 0 if no error, -EAGAIN or -ENOTSUPP
  72. */
  73. static u32 bsec_check_error(u32 base, u32 otp)
  74. {
  75. u32 bit;
  76. u32 bank;
  77. bit = 1 << (otp & OTP_LOCK_MASK);
  78. bank = ((otp >> OTP_LOCK_BANK_SHIFT) & OTP_LOCK_MASK) * sizeof(u32);
  79. if (readl(base + BSEC_DISTURBED_OFF + bank) & bit)
  80. return -EAGAIN;
  81. else if (readl(base + BSEC_ERROR_OFF + bank) & bit)
  82. return -ENOTSUPP;
  83. return 0;
  84. }
  85. /**
  86. * bsec_read_SR_lock() - read SR lock (Shadowing)
  87. * @base: base address of bsec IP
  88. * @otp: otp number (0 - BSEC_OTP_MAX_VALUE)
  89. * Return: true if locked else false
  90. */
  91. static bool bsec_read_SR_lock(u32 base, u32 otp)
  92. {
  93. return bsec_read_lock(base + BSEC_SRLOCK_OFF, otp);
  94. }
  95. /**
  96. * bsec_read_SP_lock() - read SP lock (program Lock)
  97. * @base: base address of bsec IP
  98. * @otp: otp number (0 - BSEC_OTP_MAX_VALUE)
  99. * Return: true if locked else false
  100. */
  101. static bool bsec_read_SP_lock(u32 base, u32 otp)
  102. {
  103. return bsec_read_lock(base + BSEC_SPLOCK_OFF, otp);
  104. }
  105. /**
  106. * bsec_SW_lock() - manage SW lock (Write in Shadow)
  107. * @base: base address of bsec IP
  108. * @otp: otp number (0 - BSEC_OTP_MAX_VALUE)
  109. * Return: true if locked else false
  110. */
  111. static bool bsec_read_SW_lock(u32 base, u32 otp)
  112. {
  113. return bsec_read_lock(base + BSEC_SWLOCK_OFF, otp);
  114. }
  115. /**
  116. * bsec_power_safmem() - Activate or deactivate safmem power
  117. * @base: base address of bsec IP
  118. * @power: true to power up , false to power down
  119. * Return: 0 if succeed
  120. */
  121. static int bsec_power_safmem(u32 base, bool power)
  122. {
  123. u32 val;
  124. u32 mask;
  125. if (power) {
  126. setbits_le32(base + BSEC_OTP_CONF_OFF, BSEC_CONF_POWER_UP);
  127. mask = BSEC_MODE_PWR_MASK;
  128. } else {
  129. clrbits_le32(base + BSEC_OTP_CONF_OFF, BSEC_CONF_POWER_UP);
  130. mask = 0;
  131. }
  132. /* waiting loop */
  133. return readl_poll_timeout(base + BSEC_OTP_STATUS_OFF,
  134. val, (val & BSEC_MODE_PWR_MASK) == mask,
  135. BSEC_TIMEOUT_US);
  136. }
  137. /**
  138. * bsec_shadow_register() - copy safmen otp to bsec data
  139. * @base: base address of bsec IP
  140. * @otp: otp number (0 - BSEC_OTP_MAX_VALUE)
  141. * Return: 0 if no error
  142. */
  143. static int bsec_shadow_register(struct udevice *dev, u32 base, u32 otp)
  144. {
  145. u32 val;
  146. int ret;
  147. bool power_up = false;
  148. /* check if shadowing of otp is locked */
  149. if (bsec_read_SR_lock(base, otp))
  150. dev_dbg(dev, "OTP %d is locked and refreshed with 0\n",
  151. otp);
  152. /* check if safemem is power up */
  153. val = readl(base + BSEC_OTP_STATUS_OFF);
  154. if (!(val & BSEC_MODE_PWR_MASK)) {
  155. ret = bsec_power_safmem(base, true);
  156. if (ret)
  157. return ret;
  158. power_up = true;
  159. }
  160. /* set BSEC_OTP_CTRL_OFF with the otp value*/
  161. writel(otp | BSEC_READ, base + BSEC_OTP_CTRL_OFF);
  162. /* check otp status*/
  163. ret = readl_poll_timeout(base + BSEC_OTP_STATUS_OFF,
  164. val, (val & BSEC_MODE_BUSY_MASK) == 0,
  165. BSEC_TIMEOUT_US);
  166. if (ret)
  167. return ret;
  168. ret = bsec_check_error(base, otp);
  169. if (power_up)
  170. bsec_power_safmem(base, false);
  171. return ret;
  172. }
  173. /**
  174. * bsec_read_shadow() - read an otp data value from shadow
  175. * @base: base address of bsec IP
  176. * @val: read value
  177. * @otp: otp number (0 - BSEC_OTP_MAX_VALUE)
  178. * Return: 0 if no error
  179. */
  180. static int bsec_read_shadow(struct udevice *dev, u32 base, u32 *val, u32 otp)
  181. {
  182. *val = readl(base + BSEC_OTP_DATA_OFF + otp * sizeof(u32));
  183. return bsec_check_error(base, otp);
  184. }
  185. /**
  186. * bsec_write_shadow() - write value in BSEC data register in shadow
  187. * @base: base address of bsec IP
  188. * @val: value to write
  189. * @otp: otp number (0 - BSEC_OTP_MAX_VALUE)
  190. * Return: 0 if no error
  191. */
  192. static int bsec_write_shadow(struct udevice *dev, u32 base, u32 val, u32 otp)
  193. {
  194. /* check if programming of otp is locked */
  195. if (bsec_read_SW_lock(base, otp))
  196. dev_dbg(dev, "OTP %d is lock, write will be ignore\n", otp);
  197. writel(val, base + BSEC_OTP_DATA_OFF + otp * sizeof(u32));
  198. return bsec_check_error(base, otp);
  199. }
  200. /**
  201. * bsec_program_otp() - program a bit in SAFMEM
  202. * @base: base address of bsec IP
  203. * @val: value to program
  204. * @otp: otp number (0 - BSEC_OTP_MAX_VALUE)
  205. * after the function the otp data is not refreshed in shadow
  206. * Return: 0 if no error
  207. */
  208. static int bsec_program_otp(struct udevice *dev, long base, u32 val, u32 otp)
  209. {
  210. u32 ret;
  211. bool power_up = false;
  212. if (bsec_read_SP_lock(base, otp))
  213. dev_dbg(dev, "OTP %d locked, prog will be ignore\n", otp);
  214. if (readl(base + BSEC_OTP_LOCK_OFF) & (1 << BSEC_LOCK_PROGRAM))
  215. dev_dbg(dev, "Global lock, prog will be ignore\n");
  216. /* check if safemem is power up */
  217. if (!(readl(base + BSEC_OTP_STATUS_OFF) & BSEC_MODE_PWR_MASK)) {
  218. ret = bsec_power_safmem(base, true);
  219. if (ret)
  220. return ret;
  221. power_up = true;
  222. }
  223. /* set value in write register*/
  224. writel(val, base + BSEC_OTP_WRDATA_OFF);
  225. /* set BSEC_OTP_CTRL_OFF with the otp value */
  226. writel(otp | BSEC_WRITE, base + BSEC_OTP_CTRL_OFF);
  227. /* check otp status*/
  228. ret = readl_poll_timeout(base + BSEC_OTP_STATUS_OFF,
  229. val, (val & BSEC_MODE_BUSY_MASK) == 0,
  230. BSEC_TIMEOUT_US);
  231. if (ret)
  232. return ret;
  233. if (val & BSEC_MODE_PROGFAIL_MASK)
  234. ret = -EACCES;
  235. else
  236. ret = bsec_check_error(base, otp);
  237. if (power_up)
  238. bsec_power_safmem(base, false);
  239. return ret;
  240. }
  241. /* BSEC MISC driver *******************************************************/
  242. struct stm32mp_bsec_plat {
  243. u32 base;
  244. };
  245. static int stm32mp_bsec_read_otp(struct udevice *dev, u32 *val, u32 otp)
  246. {
  247. struct stm32mp_bsec_plat *plat;
  248. u32 tmp_data = 0;
  249. int ret;
  250. if (IS_ENABLED(CONFIG_TFABOOT))
  251. return stm32_smc(STM32_SMC_BSEC,
  252. STM32_SMC_READ_OTP,
  253. otp, 0, val);
  254. plat = dev_get_plat(dev);
  255. /* read current shadow value */
  256. ret = bsec_read_shadow(dev, plat->base, &tmp_data, otp);
  257. if (ret)
  258. return ret;
  259. /* copy otp in shadow */
  260. ret = bsec_shadow_register(dev, plat->base, otp);
  261. if (ret)
  262. return ret;
  263. ret = bsec_read_shadow(dev, plat->base, val, otp);
  264. if (ret)
  265. return ret;
  266. /* restore shadow value */
  267. ret = bsec_write_shadow(dev, plat->base, tmp_data, otp);
  268. return ret;
  269. }
  270. static int stm32mp_bsec_read_shadow(struct udevice *dev, u32 *val, u32 otp)
  271. {
  272. struct stm32mp_bsec_plat *plat;
  273. if (IS_ENABLED(CONFIG_TFABOOT))
  274. return stm32_smc(STM32_SMC_BSEC,
  275. STM32_SMC_READ_SHADOW,
  276. otp, 0, val);
  277. plat = dev_get_plat(dev);
  278. return bsec_read_shadow(dev, plat->base, val, otp);
  279. }
  280. static int stm32mp_bsec_read_lock(struct udevice *dev, u32 *val, u32 otp)
  281. {
  282. struct stm32mp_bsec_plat *plat = dev_get_plat(dev);
  283. /* return OTP permanent write lock status */
  284. *val = bsec_read_lock(plat->base + BSEC_WRLOCK_OFF, otp);
  285. return 0;
  286. }
  287. static int stm32mp_bsec_write_otp(struct udevice *dev, u32 val, u32 otp)
  288. {
  289. struct stm32mp_bsec_plat *plat;
  290. if (IS_ENABLED(CONFIG_TFABOOT))
  291. return stm32_smc_exec(STM32_SMC_BSEC,
  292. STM32_SMC_PROG_OTP,
  293. otp, val);
  294. plat = dev_get_plat(dev);
  295. return bsec_program_otp(dev, plat->base, val, otp);
  296. }
  297. static int stm32mp_bsec_write_shadow(struct udevice *dev, u32 val, u32 otp)
  298. {
  299. struct stm32mp_bsec_plat *plat;
  300. if (IS_ENABLED(CONFIG_TFABOOT))
  301. return stm32_smc_exec(STM32_SMC_BSEC,
  302. STM32_SMC_WRITE_SHADOW,
  303. otp, val);
  304. plat = dev_get_plat(dev);
  305. return bsec_write_shadow(dev, plat->base, val, otp);
  306. }
  307. static int stm32mp_bsec_write_lock(struct udevice *dev, u32 val, u32 otp)
  308. {
  309. if (!IS_ENABLED(CONFIG_TFABOOT))
  310. return -ENOTSUPP;
  311. if (val == 1)
  312. return stm32_smc_exec(STM32_SMC_BSEC,
  313. STM32_SMC_WRLOCK_OTP,
  314. otp, 0);
  315. if (val == 0)
  316. return 0; /* nothing to do */
  317. return -EINVAL;
  318. }
  319. static int stm32mp_bsec_read(struct udevice *dev, int offset,
  320. void *buf, int size)
  321. {
  322. int ret;
  323. int i;
  324. bool shadow = true, lock = false;
  325. int nb_otp = size / sizeof(u32);
  326. int otp;
  327. unsigned int offs = offset;
  328. if (offs >= STM32_BSEC_LOCK_OFFSET) {
  329. offs -= STM32_BSEC_LOCK_OFFSET;
  330. lock = true;
  331. } else if (offs >= STM32_BSEC_OTP_OFFSET) {
  332. offs -= STM32_BSEC_OTP_OFFSET;
  333. shadow = false;
  334. }
  335. if ((offs % 4) || (size % 4))
  336. return -EINVAL;
  337. otp = offs / sizeof(u32);
  338. for (i = otp; i < (otp + nb_otp) && i <= BSEC_OTP_MAX_VALUE; i++) {
  339. u32 *addr = &((u32 *)buf)[i - otp];
  340. if (lock)
  341. ret = stm32mp_bsec_read_lock(dev, addr, i);
  342. else if (shadow)
  343. ret = stm32mp_bsec_read_shadow(dev, addr, i);
  344. else
  345. ret = stm32mp_bsec_read_otp(dev, addr, i);
  346. if (ret)
  347. break;
  348. }
  349. if (ret)
  350. return ret;
  351. else
  352. return (i - otp) * 4;
  353. }
  354. static int stm32mp_bsec_write(struct udevice *dev, int offset,
  355. const void *buf, int size)
  356. {
  357. int ret = 0;
  358. int i;
  359. bool shadow = true, lock = false;
  360. int nb_otp = size / sizeof(u32);
  361. int otp;
  362. unsigned int offs = offset;
  363. if (offs >= STM32_BSEC_LOCK_OFFSET) {
  364. offs -= STM32_BSEC_LOCK_OFFSET;
  365. lock = true;
  366. } else if (offs >= STM32_BSEC_OTP_OFFSET) {
  367. offs -= STM32_BSEC_OTP_OFFSET;
  368. shadow = false;
  369. }
  370. if ((offs % 4) || (size % 4))
  371. return -EINVAL;
  372. otp = offs / sizeof(u32);
  373. for (i = otp; i < otp + nb_otp && i <= BSEC_OTP_MAX_VALUE; i++) {
  374. u32 *val = &((u32 *)buf)[i - otp];
  375. if (lock)
  376. ret = stm32mp_bsec_write_lock(dev, *val, i);
  377. else if (shadow)
  378. ret = stm32mp_bsec_write_shadow(dev, *val, i);
  379. else
  380. ret = stm32mp_bsec_write_otp(dev, *val, i);
  381. if (ret)
  382. break;
  383. }
  384. if (ret)
  385. return ret;
  386. else
  387. return (i - otp) * 4;
  388. }
  389. static const struct misc_ops stm32mp_bsec_ops = {
  390. .read = stm32mp_bsec_read,
  391. .write = stm32mp_bsec_write,
  392. };
  393. static int stm32mp_bsec_of_to_plat(struct udevice *dev)
  394. {
  395. struct stm32mp_bsec_plat *plat = dev_get_plat(dev);
  396. plat->base = (u32)dev_read_addr_ptr(dev);
  397. return 0;
  398. }
  399. static int stm32mp_bsec_probe(struct udevice *dev)
  400. {
  401. int otp;
  402. struct stm32mp_bsec_plat *plat;
  403. struct clk_bulk clk_bulk;
  404. int ret;
  405. ret = clk_get_bulk(dev, &clk_bulk);
  406. if (!ret) {
  407. ret = clk_enable_bulk(&clk_bulk);
  408. if (ret)
  409. return ret;
  410. }
  411. /*
  412. * update unlocked shadow for OTP cleared by the rom code
  413. * only executed in U-Boot proper when TF-A is not used
  414. */
  415. if (!IS_ENABLED(CONFIG_TFABOOT) && !IS_ENABLED(CONFIG_SPL_BUILD)) {
  416. plat = dev_get_plat(dev);
  417. for (otp = 57; otp <= BSEC_OTP_MAX_VALUE; otp++)
  418. if (!bsec_read_SR_lock(plat->base, otp))
  419. bsec_shadow_register(dev, plat->base, otp);
  420. }
  421. return 0;
  422. }
  423. static const struct udevice_id stm32mp_bsec_ids[] = {
  424. { .compatible = "st,stm32mp15-bsec" },
  425. {}
  426. };
  427. U_BOOT_DRIVER(stm32mp_bsec) = {
  428. .name = "stm32mp_bsec",
  429. .id = UCLASS_MISC,
  430. .of_match = stm32mp_bsec_ids,
  431. .of_to_plat = stm32mp_bsec_of_to_plat,
  432. .plat_auto = sizeof(struct stm32mp_bsec_plat),
  433. .ops = &stm32mp_bsec_ops,
  434. .probe = stm32mp_bsec_probe,
  435. };
  436. bool bsec_dbgswenable(void)
  437. {
  438. struct udevice *dev;
  439. struct stm32mp_bsec_plat *plat;
  440. int ret;
  441. ret = uclass_get_device_by_driver(UCLASS_MISC,
  442. DM_DRIVER_GET(stm32mp_bsec), &dev);
  443. if (ret || !dev) {
  444. log_debug("bsec driver not available\n");
  445. return false;
  446. }
  447. plat = dev_get_plat(dev);
  448. if (readl(plat->base + BSEC_DENABLE_OFF) & BSEC_DENABLE_DBGSWENABLE)
  449. return true;
  450. return false;
  451. }