cmd_ddrphy.c 7.0 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2014 Panasonic Corporation
  4. * Copyright (C) 2015-2017 Socionext Inc.
  5. * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
  6. */
  7. #include <common.h>
  8. #include <command.h>
  9. #include <stdio.h>
  10. #include <linux/io.h>
  11. #include <linux/printk.h>
  12. #include <linux/sizes.h>
  13. #include "../soc-info.h"
  14. #include "ddrphy-regs.h"
  15. /* Select either decimal or hexadecimal */
  16. #if 1
  17. #define PRINTF_FORMAT "%2d"
  18. #else
  19. #define PRINTF_FORMAT "%02x"
  20. #endif
  21. /* field separator */
  22. #define FS " "
  23. #define ptr_to_uint(p) ((unsigned int)(unsigned long)(p))
  24. #define UNIPHIER_MAX_NR_DDRPHY 4
  25. struct uniphier_ddrphy_param {
  26. unsigned int soc_id;
  27. unsigned int nr_phy;
  28. struct {
  29. resource_size_t base;
  30. unsigned int nr_dx;
  31. } phy[UNIPHIER_MAX_NR_DDRPHY];
  32. };
  33. static const struct uniphier_ddrphy_param uniphier_ddrphy_param[] = {
  34. {
  35. .soc_id = UNIPHIER_LD4_ID,
  36. .nr_phy = 2,
  37. .phy = {
  38. { .base = 0x5bc01000, .nr_dx = 2, },
  39. { .base = 0x5be01000, .nr_dx = 2, },
  40. },
  41. },
  42. {
  43. .soc_id = UNIPHIER_PRO4_ID,
  44. .nr_phy = 4,
  45. .phy = {
  46. { .base = 0x5bc01000, .nr_dx = 2, },
  47. { .base = 0x5bc02000, .nr_dx = 2, },
  48. { .base = 0x5be01000, .nr_dx = 2, },
  49. { .base = 0x5be02000, .nr_dx = 2, },
  50. },
  51. },
  52. {
  53. .soc_id = UNIPHIER_SLD8_ID,
  54. .nr_phy = 2,
  55. .phy = {
  56. { .base = 0x5bc01000, .nr_dx = 2, },
  57. { .base = 0x5be01000, .nr_dx = 2, },
  58. },
  59. },
  60. {
  61. .soc_id = UNIPHIER_LD11_ID,
  62. .nr_phy = 1,
  63. .phy = {
  64. { .base = 0x5bc01000, .nr_dx = 4, },
  65. },
  66. },
  67. };
  68. UNIPHIER_DEFINE_SOCDATA_FUNC(uniphier_get_ddrphy_param, uniphier_ddrphy_param)
  69. static void print_bdl(void __iomem *reg, int n)
  70. {
  71. u32 val = readl(reg);
  72. int i;
  73. for (i = 0; i < n; i++)
  74. printf(FS PRINTF_FORMAT, (val >> i * 6) & 0x3f);
  75. }
  76. static void dump_loop(const struct uniphier_ddrphy_param *param,
  77. void (*callback)(void __iomem *))
  78. {
  79. void __iomem *phy_base, *dx_base;
  80. int phy, dx;
  81. for (phy = 0; phy < param->nr_phy; phy++) {
  82. phy_base = ioremap(param->phy[phy].base, SZ_4K);
  83. dx_base = phy_base + PHY_DX_BASE;
  84. for (dx = 0; dx < param->phy[phy].nr_dx; dx++) {
  85. printf("PHY%dDX%d:", phy, dx);
  86. (*callback)(dx_base);
  87. dx_base += PHY_DX_STRIDE;
  88. printf("\n");
  89. }
  90. iounmap(phy_base);
  91. }
  92. }
  93. static void __wbdl_dump(void __iomem *dx_base)
  94. {
  95. print_bdl(dx_base + PHY_DX_BDLR0, 5);
  96. print_bdl(dx_base + PHY_DX_BDLR1, 5);
  97. printf(FS "(+" PRINTF_FORMAT ")",
  98. readl(dx_base + PHY_DX_LCDLR1) & 0xff);
  99. }
  100. static void wbdl_dump(const struct uniphier_ddrphy_param *param)
  101. {
  102. printf("\n--- Write Bit Delay Line ---\n");
  103. printf(" DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM DQS (WDQD)\n");
  104. dump_loop(param, &__wbdl_dump);
  105. }
  106. static void __rbdl_dump(void __iomem *dx_base)
  107. {
  108. print_bdl(dx_base + PHY_DX_BDLR3, 5);
  109. print_bdl(dx_base + PHY_DX_BDLR4, 4);
  110. printf(FS "(+" PRINTF_FORMAT ")",
  111. (readl(dx_base + PHY_DX_LCDLR1) >> 8) & 0xff);
  112. }
  113. static void rbdl_dump(const struct uniphier_ddrphy_param *param)
  114. {
  115. printf("\n--- Read Bit Delay Line ---\n");
  116. printf(" DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM (RDQSD)\n");
  117. dump_loop(param, &__rbdl_dump);
  118. }
  119. static void __wld_dump(void __iomem *dx_base)
  120. {
  121. int rank;
  122. u32 lcdlr0 = readl(dx_base + PHY_DX_LCDLR0);
  123. u32 gtr = readl(dx_base + PHY_DX_GTR);
  124. for (rank = 0; rank < 4; rank++) {
  125. u32 wld = (lcdlr0 >> (8 * rank)) & 0xff; /* Delay */
  126. u32 wlsl = (gtr >> (12 + 2 * rank)) & 0x3; /* System Latency */
  127. printf(FS PRINTF_FORMAT "%sT", wld,
  128. wlsl == 0 ? "-1" : wlsl == 1 ? "+0" : "+1");
  129. }
  130. }
  131. static void wld_dump(const struct uniphier_ddrphy_param *param)
  132. {
  133. printf("\n--- Write Leveling Delay ---\n");
  134. printf(" Rank0 Rank1 Rank2 Rank3\n");
  135. dump_loop(param, &__wld_dump);
  136. }
  137. static void __dqsgd_dump(void __iomem *dx_base)
  138. {
  139. int rank;
  140. u32 lcdlr2 = readl(dx_base + PHY_DX_LCDLR2);
  141. u32 gtr = readl(dx_base + PHY_DX_GTR);
  142. for (rank = 0; rank < 4; rank++) {
  143. u32 dqsgd = (lcdlr2 >> (8 * rank)) & 0xff; /* Delay */
  144. u32 dgsl = (gtr >> (3 * rank)) & 0x7; /* System Latency */
  145. printf(FS PRINTF_FORMAT "+%dT", dqsgd, dgsl);
  146. }
  147. }
  148. static void dqsgd_dump(const struct uniphier_ddrphy_param *param)
  149. {
  150. printf("\n--- DQS Gating Delay ---\n");
  151. printf(" Rank0 Rank1 Rank2 Rank3\n");
  152. dump_loop(param, &__dqsgd_dump);
  153. }
  154. static void __mdl_dump(void __iomem *dx_base)
  155. {
  156. int i;
  157. u32 mdl = readl(dx_base + PHY_DX_MDLR);
  158. for (i = 0; i < 3; i++)
  159. printf(FS PRINTF_FORMAT, (mdl >> (8 * i)) & 0xff);
  160. }
  161. static void mdl_dump(const struct uniphier_ddrphy_param *param)
  162. {
  163. printf("\n--- Master Delay Line ---\n");
  164. printf(" IPRD TPRD MDLD\n");
  165. dump_loop(param, &__mdl_dump);
  166. }
  167. #define REG_DUMP(x) \
  168. { int ofst = PHY_ ## x; void __iomem *reg = phy_base + ofst; \
  169. printf("%3d: %-10s: %08x : %08x\n", \
  170. ofst >> PHY_REG_SHIFT, #x, \
  171. ptr_to_uint(reg), readl(reg)); }
  172. #define DX_REG_DUMP(dx, x) \
  173. { int ofst = PHY_DX_BASE + PHY_DX_STRIDE * (dx) + \
  174. PHY_DX_## x; \
  175. void __iomem *reg = phy_base + ofst; \
  176. printf("%3d: DX%d%-7s: %08x : %08x\n", \
  177. ofst >> PHY_REG_SHIFT, (dx), #x, \
  178. ptr_to_uint(reg), readl(reg)); }
  179. static void reg_dump(const struct uniphier_ddrphy_param *param)
  180. {
  181. void __iomem *phy_base;
  182. int phy, dx;
  183. printf("\n--- DDR PHY registers ---\n");
  184. for (phy = 0; phy < param->nr_phy; phy++) {
  185. phy_base = ioremap(param->phy[phy].base, SZ_4K);
  186. printf("== PHY%d (base: %08x) ==\n",
  187. phy, ptr_to_uint(phy_base));
  188. printf(" No: Name : Address : Data\n");
  189. REG_DUMP(RIDR);
  190. REG_DUMP(PIR);
  191. REG_DUMP(PGCR0);
  192. REG_DUMP(PGCR1);
  193. REG_DUMP(PGSR0);
  194. REG_DUMP(PGSR1);
  195. REG_DUMP(PLLCR);
  196. REG_DUMP(PTR0);
  197. REG_DUMP(PTR1);
  198. REG_DUMP(PTR2);
  199. REG_DUMP(PTR3);
  200. REG_DUMP(PTR4);
  201. REG_DUMP(ACMDLR);
  202. REG_DUMP(ACBDLR);
  203. REG_DUMP(DXCCR);
  204. REG_DUMP(DSGCR);
  205. REG_DUMP(DCR);
  206. REG_DUMP(DTPR0);
  207. REG_DUMP(DTPR1);
  208. REG_DUMP(DTPR2);
  209. REG_DUMP(MR0);
  210. REG_DUMP(MR1);
  211. REG_DUMP(MR2);
  212. REG_DUMP(MR3);
  213. for (dx = 0; dx < param->phy[phy].nr_dx; dx++) {
  214. DX_REG_DUMP(dx, GCR);
  215. DX_REG_DUMP(dx, GTR);
  216. }
  217. iounmap(phy_base);
  218. }
  219. }
  220. static int do_ddr(struct cmd_tbl *cmdtp, int flag, int argc,
  221. char *const argv[])
  222. {
  223. const struct uniphier_ddrphy_param *param;
  224. char *cmd;
  225. param = uniphier_get_ddrphy_param();
  226. if (!param) {
  227. pr_err("unsupported SoC\n");
  228. return CMD_RET_FAILURE;
  229. }
  230. if (argc == 1)
  231. cmd = "all";
  232. else
  233. cmd = argv[1];
  234. if (!strcmp(cmd, "wbdl") || !strcmp(cmd, "all"))
  235. wbdl_dump(param);
  236. if (!strcmp(cmd, "rbdl") || !strcmp(cmd, "all"))
  237. rbdl_dump(param);
  238. if (!strcmp(cmd, "wld") || !strcmp(cmd, "all"))
  239. wld_dump(param);
  240. if (!strcmp(cmd, "dqsgd") || !strcmp(cmd, "all"))
  241. dqsgd_dump(param);
  242. if (!strcmp(cmd, "mdl") || !strcmp(cmd, "all"))
  243. mdl_dump(param);
  244. if (!strcmp(cmd, "reg") || !strcmp(cmd, "all"))
  245. reg_dump(param);
  246. return CMD_RET_SUCCESS;
  247. }
  248. U_BOOT_CMD(
  249. ddr, 2, 1, do_ddr,
  250. "UniPhier DDR PHY parameters dumper",
  251. "- dump all of the following\n"
  252. "ddr wbdl - dump Write Bit Delay\n"
  253. "ddr rbdl - dump Read Bit Delay\n"
  254. "ddr wld - dump Write Leveling\n"
  255. "ddr dqsgd - dump DQS Gating Delay\n"
  256. "ddr mdl - dump Master Delay Line\n"
  257. "ddr reg - dump registers\n"
  258. );